IDT74FCT2533ATQ [IDT]
FAST CMOS OCTAL TRANSPARENT LATCHES; 快速CMOS八路透明锁存器
| 型号： | IDT74FCT2533ATQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL TRANSPARENT LATCHES |
| 文件： | 总8页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT
IDT54/74FCT533T/AT/CT
IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL
TRANSPARENT
LATCHES
Integrated Device Technology, Inc.
– Reduced system switching noise
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
The FCT373T/FCT2373T, FCT533T and FCT573T/
FCT2573T are octal transparent latches built using an ad-
vanced dual metal CMOS technology. These octal latches
have 3-state outputs and are intended for bus oriented appli-
cations. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OEis HIGH, the
bus output is in the high- impedance state.
The FCT2373T and FCT2573T have balanced drive out-
puts with current limiting resistors. This offers low ground
bounce, minimal undershoot and controlled output fall times-
reducing the need for external series terminating resistors.
The FCT2xxxT parts are plug-in replacements for FCTxxxT
parts.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT373T/FCT533T/FCT573T:
– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
• Features for FCT2373T/FCT2573T:
– Std., A and C speed grades
– Resistor output
(-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
2564 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
2564 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc.
6.12
DSC-4216/6
1
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373/2373T
INDEX
D
OE
1
20
19
18
17
VCC
O
7
O
0
2
3
4
D
D
7
6
3
2
20 19
D
0
P20-1
D20-1
1
4
5
6
7
8
18
1
D
D
7
6
D
1
17
16
15
14
O
1
2
O
O
6
5
O
O
1
2
5
SO20-2 16
SO20-7
SO20-8
O
O
O
6
5
L20-2
6
15
D
2
3
D
D
5
4
D
2
7
14
&
D
D
5
D
3
8
13
12
11
E20-1
9 10 11 12 13
O
3
9
O4
GND
10
LE
2564 cnv* 04
2564 cnv* 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT573/2573T
INDEX
1
20
19
18
17
VCC
OE
D0
2
3
4
O0
O1
O2
O3
O4
3
2
20 19
1
D1
D2
4
5
6
7
8
18
17
16
15
14
D2
O1
O2
O3
O4
O5
P20-1
D20-1
D3
D4
D3
D4
D5
D6
5
SO20-2 16
L20-2
SO20-7
SO20-8
6
15
D5
D6
7
14
O5
O6
&
8
13
12
11
9 10 11 12 13
E20-1
9
O7
LE
D7
GND
10
2564 cnv* 05
2564 cnv* 06
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT533
OE
INDEX
1
20
19
18
17
V
CC
O
0
O7
2
3
4
3
2
20 19
D
0
D
D
7
6
1
D1
4
5
6
7
8
18
17
16
15
14
D7
D6
D
1
P20-1
O1
O2
D2
D3
O
O
1
2
5
D20-1 16
O
O
6
5
SO20-2
L20-2
O6
O5
D5
6
15
&
14
D
D
2
3
7
D
D
5
4
E20-1
8
13
12
11
9 10 11 12 13
O
3
9
O4
GND
10
LE
2564 cnv* 07
2564 cnv* 08
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
6.12
2
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (533)(1)
FUNCTION TABLE (373 and 573)(1)
Inputs
Outputs
Inputs
Outputs
ON
DN
H
LE
H
N
O
DN
H
LE
H
OE
L
OE
L
L
H
L
L
H
L
H
Z
L
H
L
X
X
H
X
X
H
Z
NOTE:
2564 tbl 01
NOTE:
2564 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Z = High Impedance
DEFINITION OF FUNCTIONAL TERMS
Pin Names
Description
DN
Data Inputs
LE
OE
ON
ON
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
Complementary 3-State Outputs
2564 tbll 03
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2564 lnk 05
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2564 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.12
3
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
VIL
II H
II L
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
—
IOZH
IOZL
II
—
µA
—
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
mV
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
mA
2564 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
V
OH
Output HIGH Voltage
V
V
CC = Min.
IN = VIH or VIL
I
I
I
I
I
I
OH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
OH = –8mA COM'L.
OH = –12mA MIL.
OH = –15mA COM'L.
OL = 32mA MIL.
—
V
V
VOL
Output LOW Voltage
V
V
V
CC = Min.
IN = VIH or VIL
0.5
OL = 48mA COM'L.
I
I
OS
Short Circuit Current
Input/Output Power Off Leakage(5)
CC = Max., V
O
= GND(3)
–60
—
–120 –225
mA
OFF
V
CC = 0V, VIN or V
O
≤ 4.5V
—
±1
µA
2564 lnk 07
OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T
Symbol
Parameter
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
Min. Typ.(2) Max.
Unit
IODL
Output LOW Current
16
–16
2.4
48
–48
3.3
—
—
—
mA
IODH
VOH
Output HIGH Current
Output HIGH Voltage
mA
V
VCC = Min.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 12mA
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
—
0.3
0.50
V
VIN = VIH or VIL
2564 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.12
4
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = 3.4V(3)
—
—
—
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = GND
VIN = VCC FCTxxxT
VIN = GND
0.15
0.06
0.25
0.12
mA/
MHz
FCT2xxxT
One Input Toggling
50% Duty Cycle
VCC = Max.
IC
Total Power Supply Current(6)
VIN = VCC FCTxxxT
VIN = GND FCT2xxxT
—
—
1.5
0.6
3.5
2.2
mA
Outputs Open
fi = 10MHz
50% Duty Cycle
OE = GND
VIN = 3.4
VIN = GND
FCTxxxT
—
1.8
0.9
4.5
3.2
LE = VCC
FCT2xxxT
One Bit Toggling
VCC = Max.
VIN = VCC FCTxxxT
VIN = GND FCT2xxxT
—
—
3.0
1.2
6.0(5)
3.4(5)
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = GND
VIN = 3.4
VIN = GND
FCTxxxT
—
—
5.0
3.2
14.0(5)
11.4(5)
LE = VCC
FCT2xxxT
Eight Bits Toggling
2564 tbl 09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.12
5
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT373T/2373T/573T/2573T
FCT373AT/2373AT/573AT/2573AT
Com'l.
Mil.
Com'l.
Mil.
(2)
(2)
(2)
(2)
Symbol
PLH
Parameter
Conditions(1)
= 50pF
= 500
Min
.
Max
.
Min
.
Max
.
Min
.
Max
.
Min
.
Max
.
Unit
t
t
Propagation Delay
C
L
1.5
8.0
1.5
8.5
1.5
5.2
1.5
5.6
ns
PHL
D
N
to O
Propagation Delay
LE to O
N
R
L
Ω
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
SU
2.0
1.5
1.5
2.0
1.5
6.0
13.0
12.0
7.5
—
2.0
1.5
1.5
2.0
1.5
6.0
15.0
13.5
10.0
—
2.0
1.5
1.5
2.0
1.5
5.0
8.5
6.5
5.5
—
2.0
1.5
1.5
2.0
1.5
6.0
9.8
7.5
6.5
—
ns
ns
ns
ns
ns
N
Output Enable Time
Output Disable Time
Set-up Time HIGH
or LOW, D
Hold Time HIGH
or LOW, D to LE
N to LE
t
H
—
—
—
—
N
t
W
LE Pulse Width HIGH
—
—
—
—
ns
2564 tbl 10
FCT373CT/2373CT/573CT/2573CT
Com'l. Mil.
FCT373DT/573DT
Com'l. Mil.
Symbol
Parameter
Propagation Delay
DN to ON
Conditions(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
1.5
4.2
1.5
5.1
1.5
3.8
—
—
ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
LE to ON
2.0
1.5
1.5
2.0
1.5
5.0
5.5
5.5
5.0
—
2.0
1.5
1.5
2.0
1.5
6.0
8.0
6.3
5.9
—
2.0
1.5
1.5
1.5
1.0
3.0
4.0
4.8
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
Output Enable Time
Output Disable Time
tSU
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH(3)
tH
—
—
—
tW
—
—
—
ns
2564 tbl 11
FCT533T
Com'l.
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
FCT533AT
FCT533CT
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Propagation Delay
DN to ON
tPLH
tPHL
CL = 50pF
1.5 10.0 1.5 12.0 1.5
5.2 1.5
5.6 1.5
4.2 1.5
5.1 ns
RL = 500Ω
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
LE to ON
2.0 13.0 2.0 14.0 2.0
1.5 11.0 1.5 12.5 1.5
8.5 2.0
6.5 1.5
5.5 1.5
9.8 2.0
7.5 1.5
6.5 1.5
5.5 2.0
5.5 1.5
5.0 1.5
8.0 ns
6.3 ns
5.9 ns
Output Enable
Time
Output Disable
Time
1.5
2.0
1.5
6.0
7.0 1.5
8.5
—
—
—
1.5
2.0
1.5
5.0
tSU
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
5.0
—
—
—
2.0
1.5
6.0
—
—
—
ns
ns
ns
tH
tW
NOTES:
2564 tbl 12
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
6.12
6
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500
Ω
Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
2564 lnk 13
D.U.T.
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
500
T
R
Generator.
C
L
2564 drw 09
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
t
t
SU
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
t
W
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
2564 drw 11
CLEAR
CLOCK ENABLE
ETC.
SU
t
H
2564 drw 10
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
V
OL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
V
OH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2564 drw 12
0V
2564 drw 13
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.12
7
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
X
Temp. Range
Device Type
Package
Process
Family
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Small Outline IC
Leadless Chip Carrier
CERPACK
PY
Q
Shrink Small Outline Package
Quarter-size Small Outline Package
373T
573T
533T
Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch
Inverting Octal Transparent Latch
373AT
573AT
533AT
373CT
573CT
533CT
373DT
573DT
Blank
2
High Drive
Balanced Drive
54
74
–55°C to +125°C
0°C to +70°C
2564 drw 14
6.12
8
相关型号：
IDT74FCT2533CTLG
Bus Driver, FCT Series, 1-Func, 8-Bit, Inverted Output, CMOS, CQCC20, LCC-20
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IDT
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