IDT74FCT273TLB [IDT]
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET; 快速CMOS八路D触发器与主复位
| 型号： | IDT74FCT273TLB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT273T/AT/CT
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
Integrated Device Technology, Inc.
DESCRIPTION:
FEATURES:
The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT273T/AT/CT have eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
• Std., A, and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D3
D4
D
5
D
6
D7
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
R
D
R
D
RD
RD
R
D
R
D
RD
RD
MR
O
0
O
1
O2
O
3
O
4
O
5
O6
O7
2568 drw 03
PIN CONFIGURATIONS
INDEX
1
20
19
18
17
16
15
14
13
12
11
VCC
O7
D7
MR
O0
2
3
4
3
2
20 19
D0
D1
P20-1
D20-1
SO20-2
SO20-8
&
1
D
1
4
18
D7
D6
O
1
2
5
6
7
8
17
16
15
14
D
6
O1
O2
D2
D3
5
O6
O5
O
O
6
5
L20-2
6
D
2
3
O
7
D5
D4
E20-1
D
D5
8
9 10 11 12 13
9
O3
GND
O4
10
CP
2568 drw 01
2568 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
1995 Integrated Device Technology, Inc.
6.10
DSC-4209/3
1
IDT54/74FCT273T/AT/CT FAST CMOS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTAL D FLIP-FLOP WITH MASTER RESET
PIN DESCRIPTION
FUNCTION TABLE(1)
Pin Names
Description
Inputs
CP
Outputs
ON
DN
Data Inputs
Operating Mode
Reset (Clear)
Load "1"
DN
X
h
MR
L
MR
CP
ON
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
X
↑
L
H
L
H
H
Load "0"
↑
I
2568 tbl 01
NOTE:
1. H = HIGH voltage level steady state
2568 tbl 02
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input
Capacitance
Output
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
CIN
VIN = 0V
6
10
pF
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
COUT
VOUT = 0V
8
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5
–0.5 to
VCC +0.5
V
Capacitance
2568 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2568 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.10
2
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
±1
V
VIL
II H
II L
Input LOW Level
Guaranteed Logic LOW Level
V
µA
µA
µA
V
Input HIGH Current(4)
Input LOW Current(4)
Input HIGH Current(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
—
—
—
—
±1
II
VCC = Max., VI = VCC (Max.)
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
—
±1
VIK
IOS
VOH
—
–0.7
–1.2
–60
2.4
–120 –225
mA
V
VCC = Min.
IOH = –6mA MIL.
3.3
3.0
0.3
—
VIN = VIH or VIL
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 32mA MIL.
2.0
—
—
V
V
VOL
Output LOW Voltage
VCC = Min.
0.5
VIN = VIH or VIL
IOL = 48mA COM'L.
VH
Input Hysteresis
—
—
—
200
—
1
mV
mA
ICC
Quiescent Power Supply Current
VCC = Max.
0.01
VIN = GND or VCC
NOTES:
2568 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test parameter for this parameter is ±5µA at TA = -55°C.
6.10
3
IDT54/74FCT273T/AT/CT FAST CMOS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTAL D FLIP-FLOP WITH MASTER RESET
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
MR = VCC
∆ICC
—
—
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current(4)
VIN = VCC
VIN = GND
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
MR = VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
MR = VCC
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
IC
Total Power Supply Current(6)
VIN = VCC
VIN = GND
—
—
—
—
1.5
2.0
3.8
6.0
3.5
5.5
mA
VIN = 3.4V
VIN = GND
VIN = VCC
VIN = GND
7.35)
VIN = 3.4V
VIN = GND
16.3(5)
NOTES:
2568 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.10
4
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273T
IDT54/74FCT273AT
IDT54/74FCT273CT
Com'l. Mil.
Com'l. Mil.
Com'l. Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
CP to ON
Condition(1)
CL = 50pF
Unit
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 5.8 2.0 6.5 ns
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 6.1 2.0 6.8 ns
RL = 500Ω
tPHL
Propagation Delay
MR to ON
tSU
Set-up Time HIGH or LOW
DN to CP
3.0
2.0
7.0
7.0
4.0
—
—
—
—
—
3.5
2.0
7.0
7.0
5.0
—
—
—
—
—
2.0
1.5
6.0
6.0
2.0
—
—
—
—
—
2.0
1.5
6.0
6.0
2.5
—
—
—
—
—
2.0
1.5
6.0
6.0
2.0
—
—
—
—
—
2.0
1.5
6.0
6.0
2.5
—
—
—
—
—
ns
ns
ns
ns
tH
Hold Time HIGH or LOW DN
to CP
tW
CP Pulse Width HIGH or
LOW
tW
MR Pulse Width LOW
tREM
NOTES:
Recovery Time MR
to CP
ns
2568 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.10
5
IDT54/74FCT273T/AT/CT FAST CMOS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTAL D FLIP-FLOP WITH MASTER RESET
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500Ω
500Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
D.U.T.
2568 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
C L
T
R
Generator.
2568 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
2568 drw 06
3V
PRESET
CLEAR
CLOCK ENABLE
ETC.
1.5V
0V
tSU
tH
2568 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2568 drw 07
0V
2568 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.10
6
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXX
FCT
XXXX
X
X
X
Temp. Range
Family
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Small Outline IC
Leadless Chip Carrier
CERPACK
Q
Quarter-size Small Outline Package
273T
Octal D Flip-Flop w/Clear
273AT
273CT
Blank
High Drive
54
74
–55
°C to +125°C
0°
C to +70°C
2568 drw 09
6.10
7
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