IDT74FCT3573AQ8 [IDT]
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, QSOP-20;
| 型号： | IDT74FCT3573AQ8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, QSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS OCTAL
IDT74FCT3573/A
TRANSPARENT
LATCH
DESCRIPTION:
FEATURES:
The FCT3573/A are octal transparent latches built using an advanced
dual metal CMOS technology.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ±0.3V, Normal Range
These octal latches have 3-state outputs and are intended for bus
oriented applications. The flip-flops appear transparent to the data when
Latch Enable (LE) is high. When LE is low, the data that meets the set-up
time is latched. Data appears on the bus when the Output Enable (OE) is
low. When OE is high, the bus output is in the high-impedance state.
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in QSOP, SOIC, and TSSOP packages
FUNCTIONALBLOCKDIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
G
G
G
G
G
G
G
G
LE
OE
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2000
1
© 2000 Integrated Device Technology, Inc.
DSC-5418/4
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol Description
Max
Unit
V
(2)
1
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
VTERM
VTERM
VTERM
TerminalVoltagewithRespecttoGND
TerminalVoltagewithRespecttoGND
–0.5 to +4.6
–0.5 to +7
OE
(3)
(4)
V
2
3
4
D0
D1
D2
TerminalVoltagewithRespecttoGND –0.5toVCC+0.5
V
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–65to+150
–60to+60
°C
mA
5
D3
D4
NOTES:
6
Q4
Q5
Q6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
7
D5
D6
8
9
Q7
LE
D7
2. VCC terminals.
3. Input terminals.
GND
10
4. Outputs and I/O terminals.
QSOP/ SOIC/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
3.5
4
Max. Unit
CIN
VIN = 0V
6
8
pF
pF
COUT
VOUT = 0V
NOTE:
1. This parameter is measured at characterization but not tested.
PINDESCRIPTION
Pin Names
Description
DX
LE
DataInputs
Latch Enable Input (Active HIGH)
OutputEnableInput(ActiveLOW)
3-StateOutputs
OE
QX
FUNCTIONTABLE(1)
Inputs
Outputs
Dx
H
L
LE
H
OE
L
Qx
H
H
L
L
X
X
H
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
2
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = -40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
5.5
Unit
VIH
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
InputLOWLevel
V
2
—
Vcc+0.5
0.8
VIL
IIH
IIL
GuaranteedLogicLOWLevel
VCC = Max.
–0.5
—
V
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
InputLOWCurrent(Inputpins)
Input LOW Current (I/O pins)
HighImpedanceOutputCurrent
(3-StateOutputpins)
VI = 5.5V
VI = VCC
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
µA
VI = GND
VI = GND
VO = VCC
VO = GND
—
—
IOZH
IOZL
VIK
VCC = Max.
—
µA
—
ClampDiodeVoltage
VCC = Min., IIN = –18mA
—
V
IODH
IODL
VOH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
50
mA
mA
V
OutputLOWCurrent
Output HIGH Voltage
VCC = Min.
IOH = –0.1mA
VCC–0.2
2.4
2.4(5)
VIN = VIH or VIL
VCC = 3V
IOH = –3mA
IOH = –8mA
—
3
—
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
0.2
0.3
0.3
0.2
0.4
V
VIN = VIH or VIL
0.55
0.5
VCC = 3V
VIN = VIH or VIL
IOS
VH
ShortCircuitCurrent(4)
InputHysteresis
VCC = Max., VO = GND(3)
–60
—
–135
150
0.1
–240
—
mA
mV
µA
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
10
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC - 0.6V at rated current.
3
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VIN = VCC - 0.6V
Min.
—
Typ.(2)
Max.
30
Unit
ICC
Quiescent Power Supply Current
VCC = Max.
2
µA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = GND
VIN = VCC
VIN = GND
—
60
85
µA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fI = 10MHz
VIN = VCC
VIN = GND
—
—
0.6
0.6
0.9
0.9
mA
50% Duty Cycle
OE = GND
LE = VCC
VIN = VCC - 0.6V
VIN = GND
One Bit Toggling
VCC = Max.
Outputs Open
fI = 2.5MHz
VIN = VCC
VIN = GND
—
—
1.2
1.2
1.7(5)
1.8(5)
50% Duty Cycle
OE = GND
LE = VCC
VIN = VCC - 0.6V
VIN = GND
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICC, ICCH, and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for register devices (zero for non-register devices)
NCP = Number of clock inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)
74FCT3573
74FCT3573A
Symbol
tPLH
Parameter
PropagationDelay
Dx to Qx
Condition(2)
CL = 50pF
RL = 500Ω
Min.(3)
Max.
Min.(3)
Max.
Unit
1.5
8
1.5
5.2
ns
tPHL
tPLH
PropagationDelay
LE to Qx
2
13
12
2
8.5
6.5
5.5
ns
ns
ns
tPHL
tPZH
tPZL
OutputEnableTime
1.5
1.5
1.5
1.5
tPHZ
tPLZ
OutputDisableTime
7.5
tSU
Set-up Time HIGH or LOW, DX to LE
Hold Time HIGH or LOW, DX to LE
LE Pulse Width HIGH
2
1.5
6
—
—
—
2
1.5
5
—
—
—
ns
ns
ns
tH
tW
NOTES:
1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/
Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
5
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
6v
VCC
SWITCHPOSITION
Open
Test
Switch
6V
GND
500Ω
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T.
Disable High
Enable High
GND
Open
50pF
T
R
L
C
All Other Tests
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tSU
tH
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
1.5V
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
CONTROL
INPUT
1.5V
0V
tPZL
tPLZ
3V
1.5V
0V
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SAME PHASE
SWITCH
6V
INPUT TRANSITION
0.3V
0.3V
VOL
VOH
tPLH
tPLH
tPHL
tPHL
VOH
1.5V
VOL
tPZH
tPHZ
OUTPUT
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
3V
1.5V
0V
0V
OPPOSITE PHASE
INPUT TRANSITION
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If Vcc is below 3V, input voltage swings should be adjusted not to exceed Vcc.
6
IDT74FCT3573/A
3.3VCMOSOCTALTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
X
XX
X
Temp. Range
Family
Device Type
Package
SO
Q
PG
Small Outline IC
Quarter-size Small Outline Package
Thin Shrink Small Outline Package
573
573A
Octal Transparent Latch
3.3 Volt
3
74
- 40°C to +85°C
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7
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