IDT74FCT374LB [IDT]
FAST CMOS OCTAL D REGISTERS (3-STATE); 快速CMOS八路D寄存器（三态）
| 型号： | IDT74FCT374LB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL D REGISTERS (3-STATE) |
| 文件： | 总8页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT374/A/C
IDT54/74FCT534/A/C
IDT54/74FCT574/A/C
FAST CMOS OCTAL D
REGISTERS (3-STATE)
Integrated Device Technology, Inc.
FEATURES:
• IDT54/74FCT374/534/574 equivalent to FAST speed
DESCRIPTION:
The IDT54/74FCT374/A/C, IDT54/74FCT534/A/C and
IDT54/74FCT574/A/C are 8-bit registers built using an ad-
vanceddualmetalCMOStechnology.Theseregistersconsist
of eight D-type flip-flops with a buffered common clock and
buffered 3-state output control. When the output enable (OE)
is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the O outputs on the LOW-to-
HIGH transition of the clock input.
and drive
• IDT54/74FCT374A/534A/574A up to 30% faster than
FAST
• IDT54/74FCT374C/534C/574C up to 50% faster than
FAST
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common three-
state control
TheIDT54/74FCT374/A/CandIDT54/74FCT574/A/Chave
non-inverting outputs with respect to the data at the D inputs.
The IDT54/74FCT534/A/C have inverting outputs.
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
O0
O1
O2
O3
O4
O5
O6
O7
2603 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2603 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.13
DSC-4622/2
1
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT374
INDEX
D
1
20
19
18
17
16
15
14
13
12
11
VCC
OE
O
0
2
3
4
O7
D
D
7
6
D
0
3
2
20 19
D
1
1
P20-1
D20-1
SO20-2
&
4
5
6
7
8
18
D
D
7
6
1
O
O
1
2
5
O
O
6
5
17
16
15
14
O
1
2
6
O
O
6
5
O
L20-2
D
2
7
D
D
5
4
E20-1
D
2
3
D
3
8
D
D
5
9 10 11 12 13
9
O
3
O4
GND
10
CP
2603 cnv* 03
2603 cnv* 04
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT574
INDEX
1
20
19
18
17
VCC
OE
3
2
2 1
D
0
2
3
4
O
O
O
O
O
0
1
2
3
4
1
4
5
6
7
8
1
1
1
1
1
D
D
D
2
3
4
O1
O2
O3
O4
O5
D
D
1
2
P20-1
L20-2
D
D
D
D
D
3
4
5
6
7
5
D20-1 16
SO20-2
D5
6
6
15
&
14
D
7
O
O
5
6
E20-1
9 1
1
1 1
8
13
12
11
9
O
7
GND
10
CP
2603 cnv* 05
2603 cnv* 06
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
IDT54/74FCT534
INDEX
OE
1
20
19
18
17
16
15
14
13
12
11
V
CC
O
0
O
7
2
3
4
3
2
20 19
D
D
0
1
D
D
7
6
1
D1
4
5
6
7
8
18
D7
D6
P20-1
D20-1
SO20-2
&
17
16
15
14
O1
O2
D2
D3
O
O
1
2
5
O
O
6
5
L20-2
O6
O5
D5
6
D
D
2
3
7
D
D
5
4
E20-1
8
9 10 11 12 13
O
3
9
O4
GND
10
CP
2603 cnv* 07
2603 cnv* 08
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
7.13
2
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
Description
DN
D flip-flop data inputs.
CP
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
ON
ON
OE
3-state outputs, (true).
3-state outputs, (inverted).
Active LOW 3-state Output Enable input.
2603 tbl 06
FUNCTION TABLE(1)
FCT534
Outputs
FCT374/574
Outputs Internal
Inputs
CP
Internal
QN
Function
Hi-Z
DN
N
O
ON
N
Q
OE
H
H
L
L
H
H
L
H
X
X
L
H
L
Z
NC
NC
L
H
L
Z
Z
L
H
Z
Z
NC
NC
H
L
H
Z
H
L
Z
Z
Load Register
H
H
L
NOTE:
2603 tbl 05
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
= LOW-to-HIGH transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions
IN = 0V
Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
C
IN
Input
Capacitance
Output
V
6
10
pF
C
OUT
VOUT = 0V
8
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to VCC
0 to +70
–0.5 to VCC
V
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
2603 tbl 02
TA
Operating
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
120
120
mA
NOTES:
2603 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditionsforextendedperiodsmayaffectreliability. Noterminalvoltagemay
exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.13
3
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
5
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
VCC = Max.
VI = VCC
—
—
µA
VI = 2.7V
VI = 0.5V
VI = GND
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
—
—
5(4)
–5(4)
–5
II L
Input LOW Current
—
—
—
—
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
—
—
10
µA
—
—
10(4)
–10(4)
–10
–1.2
—
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
V
mA
V
–60
VHC
VHC
2.4
2.4
—
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
VCC = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
—
—
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
(4)
V
VCC = Min.
IOL = 300µA
—
GND VLC
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM'L.
—
0.3
0.3
0.5
0.5
—
NOTES:
2603 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.13
4
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current
VCC = Max.
VIN ≥ VHC; V IN ≤ VLC
ICC
—
0.2
1.5
mA
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
∆ICC
—
—
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = GND
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
1.7
2.2
4.0
6.0
mA
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = GND
VIN = 3.4V
VIN = GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling
VCC = Max.
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
4.0
6.2
7.8(5)
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
16.8(5)
50% Duty Cycle
NOTES:
2603 tbl 04
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.13
5
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT374/534/574
Com'l. Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
FCT374A/534A/574A
FCT374C/534C/574C
Com'l. Mil.
Com'l. Mil.
Symbol
tPLH
Parameter
Conditions(1)
CL = 50pF
RL = 500Ω
Unit
Propagation Delay
2.0 10.0 2.0 11.0 2.0
1.5 12.5 1.5 14.0 1.5
6.5
2.0
7.2
2.0
5.2
2.0
6.2
ns
(3)
tPHL
CP to ON
tPZH
tPZL
tPHZ
tPLZ
tSU
Output Enable Time
Output Disable Time
6.5
5.5
—
1.5
1.5
2.0
1.5
6.0
7.5
6.5
—
1.5
1.5
2.0
1.5
5.0
5.5
5.0
—
1.5
1.5
2.0
1.5
6.0
6.2
5.7
—
ns
ns
ns
ns
ns
1.5
2.0
1.5
7.0
8.0
—
—
—
1.5
2.0
1.5
7.0
8.0
—
—
—
1.5
2.0
1.5
5.0
Set-up Time HIGH
or LOW, DN to CP
Hold Time HIGH
or LOW, DN to CP
CP Pulse Width
HIGH or LOW
tH
—
—
—
—
tW
—
—
—
—
NOTES:
2603 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. ON for FCT374 and FCT574, ON for FCT534.
7.13
6
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
C L
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2603 tbl 08
RT
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
tH
t SU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2603 drw 15
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.13
7
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
Temp. Range
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Small Outline IC
Leadless Chip Carrier
CERPACK
374
Non-Inverting Octal D Register
574
Non-Inverting Octal D Register
534
Inverting Octal D Register
374A
574A
534A
374C
574C
534C
Fast Non-Inverting Octal D Register
Fast Non-Inverting Octal D Register
Fast Inverting Octal D Register
Super Fast Non-Inverting Octal D Register
Super Fast Non-Inverting Octal D Register
Super Fast Inverting Octal D Register
54
74
–55°C to +125°C
0°C to +70°C
2603 cnv* 14
7.13
8
相关型号：
©2020 ICPDF网 联系我们和版权申明