IDT74FCT388915T133PYG [IDT]
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, SSOP-28;
| 型号： | IDT74FCT388915T133PYG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, SSOP-28 光电二极管 |
| 文件： | 总10页 (文件大小：1140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
IDT74FCT388915T
70/100/133/150
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT388915T uses phase-lock loop technology to lock the fre-
quencyandphase ofoutputs tothe inputreference clock. Itprovides low
skewclockdistributionforhighperformancePCsandworkstations. Oneof
the outputs is fed back to the PLL at the FEEDBACK input resulting in
essentiallyzerodelayacross the device. The PLLconsists ofthe phase/
frequency detector, charge pump, loop filter and VCO. The VCO is
designed for a 2Q operating frequency range of 40MHz to f2Q Max.
TheFCT388915Tprovides8outputs,theQ5outputisinvertedfromthe
Qoutputs. The 2Qruns attwice the QfrequencyandQ/2runs athalfthe
Qfrequency.
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x output,
one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Duty cycle distortion < 500ps (max.)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
The FREQ_SELcontrolprovides anadditional÷2optioninthe output
path. PLL _EN allows bypassing of the PLL, which is useful in static test
modes. WhenPLL_ENis low,SYNCinputmaybe usedas a testclock. In
this testmode,theinputfrequencyis notlimitedtothespecifiedrangeand
thepolarityofoutputsiscomplementarytothatinnormaloperation(PLL_EN
=1). The LOCKoutputattains logicHIGHwhenthe PLLis insteady-state
phase andfrequencylock. WhenOE/RST is low,allthe outputs are putin
highimpedance state andregisters atQ,Q andQ/2outputs are reset.
The FCT388915T requires one external loop filter component as
recommended in Figure 3.
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC and SSOP packages
FUNCTIONALBLOCKDIAGRAM
FEEDBACK
LOCK
Voltage
Controlled
Oscilator
Phase/Freq.
Detector
0 M
u
Charge Pump
SYNC (0)
SYNC (1)
x
1
LF
REF_SEL
PLL_EN
0
1
2Q
Mux
(÷1)
(÷2)
1
0
M
u
x
D
Q0
Q1
Q
CP
Q
R
R
R
R
R
R
R
Divide
-By-2
D
Q
Q
Q
Q
Q
Q
FREQ_SEL
OE/RST
CP
D
Q2
Q3
CP
D
CP
D
Q4
Q5
Q/2
CP
D
CP
D
CP
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
OCTOBER 2008
1
© 2004 Integrated Device Technology, Inc.
DSC-4243/7
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
1
2
3
28
27
26
GND
Q5
Q4
4
3
2
1
28 27 26
VCC
2Q
25 Q/2
FEEDBK
REF_SEL
SYNC(0)
VCC(AN)
LF
5
VCC
4
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
25
24
23
Q/2
GND
Q3
GND
24
6
5
23 Q3
7
6
7
22
21
20
19
18
17
VCC
VCC
8
22
21
20
19
8
Q2
Q2
9
9
GND
LOCK
GND(AN)
10
11
12
10
11
GND
LOCK
GND(AN)
SYNC(1)
SYNC(1)
FREQ_SEL
GND
PLL_EN
GND
12 13 14 15 16 17 18
13
14
16
15
Q1
VCC
Q0
SSOP
PLCC
TOP VIEW
TOP VIEW
PINDESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
I/O
I
Description
Referenceclockinput
Referenceclockinput
I
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selectsbetween÷1and÷2frequencyoptions(refertofunctionalblockdiagram)
Feedbackinputtophasedetector
I
I
I
Inputforexternalloopfilterconnection
Q0-Q4
O
O
O
O
O
I
Clockoutput
Q5
Invertedclockoutput
2Q
Clock output (2 x Q frequency)
Q/2
Clock output (Q frequency ÷ 2)
LOCK
Indicates phase lock has been achieved (HIGH when locked)
OE/RST
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in
HIGH impedance.
PLL_EN
I
Disablesphase-lockforlowfrequencytesting(refertofunctionalblockdiagram)
2
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
Symbol
Parameter
Conditions
Typ.
Max. Unit
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to +7
CIN
Input Capacitance
Output Capacitance
VIN = 0V
4.5
6
8
pF
pF
(3)
VTERM
V
COUT
VOUT = 0V
5.5
(4)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +60
° C
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
5.5
0.8
1
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
–36
50
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current(4)
(3-State Output Pins)
Clamp Diode Voltage
Output Drive Current
Output Drive Current
VI = 5.5V
VI = GND
VI = VCC
—
µA
µA
µA
IIL
VCC = Max.
—
1
IOZH
IOZL
VIK
VCC = Max.
—
1
VI = GND
—
1
VCC = Min., IIN = –18mA
–0.7
—
–1.2
—
—
V
(3)
IODH
IODL
VCC = Min., VIN = VIH or VIL, VO = 1.5V
mA
mA
(3)
VCC = Min., VIN = VIH or VIL, VO = 1.5V
—
VOH
VOL
VH
OutputHIGHVoltage
OutputLOWVoltage
VCC = Min
VCC = Min
IOH = –16mA
IOL = 32mA
2.4(4)
—
3.3
0.3
100
2
—
0.5
—
6
V
V
Input Hysteresis
—
—
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.,VIN = GND or VCC
(Test Mode)
—
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. VOH = VCC - 0.6V at rated current.
3
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VIN = VCC–0.6V
Min.
Typ.(2)
Max.
Unit
(3)
ΔICC
QuiescentPowerSupplyCurrent
TTL Inputs HIGH
VCC = Max.
—
2
30
µA
(3)
VIN = VCC –2.1V
VCC = Max.
ICCD
Dynamic Power Supply Current(4)
VIN = VCC
—
0.2
0.3
mA/
MHz
pF
AllOutputsOpen
50% Duty Cycle
VCC = Max.
VIN = GND
CPD
IC
PowerDissipationCapacitance
TotalPowerSupplyCurrent(6)
—
—
15
30
25
60
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 15pF
VCC = Max.
—
90
120
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 50Ω Thevenin
terminationand20pF
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q Frequency
ILOAD = Dynamic Current due to load.
SYNCHINPUTTIMINGREQUIRMENTS
Symbol Parameter
Min.
Max.
Unit
TRISE/FALL Rise/Fall Times, SYNC inputs
(0.8V to 2V)
—
3
ns
(1)
Frequency Input Frequency, SYNC Inputs
10
2Q fmax MHz
75%
Duty Cycle Input Duty Cycle, SYNC Inputs
25%
—
OUTPUTFREQUENCYSPECIFICATIONS
Max.(2)
Symbol
f2Q
Parameter
Min.
40
70
70
100
100
50
133(3)
133
150(3)
150
Unit
Operatingfrequency2QOutput
OperatingfrequencyQ0-Q4,Q5Outputs
OperatingfrequencyQ/2Output
MHz
MHz
MHz
fQ
20
35
66.7
33.3
75
fQ/2
10
17.5
25
37.5
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
3. At this frequency, 2Q cannot be used as feedback.
4
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
tRISE/FALL
AllOutputs
Parameter
Condition(1)
Min.
0.2(2)
Max.
Unit
Rise/FallTime
Load = 50Ω to VCC/2, CL = 20pF
2
ns
(between0.8Vand2V)
OutputPulseWidth
Q, Q, Q/2 outputs(3) Q0-Q4, Q5, Q/2, @ 1.5V
(3)
tPULSEWIDTH
Load = 50Ω to VCC/2, CL = 20pF
0.5tCYCLE–0.8(5) 0.5tCYCLE+0.8(5)
0.5tCYCLE–1(5) 0.5tCYCLE+1(5)
ns
ns
ns
ps
ps
ps
ms
tPULSEWIDTH
2QOutput(3)
tPD
OutputPulseWidth
2Q @ 1.5V
SYNC input to FEEDBACK delay
Load = 50Ω to VCC/2, CL = 20pF
+0.1
—
+1.3
600
250
800
10
(3)
(5)
SYNC-FEEDBACK (measured at SYNC0 or 1 and FEEDBACK input pins) 0.1µF from LF to Analog GND
tSKEWr
(3,4)
OutputtoOutputSkewbetweenoutputs 2Q,Q0-Q4,
Q/2(risingedges only)
Load = 50Ω to VCC/2, CL = 20pF
(rising)
tSKEWf
OutputtoOutputSkew
—
(3,4)
(falling)
betweenoutputsQ0-Q4(fallingedgesonly)
OutputtoOutputSkew
tSKEWall(3,4)
—
2Q, Q/2, Q0-Q4 rising, Q5 falling
TimerequiredtoacquirePhase-Lockfromtime
SYNC input signal is received
OutputEnableTime
(6)
(2)
tLOCK
1
(2)
tPZH
tPZL
tPHZ
tPLZ
3
14
14
ns
ns
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
OutputDisableTime
(2)
3
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter
capacitor shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration.
FREQ_SEL
Level
Feedback
Output
Q/2
Allowable SYNC Input
FrequencyRange(MHZ)
10to(2x_QfMAX Spec)/4
20 to (2x_Q fMAX Spec)/2
20 to (2x_Q fMAX Spec)/2
40 to (2x_Q fMAX Spec)
5 to (2x_Q fMAX Spec)/8
10 to (2x_QfMAX Spec)/4
10 to (2x_QfMAX Spec)/4
20 to (2x_Q fMAX Spec)/2
Corresponding 2Q Output
FrequencyRange
Phase Relationship of the Q Outputs
to Rising SYNC Edge
HIGH
HIGH
HIGH
HIGH
LOW
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
0°
0°
Any Q (Q0-Q4)
Q5
180°
0°
2X_Q
Q/2
0°
LOW
Any Q (Q0-Q4)
Q5
0°
LOW
180°
0°
LOW
2X_Q
5
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
GENERAL AC SPECIFICATION NOTES (continued):
8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and voltage. The
phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with
the loop filter connection shown in Figure 1 below:
External Loop
LF
Filter
C1
0.1μF
Analog GND
Figure 1
NOTES:
1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free
operation:
a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable
voltage transients at the LF pin.
b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage
transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 388915T's
digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional protection from the power supply and ground plane transients
that can occur in a high frequency, high speed digital system.
c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of Figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board
ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass
capacitors should also be tied as close to the 388915T package as possible.
BOARD VCC
ANALOG VCC
Analog loop filter section
of the FCT388915T
10μF
Low
0.1μF
High
LF
Freq.
Bypass
Freq.
Bypass
0.1μF (Loop
Filter Cap)
ANALOG GND
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the FCT388915T in a normal digital environment.
BOARD GND
Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T
6
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
ThefrequencyrelationshipshownhereisapplicabletoallQoutputs(Q0,Q1,
Q2, Q3 and Q4).
50 MHz signal
25 MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always runat2Xthe Q/2frequency, andthe 2Qoutputwillrunat4Xthe Q/2
Q4
2Q
OE/RST
Q5
12.5 MHz
signal
Q/2
Q3
FEEDBACK
LOW
REF_SEL
SYNC(0)
VCC(AN)
LF
25 MHz
input
25 MHz
"Q"
Clock
frequency.
FCT388915T
50 MHz signal
Outputs
12.5 MHz feedback signal
Q2
GND(AN)
HIGH
FQ_SEL
HIGH
Q0
Q1
PLL_EN
HIGH
2Q
Q/2
Q5
OE/RST
Q4
FEEDBACK
REF_SEL
LOW
12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
Q3
Q2
SYNC(0)
VCC(AN)
LF
AllowableInputFrequencyRange:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
FCT388915T
Figure 3b. Wiring Diagram and Frequency Relationships With
Q4 Output Feedback
GND(AN)
FQ_SEL
PLL_EN
HIGH
Q0
Q1
2:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
HIGH
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequencywillequaltheSYNCfrequency. TheQ/2 output willalwaysrunat
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
AllowableInputFrequencyRange:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
50 MHz feedback signal
HIGH
Figure 3a. Wiring Diagram and Frequency Relationships With Q/
2 Output Feedback
OE/RST
Q4
2Q
Q5
12.5 MHz
input
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
Q/2
LOW
50 MHz
input
25 MHz
Q3
"Q"
Clock
1:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
FCT388915T
Outputs
Q2
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency(andtherestofthe"Q"outputs)willequaltheSYNCfrequency. The
Q/2 output willalways runat1/2theQfrequency,andthe2Qoutputwillrun
at2Xthe Qfrequency.
GND(AN)
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
AllowableInputFrequencyRange:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With
2Q Output Feedback
7
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
FCT388915T
PLL
CLOCK
2f
@f
SYSTEM
CLOCK
SOURCE
CMMU
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
FCT388915T
PLL
2f
CMMU
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
FCT388915T
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
and Low Board-to-Board skew
FCT388915TSYSTEMLEVELTESTING
FUNCTIONALITY
Theserelationshipscanbeseenintheblockdiagram. Arecommendedtest
configurationwouldbetouseSYNC0orSYNC1asthetestclockinput,andtie
PLL_ENandREF_SELtogetherandconnectthemtothetestselectlogic.
WhenthePLL_ENpinisLOW,thePLLisbypassedandtheFCT388915T
isinlowfrequency"testmode". Intestmode(withFREQ_SELHIGH),the2Q
outputisinvertedfromtheselectedSYNCinput,andtheQoutputsaredivide-
by-2(negativeedgetriggered)oftheSYNCinput,andtheQ/2outputisdivide-
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-
by-2oftheSYNC,theQoutputsdivide-by-4,andtheQ/2outputdivide-by-8.
Thisfunctionalityisneededsincemostboard-leveltestersrunat1MHzor
below,andtheFCT388915Tcannotlockontothatlowofaninputfrequency.
Inthetestmodedescribedabove,anytestfrequencytestcanbeused.
8
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
6.0V
VCC
VCC
VCC
GND
100Ω
500Ω
500Ω
IN
VOUT
V
VOUT
IN
V
Pulse
Generator
Pulse
Generator
D.U.T.
D.U.T.
20pF
CL
100Ω
RT
RT
50Ω to VCC/2, CL = 20pF
Enable and Disable Test Circuit
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
t
CYCLE
SYNC INPUT
tPD
VCC/2
VCC/2
FEEDBACK
INPUT
Q/2 OUTPUT
t
t
t
SKEWf
t
SKEWf
SKEWr
t
SKEWr
VCC/2
SKEWALL
Q0-Q4
OUTPUTS
t
CYCLE "Q" OUTPUTS
VCC/2
VCC/2
Q5 OUTPUT
2Q OUTPUT
Propagation Delay, Output Skew
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE
DISABLE
SWITCHPOSITION
3V
CONTROL
INPUT
1.5V
0V
Test
Switch
tPZL
tPLZ
Disable Low
Enable Low
6V
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
0.3V
0.3V
VOL
Disable High
Enable High
GND
tPZH
tPHZ
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
0V
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns.
9
IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
XXXX
XX
XX
XX
FCT
Temp. Range
Speed
Device Type
Package
J
Plastic Leaded Chip Carrier
JG
PY
PYG
PLCC - Green
Small Shrink Outline IC
SSOP - Green
70(1)
70MHz Max. Frequency
100MHz Max. Frequency
133MHz Max. Frequency
150MHz Max. Frequency
(1)
100
(1)
133
150 (1)
388915T 3.3V Low skew PLL-based CMOS clock driver
0°C to +70°C
74
NOTE:
1. When ordering GREEN packages, replace this numeric value with the equivalent letter below.
B= 70 MHz
C= 100 MHz
D= 133 MHz
E= 150 MHz
(JG or PYG)
(JG or PYG)
(JG or PYG)
(JG or PYG)
For example, to order a 133MHz version, Green PLCC, the nomenclature would be 74FCT388915TDJG.
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6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
clockhelp@idt.com
www.idt.com
10
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