IDT74FCT3932100PA [IDT]
PLL Based Clock Driver, FCT Series, 17 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, 6.10 MM, 0.50MM PITCH, TSSOP-48;
| 型号： | IDT74FCT3932100PA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, FCT Series, 17 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, 6.10 MM, 0.50MM PITCH, TSSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74FCT3932-100
IDT74FCT32932-100
ADVANCE INFORMATION
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
Integrated Device Technology, Inc.
feedbackpathdelayshouldbemadetomatchthisoutputpath
delay.
The PLL consists of the phase/frequency detector, charge
pump, loopfilterandVCO. TheFCT3932requiresnoexternal
loop filter components.
The FCT3932 provides 17 outputs grouped in 3 banks with
individual 3-state control and an additional dedicated feed-
backoutputwithnodisable. ConnectingQ_FBtoFEEDBACK
ensures uninterrupted PLL operation when all outputs are
disabled.
Individual bank 3-state allows users to disable unused
outputs in order to limit power dissipation or minimize switch-
ing noise. It also allows users to shut down outputs in low
power modes while maintaining phase lock.
TheFCT3932providesaLOCKpinthatgoeshighwhenthe
device is phase-locked.
The user can bypass the PLL for testability purposes by
deasserting PLL_EN. In this "test" mode, the input frequency
is not limited to the specified range.
The FCT3932 provides an asynchronous reset input, RST,
whichresetsalloutputs. Thisinitializesallinternalregistersso
that outputs start up in a known state.
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew
• 16 programmable frequency configurations
• 17 3-state outputs:
±24 mA FCT3932
±8 mA FCT32932
• Output configuration:
BANK1: 4 outputs
BANK2: 8 outputs
BANK3: 5 outputs
• Dedicated feedback output (Q_FB)
• Maximum output frequency: 100MHz
• VCC = 3.3V ±0.3V
• Inputs can be driven from 3.3V or 5V components
• Available in 48 SSOP, TSSOP packages
• Suited to SDRAM applications
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the
frequency and phase of the feedback to the input reference
clock. It provides a large number of low skew outputs that are
configurable in 16 different modes using the CNTRL 1-4
inputs. A dedicated output, Q_FB, is provided to supply the
PLL feedback and it should be connected to the FEEDBACK
input. Q_FB is located adjacent to FEEDBACK to minimize
the delay in the feedback path. In order to offset any delay in
theoutputpathfromtheFCT3932outputtoareceivingdevice,
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microproces-
sors, motherboard clock distribution to DIMMs.
FUNCTIONAL BLOCK DIAGRAM
LOCK
FEEDBACK
Voltage
Controlled
Oscillator
Charge
Pump &
Loop Filter
Phase/Freq.
Detector
REF_IN
0
1
PLL_EN
Mux
OE1
OE2
Q41-4
(BANK 1)
C
O
N
T
R
O
L
Q81-8
(BANK 2)
OE3
Q51-5
(BANK 3)
CNTRL1-4
Q_FB
RST
3267 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 1996
1996 Integrated Device Technology, Inc.
9.9
DSC-3267/2
1
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Terminal Voltage with Respect to
GND
Max.
Unit
(2)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VTERM
–0.5 to +4.6
V
V
CC
Q54
2
Q5
5
Q5
GND
Q5
Q5
3
(3)
Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to –0.5 to VCC
VTERM
–0.5 to +7.0
V
V
3
CNTRL1
GND
(4)
VTERM
4
2
GND
+ 0.5
5
CNTRL2
CNTRL3
1
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
6
VCC
–60 to +60 mA
3267 tbl 01
7
V
CC
NOTES:
Q4
Q4
GND
Q4
Q4
4
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
8
CNTRL4
Q_FB
FEEDBACK
GND
3
9
10
11
2
1
12 SO48-1
SO48-2
13
REF_IN
AVCC
V
CC
CC
V
14
15
16
17
18
19
20
21
22
23
24
NC
Q88
AGND
GND
Q8
GND
Q8
7
CAPACITANCE (TA = +25°C, f = 1.0MHz)
OE1
6
Symbol Parameter(1)
Conditions
IN = 0V
Typ. Max. Unit
OE2
Q85
C
IN
Input
V
3.2
5.0
pF
OE3
VCC
Capacitance
I/O
RST
Q8
Q8
GND
Q8
Q8
4
C
I/O
VOUT = 0V
3.7
8.0
pF
GND
3
Capacitance
3267 lnk 02
PLL_EN
LOCK
NOTE:
1. This parameter is measured at characterization but not tested.
2
V
CC
1
SSOP
TSSOP
TOP VIEW
3267 drw 02
*NC = No connect
9.9
2
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name
REF_IN
FEEDBACK
Q41-4
I/O
I
Description
Reference clock input.
Feedback input to phase detector.
BANK1 clock outputs.
I
O
O
O
I
Q81-8
BANK2 clock outputs.
Q51-5
BANK3 clock outputs.
OE1-3
Output enable controls for BANKS 1, 2 and 3 (Active LOW).
Control lines to select output configuration (see table).
Dedicated PLL feedback output.
CNTRL1-4
Q_FB
I
O
I
RST
Asynchronous reset (Active LOW).
PLL_EN
I
Disables phase-lock for low frequency testing (Refer to functional block diagram).
LOCK
O
PLL "LOCK" indicator (HIGH when PLL is locked).
3267 tbl 03
OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE
MODE
CNTRL
Q_FEEDBACK
Q_BANK1
Q_BANK2
Q_BANK3
FIN Range
4 3 2 1
(4 outputs)
(8 outputs)
(5 outputs)
0
1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-3)
F (divide-by-3)
F (divide-by-3)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-4)
F (divide-by-4)
F (divide-by-4)
F
F
F
F
F
F/2
F
50-100MHz
50-100MHz
50-100MHz
50-100MHz
50-100MHz
16.7-33.3MHz
16.7-33.3MHz
16.7-33.3MHz
25-50MHz
2
F
F
3
F
F/2
F/3
3F
F
F/2
F
4
F
5
3F
3F
3F
2F
2F
2F
2F
2F
4F
4F
4F
F
6
3F
3F
2F
2F
F
7
3F
2F
F
8
9
25-50MHz
10
11
12
13
14
15
F
25-50MHz
F
F/2
F
25-50MHz
F/2
2F
2F
2F
25-50MHz
4F
2F
F
12.5-25MHz
12.5-25MHz
12.5-25MHz
3267 tbl 04
9.9
3
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
VIH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2.0
—
5.5
VCC+0.5
0.8
V
Input HIGH Level (I/O pins)
Input LOW Level
2.0
—
—
VIL
Guaranteed Logic LOW Level
–0.5
V
(Input and I/O pins)
II H
Input HIGH Current (Input pins)
Input LOW Current (Input pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VCC = Max.
VI = 5.5V
VI = GND
VO = VCC
VO = GND
—
—
—
—
±1
±1
µA
µA
II L
IOZH
IOZL
VIK
—
—
±1
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–75
75
–1.2
V
IODH
IODL
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = Max., VIN = GND or VCC
–36
50
—
mA
mA
mA
Output LOW Current
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
—
6
3267 tbl 05
TYPE 1 DRIVER - FCT3932
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.
IOH = –0.1mA
VCC–0.2
—
—
V
VIN = VIH or VIL
VCC = 3.0V
IOH = –8mA
2.2(4)
2.4
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
—
—
—
—
0.2
0.3
0.2
0.4
0.5
V
VIN = VIH or VIL
3267 tbl 06
TYPE 2 DRIVER - FCT32932
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.
IOH = –0.1mA
VCC–0.2
—
—
V
VIN = VIH or VIL
VCC = 3.0V
IOH = –8mA
2.4(4)
3.0
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
IOL = 0.05mA
IOL = 4mA
—
—
—
—
0.2
0.3
0.2
0.4
0.5
V
VIN = VIH or VIL
IOL = 8mA
3267 tbl 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. VOH = VCC –0.6V at rated current.
9.9
4
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
tRISE/FALL
Rise/Fall Times REF_IN input (0.8V to 2.0V)
Input Frequency REF_IN input Modes 0, 1, 2, 3, 4
Modes 5, 6, 7
—
3.0
ns
Frequency
50
16.7
25
100
33.3
50
MHz
Modes 8, 9, 10, 11, 12
Modes 13, 14, 15
12.5
25
25
Duty Cycle
Input Duty Cycle, REF_IN input
75
%
3267 tbl 09
OUTPUT FREQUENCY SPECIFICATIONS
Mode
Parameter
Min.
50
Max.
Unit
0, 1, 2, 3,4
Operating
frequency
F, F Outputs
100
50
MHz
F/2 Outputs
F/3 Outputs
3F Outputs
F Outputs
25
16.7
50
33.3
100
33.3
100
50
5, 6, 7
Operating
frequency
Operating
frequency
16.7
50
8, 9, 10, 11, 12
2F Outputs
F Outputs
25
F/2 Outputs
4F Outputs
2F Outputs
F Outputs
12.5
50
25
13, 14, 15
Operating
frequency
100
50
25
12.5
25
3267 tbl 10
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VIN = VCC –0.6V(3)
Min. Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
—
2.0
30
µA
ICCD
IC
Dynamic Power Supply
Current(4)
VCC = Max.
VIN = VCC
VIN = GND
MODE 10
F = 50Mhz
—
72
µA/
MHz/
bit
All Outputs Open
50% Duty Cycle
VCC = Max.
Total Power Supply Current(5,6)
—
62
mA
PLL_EN = 1, LOCK = 1, MODE 10
REF_IN frequency = 50MHz.
All outputs open
3267 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = SYNC input frequency
ILOAD = Dynamic Current due to load.
9.9
5
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(7)
Symbol
Parameter
Condition(1)
Min.(2) Max. Unit
(3)
tPD
Propagation Delay
No Load
–0.5
+0.5
ns
(REF_IN input to Q outputs)
REF_IN-Q_FB
tRISE/FALL
Rise/Fall Time (between 0.8 and 2.0V)
FCT3932
CL = 20pF for FCT3932
CL = 10pF for FCT32932
0.5
0.5
45
—
1.5
2.0
55
ns
All Outputs
FCT32932
(3)
tPW
Output Duty Cycle
%
tSKEWr(3,4)
tSKEWf(3,4)
tSKEWall(3,4)
Output to Output Skew (All outputs at
same frequency rising edge)
Output to Output Skew (All outputs at
same frequency falling edge)
Output to Output Skew (All outputs,
rising edge any frequency)
Time required to acquire
500
ps
—
—
1
500
1.0
10
ps
ns
(5)
tLOCK
ms
Phase-Lock from time
REF_IN input signal is received
Output Enable Time OEx
tPZH
tPZL
tPHZ
tPLZ
3.0
3.0
8.0
8.0
ns
(LOW-to-HIGH) to Q
Output Disable Time OEx
(HIGH-to-LOW) to Q
ns
3267 tbl 13
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. With VCC fully powered-on and Q_FB properly connected to the FEEDBACK pin.
6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output.
7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2.
t
PD = ±0.5ns
Offset
REF_IN input
Feedback Output
3267 drw 03
9.9
6
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
Board VCC Plane
10µF
(1)
(7)
(43)
(37)
0.1µF
0.1µF
(13)
FCT3932
(36)
(30)
0.1µF
0.1µF
(24)
0.1µF
3267 drw 04
Figure 2. Recommended Decoupling for the FCT3932/FCT32932
NOTES:
1. Figure 2 shows a decoupling scheme which will be effective in most FCT3932 applications. The following guidelines should be followed for stable, jitter-
free operation:
a. All decoupling capacitors should be connected as close to the package as possible. (Preferably at the device pins).
b. The 10µF and 0.1µF bypass capacitors provide protection from power supply and ground plane transients.
STANDARD LOAD (USED WHEN SPECIFIED)
500Ω
50pF
9.9
7
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT
ENABLE/DISABLE TEST CIRCUIT
6.0V
VCC
VCC
Open
GND
VOUT
V
IN
500Ω
Pulse
Generator
VOUT
D.U.T.
V
IN
Pulse
Generator
D.U.T.
CL
RT
C
L
500Ω
RT
3267 drw 06
PROPAGATION DELAY, OUTPUT SKEW3267 drw 05
3V
1.5V
0V
REF_IN
INPUT
tPD
VOH
1.5V
VOL
Q_FB
tSKEWf
tSKEWr
tSKEWr
VOH
1.5V
VOL
Qxx
Qyy
tSKEWf
VOH
1.5V
VOL
tSKEWall
tSKEWf
VOH
1.5V
VOL
Qzz
3267 drw 07
tSKEWr
ENABLE AND DISABLE TIMES
SWITCH POSITION
ENABLE
DISABLE
Test
Open Drain
Switch
3V
Disable Low
Enable Low
6V
CONTROL
INPUT
1.5V
0V
tPZL
tPLZ
Disable High
Enable High
All Other tests
DEFINITIONS:
GND
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Open
0.3V
0.3V
VOL
VOH
3267 lnk 14
tPZH
tPHZ
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
Generator.
1.5V
0V
0V
3267 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
9.9
8
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX
X
X
IDT
XX
FCT
Speed
Package
Temp. Range
Device Type
PV
PA
Small Shrink Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
100
50 - 100Mhz
3.3V Low skew PLL-based
CMOS clock driver
3932
32932
0°C to +70°C
74
3267 drw 09
9.9
9
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