IDT74FCT807CTPYGI8 [IDT]
Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20;
| 型号： | IDT74FCT807CTPYGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
1-TO-10 CLOCK DRIVER
IDT74FCT807BT/CT
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 250ps (max.)
• Very low duty cycle distortion < 350ps (max.)
• High speed: propagation delay < 2.5ns (max.)
• 100MHz operation
The FCT807T clock driver is built using advanced dual metal CMOS
technology. This low skew clock driver features 1:10 fanout, providing
minimal loading on the preceding drivers. The FCT807T offers low
capacitance inputs with hysteresis for improved noise margins. TTL level
outputs and multiple power and grounds reduce noise. The device also
features -32/48mA drive capability for driving low impedance traces.
• TTL compatible inputs and outputs
• TTL level output voltage swings
• 1:10 fanout
• Output rise and fall time < 1.5ns (max)
• Low input capacitance: 4.5pF typical
• High drive: -32mA IOH, +48mA IOL
• Available in QSOP, SSOP, and SOIC packages
FUNCTIONALBLOCKDIAGRAM
PINCONFIGURATION
O1
1
20
19
18
17
VCC
IN
O2
O3
O4
2
3
GND
O1
O10
O9
4
VCC
O2
GND
O8
5
16
15
14
13
12
11
6
GND
O3
VCC
O7
7
O5
8
VCC
O4
GND
O6
IN
9
O6
10
GND
O5
O7
O8
O9
QSOP/ SOIC/ SSOP
TOP VIEW
O10
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2010
1
c
2006 Integrated Device Technology, Inc.
DSC-4242/4
IDT74FCT807BT/CT
FASTCMOS1-TO-10CLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
CAPACITANCE (TA = +25OC, f = 1.0MHz)
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
CIN
Parameter(1)
Conditions
VIN = 0V
Typ.
4.5
Max. Unit
Symbol
VTERM
TSTG
Description
Max
Unit
V
InputCapacitance
OutputCapacitance
6
8
pF
pF
TerminalVoltagewithRespecttoGND
StorageTemperature
–0.5 to +7
–65to+150
COUT
VOUT = 0V
5.5
°C
NOTE:
IOUT
DCOutputCurrent
–60to+120
mA
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PINDESCRIPTION
Pin Names
Description
IN
Inputs
O x
Outputs
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 5V ± 5%
Symbol
VIH
Parameter
TestConditions(1)
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
VCC = Max.
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input HIGH Level (Input pins)
InputLOWLevel
VIL
—
—
—
—
—
—
—
–60
2.4
2
—
0.8
1
V
IIH
Input HIGH Current (Input pins)
InputLOWCurrent(Inputpins)
HighImpedanceOutputCurrent
(3-StateOutputpins)
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
1
IOZH
IOZL
II
VCC = Max.
—
1
—
1
Input HIGH Current
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
VCC = Min.
—
1
µA
V
VIK
ClampDiodeVoltage
ShortCircuitCurrent(4)
–0.7
–120
3.3
3
–1.2
–225
—
IOS
mA
V
VOH
Output HIGH Voltage
IOH = –15mA
IOH = –32mA
IOL = 48mA
VIN = VIH or VIL
—
VOL
OutputLOWVoltage
VCC = Min.
—
0.3
0.55
V
VIN = VIH or VIL
IOFF
VH
Input/OutputPowerOffLeakage
InputHysteresisforallinputs
Quiescent Power Supply Current
VCC = 0V, VIN or VO ≤4.5V
—
—
—
—
—
150
5
1
—
µA
mV
µA
ICCL
ICCH
ICCZ
VCC = Max., VIN = GND or VCC
500
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
2
IDT74FCT807BT/CT
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FASTCMOS1-TO-10CLOCKDRIVER
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V
—
0.5
2
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(3)
VCC = Max.
InputToggling
50% Duty Cycle
OutputsOpen
VCC = Max.
InputToggling
50% Duty Cycle
OutputsOpen
fI = 50MHz
VIN = VCC
—
0.4
0.6
mA/MHz
VIN = GND
IC
TotalPowerSupplyCurrent(5)
VIN = VCC
—
—
20
30.5(4)
31.3(4)
mA
VIN = GND
VIN = 3.4V
VIN = GND
20.3
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
3
IDT74FCT807BT/CT
FASTCMOS1-TO-10CLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-COMMERCIAL(3,4)
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.3
2.7
1.3
2.5
ns
50Ωto VCC/2,
CL = 10pF
(Seefigure1)
or 50Ωac
termination,
OutputRiseTime
—
—
—
1.5
1.5
0.5
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.25
CL = 10pF
(See figure 2)
f ≤100MHz
Outputsconnectedin
tSK(P)
tSK(T)
—
—
0.5
0.9
—
—
0.35
0.65
ns
ns
groupsoftwo
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
3.8
1.5
3.5
ns
CL = 30pF
f ≤67MHz
(Seefigure3)
OutputRiseTime
—
—
—
1.5
1.5
0.5
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.25
tSK(P)
tSK(T)
—
—
0.5
0.9
—
—
0.35
0.75
ns
ns
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
3.8
1.5
3.5
ns
CL = 30pF
f ≤40MHz
(Seefigure4)
OutputRiseTime
—
—
—
1.5
1.5
0.5
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.35
tSK(P)
tSK(T)
—
—
0.6
1
—
—
0.45
0.75
ns
ns
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
4
IDT74FCT807BT/CT
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FASTCMOS1-TO-10CLOCKDRIVER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-INDUSTRIAL(3,4)
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.3
2.9
1.3
2.7
ns
50Ωto VCC/2,
CL = 10pF
(Seefigure1)
or 50Ωac
termination,
OutputRiseTime
—
—
—
1.5
1.5
0.6
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.35
CL = 10pF
(See figure 2)
f ≤100MHz
Outputsconnectedin
tSK(P)
tSK(T)
—
—
0.6
0.9
—
—
0.45
0.65
ns
ns
groupsoftwo
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
4
1.5
3.7
ns
CL = 30pF
f ≤67MHz
(Seefigure3)
OutputRiseTime
—
—
—
1.5
1.5
0.6
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.35
tSK(P)
tSK(T)
—
—
0.6
0.9
—
—
0.45
0.75
ns
ns
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
FCT807BT
FCT807CT
(2)
(2)
Symbol
tPLH
tPHL
tR
Parameter
Conditions(1)
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
4
1.5
3.7
ns
CL = 30pF
f ≤40MHz
(Seefigure4)
OutputRiseTime
—
—
—
1.5
1.5
0.6
—
—
—
1.5
1.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
0.45
tSK(P)
tSK(T)
—
—
0.7
1
—
—
0.55
0.75
ns
ns
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
5
IDT74FCT807BT/CT
FASTCMOS1-TO-10CLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITS
VCC
VCC
VCC
100
VIN
VIN
VOUT
VOUT
Pulse
Generator
Pulse
Generator
D.U.T.
D.U.T.
50
10pF
10pF
100
RT
RT
220pF
Fig. 1: 50Ωto VCC/2, CL = 10pF
Fig. 2: 50Ω AC Termination, CL = 10pF
The capacitor value for AC termination is determined by the operating frequency. For
very low frequencies a higher capacitor value should be selected.
VCC
VCC
V OUT
V OUT
VIN
VIN
Pulse
Generator
Pulse
Generator
D.U.T.
D.U.T.
30pF
50pF
RT
R T
L
C
C L
Fig. 4: CL = 50pF Circuit
Fig. 3: CL = 30pF Circuit
VCC
7.0V
SWITCHPOSITION
500
500
Test
Switch
V OUT
V IN
Disable LOW
Enable LOW
6V
Pulse
Generator
D.U.T.
Disable HIGH
Enable HIGH
GND
50pF
RT
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Fig. 5: Enable and Disable Time Circuit
6
IDT74FCT807BT/CT
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FASTCMOS1-TO-10CLOCKDRIVER
TESTWAVEFORMS
3V
3V
1.5V
0V
1.5V
0V
INPUT
tPLH1
tPHL1
INPUT
VOH
tPLH
tPHL
1.5V
VOL
VOH
1.5V
VOL
OUTPUT 1
OUTPUT 2
2.0V
0.8V
tSK(o)
tSK(o)
VOH
1.5V
VOL
OUTPUT
tPLH2
tF
tPHL2
tR
tSK(o) =|tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Package Delay
Output Skew - tSK(O)
3V
3V
1.5V
0V
1.5V
0V
INPUT
tPHL1
tPLH1
INPUT
VOH
1.5V
VOL
tPHL
tPLH
VOH
1.5V
VOL
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tSK(t)
tSK(t)
VOH
1.5V
VOL
OUTPUT
tSK(p) =|tPHL -
tPLH|
tPLH2
tPHL2
Pulse Skew - tSK(P)
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Part-to-Part Skew - tSK(T)
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
ENABLE
DISABLE
3V
CONTROL
INPUT
1.5V
0V
PLZ
tPZL
t
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
tPHZ
tPZH
OUTPUT
NORMALLY
HIGH
VOH
0V
SWITCH
OPEN
1.5V
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
7
IDT74FCT807BT/CT
FASTCMOS1-TO-10CLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
74FCT
XXXX
X
X
Package
Device Type
Temp. Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
SOG
PYG
SOIC - Green
SSOP - Green
QSOP - Green
QG
1-to-10 Clock Driver
807BT
807CT
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
clockhelp@idt.com
www.idt.com
8
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Low Skew Clock Driver, FCT Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20
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