IDT74FCT821ADSOB [IDT]
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER; 高性能CMOS总线接口寄存器
| 型号： | IDT74FCT821ADSOB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 文件： | 总7页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT821A/B
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
FEATURES:
DESCRIPTION:
• Equivalent to AMD’s Am29821-25 bipolar registers in pinout/
function, speed and output drive over full temperature and
voltage supply extremes
The FCT821 series is built using an advanced dual metal CMOS
technology. The FCT821 series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The 74FCT821 is a buffered, 10-bit wide version of the popular
FCT374 function.
• IDT54/74FCT821A equivalent to FAST™ speed
• IDT54/74FCT821B 25% faster than FAST
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s bipolar
Am29800series(5µAmax.)
The FCT821 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
• Military product compliant to MIL-STD-883, Class B
• Available in the following packages:
– Commercial: SOIC
– Military: CERDIP, LCC
FUNCTIONALBLOCKDIAGRAM
OE
CP
C1
23
Q
Y
D0
1D
TO NINE OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5427/2
IDT54/74FCT821/A/B
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
MILITARYANDCOMMERCIALTEMPERATURERANGES
PINCONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
OE
D0
VCC
Y0
INDEX
2
3
4
D1
D2
Y1
Y2
4
3
2
2
8
2
7
2
6
5
D2
25
24
23
22
Y2
1
6
D3
D4
NC
D5
D6
D7
Y3
Y4
D3
D4
D5
Y3
Y4
Y5
5
6
7
8
9
7
8
NC
Y5
9
21
20
D6
D7
Y6
Y7
10
Y6
11
1
9
Y7
12
1
3
1
4
1
5
1
6
1
7
1
8
D8
D9
Y8
Y9
CP
10
11
12
GND
LCC
TOP VIEW
CERDIP/ SOIC
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
LOGICSYMBOL
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage
–0.5 to +7
–0.5 to +7
V
10
D
D
with Respect to GND
Terminal Voltage
10
(3)
Q
Y
VTERM
–0.5 to VCC
–0.5 to VCC
V
with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
CP
TA
0 to +70
–55 to +125
–55 to +125
0.5
–55 to +125
–65 to +135
–65 to +150
0.5
°C
°C
°C
W
CP
OE
TBIAS
TSTG
PT
IOUT
120
120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
PINDESCRIPTION
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
Pin Name
I/O
Description
Dx
I
I
D Flip-Flop Data Inputs
CP
Clock Pulse for the Register. Enters data into the
register on the LOW-to-HIGH transition
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Y x
O
I
Register 3-State Outputs
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
OE
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the
OE input is LOW, the TRUE register data is present
at the Yx outputs.
CIN
VIN = 0V
6
8
10
12
pF
pF
COUT
VOUT = 0V
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT54/74FCT821/A/B
MILITARYANDCOMMERCIALTEMPERATURERANGES
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
FUNCTIONTABLE(1)
Inputs
Outputs
OE
H
H
H
L
Dx
L
CP
↑
↑
X
Yx
Z
Function
High Z
H
X
X
X
X
L
Z
Z
Clear
Hold
Load
X
L
H
L
X
Z
X
N C
Z
H
H
L
↑
↑
↑
↑
H
L
Z
L
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH transition
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
0.8
5
5
–5(4)
–5
V
IIH
Input HIGH Current
VI = VCC
—
—
—
—
—
—
—
—
—
—
—
µA
(4)
VI = 2.7V
VI = 0.5V
VI = GND
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
IIL
Input LOW Current
VCC = Max.
VCC = Max.
—
—
—
—
µA
µA
IOZH
Off State (High Impedance)
Output Current
10
10(4)
–10(4)
–10
–1.2
IOZL
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
V
–75
–120
—
—
—
—
—
VLC
VLC(4)
0.5
0.5
mA
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VCC = Min
VHC
VHC
2.4
2.4
—
—
—
—
VCC
VCC
4.3
IOH = –300µA
IOH = –15mA MIL
IOH = –24mA COM
V
V
VIN = VIH or VIL
4.3
VOL
OutputLOWVoltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min
GND
GND
0.3
IOL = 300µA
IOL = 32mA MIL
IOL = 48mA COM
VIN = VIH or VIL
0.3
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed, but not tested.
3
IDT54/74FCT821/A/B
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
MILITARYANDCOMMERCIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply Current
VCC = Max.
—
0.2
1.5
mA
VIN ≥ VHC; VIN ≤ VLC
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
—
0.5
2
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = GND
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN ≥ VHC
VIN ≤ VLC
—
—
1.7
2.2
4
6
mA
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
—
—
4
7.8(5)
VIN = 3.4V
VIN = GND
6.2
16.8(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT821/A/B
MILITARYANDCOMMERCIALTEMPERATURERANGES
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
IDT54/74FCT821A
IDT54/74FCT821B
Com’l. Mil.
Max. Min.(2) Max. Min.(2) Max. Unit
Com’l.
Mil.
Parameter Description
Conditions(1)
CL = 50pF
Min.(2)
Max.
Min.(2)
tPLH
tPHL
PropagationDelay
—
10
—
11.5
—
7.5
—
8.5
ns
CP to Yx (OE = LOW)
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 50pF
—
20
—
20
—
15
—
16
tSU
tH
Set-up Time HIGH or LOW, Dx to CP
Hold Time HIGH or LOW, Dx to CP
4
2
—
—
4
2
—
—
3
—
—
3
—
—
RL = 500Ω
1.5
1.5
ns
ns
tW
tPZH
tPZL
CP Pulse Width, HIGH or LOW
OutputEnableTime
OE to Yx
7
—
—
12
7
—
—
13
6
—
—
8
6
—
—
9
CL = 50pF
RL = 500Ω
CL = 300pF(3)
—
23
—
25
—
15
—
16
RL = 500Ω
tPHZ
tPLZ
OutputDisableTime
OE to Yx
CL = 5pF(3)
RL = 500Ω
—
—
7
8
—
—
8
9
—
—
6.5
7.5
—
—
7
8
ns
CL = 50pF
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
5
IDT54/74FCT821/A/B
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
MILITARYANDCOMMERCIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
VCC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
VOUT
VIN
Open Drain
Disable Low
Enable Low
Pulse
Generator
D.U.T
.
50pF
All Other Tests
500Ω
T
R
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
Octal link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT54/74FCT821/A/B
MILITARYANDCOMMERCIALTEMPERATURERANGES
HIGHPERFORMANCECMOSBUSINTERFACEREGISTER
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XX
X
Temp. Range
Package
Process
Device Type
Blank
B
Commercial
MIL-STD-883, Class B
Commercial Options
Small Outline IC
SO
Military Options
CERDIP
Leadless Chip Carrier
D
L
High Performance CMOS Bus Inter-
face Register, 10-Bit
821A
821B
54
74
– 55°C to +125°C
0°C to +70°C
DATASHEETDOCUMENTHISTORY
6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
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(408) 654-6459
www.idt.com
7
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