IDT74FCT823CD [IDT]
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS; 高性能CMOS总线接口寄存器
| 型号： | IDT74FCT823CD |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 文件： | 总8页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST speed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-perform-
ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
familyaredesignedforhigh-capacitanceloaddrivecapability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
IDT54/74FCT824
D0
DN
D0
DN
EN
EN
CLR
CLR
CL
CL
CL
CL
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
CP
CP
CP
CP
OE
CP
OE
Y0
YN
Y0
YN
2608 cnv* 02
2608 cnv* 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.19
DSC-4618/2
1
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT54/74FCT821 10-BIT REGISTER
INDEX
1
2
3
4
5
6
7
8
9
10
24
23
22
V
Y
Y
Y
Y
CC
0
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
1
10
4 3 2
282726
P24-1 21
D24-1 20
2
1
10
D
D
D
2
3
4
D
D
5
6
7
8
9
10
11
25
Y
Y
Y
2
3
4
3
Q
Y
24
23
22
21
20
19
CP
E24-1
&
SO24-2
19
18
17
16
Y
Y
Y
Y
Y
4
5
6
7
8
CP
OE
NC
NC
L28-1
D
D
D
5
6
7
Y5
Y6
Y7
15
14
13
1213 1415161718
Y
CP
9
11
12
GND
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv* 03
IDT54/74FCT823/824 9-BIT REGISTERS
INDEX
1
2
3
4
5
6
7
8
9
10
24
23
22
VCC
Y0
Y1
Y2
Y3
OE
D0
D1
D2
D3
D4
D5
D6
D7
4 3 2
282726
9
P24-1 21
D24-1 20
1
9
D2
D3
D4
D
D
5
6
7
8
25
Y2
Y3
Y4
NC
Y5
Y6
Y7
Q
Y
24
23
22
21
20
19
CP EN CLR
SO24-2
&
E24-1
19
18
17
16
Y4
Y5
Y6
Y7
Y8
CP
EN
NC
D5
D6
D7
L28-1
9
10
11
CLR
OE
D8
CLR
GND
15
14
13
1213 1415161718
EN
CP
11
12
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv* 04
IDT54/74FCT825 8-BIT REGISTER
INDEX
1
2
3
4
5
6
7
8
9
10
24
23
22
VCC
OE
OE
1
2
8
OE3
8
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Q
Y
4 3 2
282726
P24-1 21
D24-1 20
1
CP EN CLR
D
D
D
1
2
3
5
6
7
8
9
10
11
25
Y
Y
Y
1
2
3
CP
EN
24
23
22
21
20
19
E24-1
&
SO24-2
19
18
17
16
Y4
Y5
Y6
Y7
NC
NC
L28-1
CLR
D4
D5
D6
Y4
Y5
Y6
OE
OE
OE
1
2
3
15
14
13
1213 1415161718
EN
CP
CLR
GND
11
12
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv* 05
7.19
2
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT SELECTOR GUIDE
FUNCTION TABLE(1)
IDT54/74FCT821/823/825
Device
Internal/
Outputs
Inputs
10-Bit
9-Bit
8-Bit
Non-inverting
Inverting
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
DI
CP
QI
YI
OE
CLR
EN
Function
54/74FCT824A/B/C
2608 tbl 01
H
H
H
H
L
L
L
H
↑
↑
L
H
Z
Z
High Z
H
L
L
L
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
L
L
Z
L
Clear
Hold
Load
PIN DESCRIPTION
H
L
H
H
H
H
H
H
NC
NC
L
H
L
Z
NC
Z
Z
L
Name
I/O
Description
DI
I
The D flip-flop data inputs.
H
H
L
CLR
I
For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the QI outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
↑
↑
L
H
H
↑
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-HIGH
CP
I
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54/74FCT824
YI , YI
EN
O
I
The register three-state outputs.
Clock Enable. When the clock enable
is LOW, data on the D I input is
transferred to the QI output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the QI
Internal/
Outputs
Inputs
DI
CP
QI
YI
OE
CLR
EN
Function
H
H
H
H
L
L
L
H
↑
↑
H
L
Z
Z
High Z
outputs do not
change state,
regardless of the data or clock input
transitions.
H
L
L
L
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
L
L
Z
L
Clear
Hold
Load
OE
I
Output Control. When the OE input is
HIGH, the Y I outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is
H
L
H
H
H
H
H
H
NC
NC
H
L
H
Z
NC
Z
Z
H
L
H
H
L
↑
present at the Y I outputs.
↑
2608 tbl 10
L
L
↑
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-
HIGH Transition, Z = High Impedance
7.19
3
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
Input
Capacitance
Output
VIN = 0V
6
10
pF
COUT
VOUT = 0V
8
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to VCC
0 to +70
–0.5 to VCC
–55 to +125
V
Capacitance
NOTE:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
T
T
T
A
Operating
°
°
°
C
C
C
Temperature
Temperature
Under Bias
Storage
BIAS
STG
–55 to +125 –65 to +135
–55 to +125 –65 to +150
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
120
120
mA
NOTES:
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
5
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
VCC = Max.
VI = VCC
—
—
µA
VI = 2.7V
VI = 0.5V
VI = GND
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
—
—
5(4)
–5(4)
–5
II L
Input LOW Current
—
—
—
—
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
—
—
10
µA
—
—
10(4)
–10(4)
–10
–1.2
—
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
V
mA
V
–75
VHC
VHC
2.4
2.4
—
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
VCC = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –15mA MIL.
IOH = –24mA COM'L.
—
—
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
(4)
V
2608 tbl 06
4
VCC = Min.
IOL = 300µA
—
GND VLC
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM'L.
—
0.3
0.3
0.5
0.5
—
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.19
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current
VCC = Max.
VIN ≥ VHC; V IN ≤ VLC
ICC
—
0.2
1.5
mA
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
∆ICC
—
—
0.5
2.0
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
Outputs Open
OE = EN = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at f i = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = EN = GND
Eight Bits Toggling
at f i = 2.5MHz
50% Duty Cycle
IC
Total Power Supply Current(6)
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
—
—
1.7
2.2
4.0
6.2
4.0
6.0
mA
VIN = 3.4V
VIN = GND
VIN ≥ VHC
VIN ≤ VLC
(FCT)
7.8(5)
VIN = 3.4V
VIN = GND
16.8(5)
NOTES:
2608 tbl 07
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.19
5
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT821A/
IDT54/74FCT821B/
823B/824B/825B
Com'l. Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
IDT54/74FCT821C/
823A/824A/825A
823C/824C/825C
Com'l.
Mil.
Com'l.
Mil.
Test
Parameter
tPLH
Description
Propagation Delay
CP to Y I (OE = LOW)
Conditions(1)
CL = 50pF
Unit
—
—
10.0
20.0
—
—
11.5
20.0
—
—
7.5
—
—
8.5
—
—
6.0
—
—
7.0 ns
13.5
tPHL
RL = 500Ω
CL = 300pF(3)
15.0
16.0
12.5
RL = 500Ω
CL = 50pF
RL = 500Ω
tSU
tH
Set-up Time HIGH or LOW
D i to CP
4.0
2.0
4.0
2.0
—
—
—
4.0
2.0
4.0
2.0
—
—
—
3.0
1.5
3.0
0
—
—
3.0
1.5
3.0
0
—
—
3.0
1.5
3.0
0
—
—
3.0
1.5
3.0
0
—
—
—
—
ns
ns
ns
ns
Hold Time HIGH or LOW
D I to CP
tSU
tH
Set-up Time HIGH or LOW
EN to CP
—
—
—
—
—
Hold Time HIGH or LOW
EN to CP
—
—
—
—
—
tPHL
Propagation Delay, CLR to
YI
14.0
15.0
—
9.0
—
9.5
—
8.0
—
8.5 ns
tREM
tW
Recovery Time CLR to CP
6.0
7.0
—
—
7.0
7.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
ns
ns
CP Pulse Width
HIGH or LOW
CLR Pulse Width
LOW
tW
6.0
—
—
7.0
—
—
6.0
—
—
8.0
6.0
—
—
9.0
6.0
—
—
7.0
6.0
—
—
ns
tPZH
tPZL
Output Enable Time OE
to YI
CL = 50pF
RL = 500Ω
CL = 300pF(3)
12.0
23.0
13.0
25.0
8.0 ns
13.5
—
—
—
15.0
—
16.0
—
12.5
—
RL = 500Ω
CL = 5pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
tPHZ
tPLZ
Output Disable Time OE
to YI
—
—
7.0
8.0
—
—
8.0
9.0
—
—
6.5
7.5
—
—
7.0
8.0
—
—
6.2
6.5
—
—
6.2 ns
6.5
NOTES:
1. See test circuit and waveforms.
2608 tbl* 08
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.19
6
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
C L
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2608 tbl 09
RT
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
tH
t SU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2608 drw 01
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.19
7
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2523IDTcnv*XX11
FCT
XXXX
Device Type
X
X
Temp. Range
Package
Process
Blank
Commercial
B
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
CERPACK
L
SO
Leadless Chip Carrier
Small Outline IC
821A
821B
821C
823A
823B
823C
824A
824B
824C
825A
825B
825C
10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
Super Fast 10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
Super Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register
54
74
–55
°C to +125°C
C to +70°C
0°
2608 cnv* 11
7.19
8
相关型号：
©2020 ICPDF网 联系我们和版权申明