IDT74FCT841ATSO [IDT]
FAST CMOS BUS INTERFACE LATCHES; FAST CMOS总线接口锁存器
| 型号： | IDT74FCT841ATSO |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS BUS INTERFACE LATCHES |
| 文件： | 总7页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS
BUS INTERFACE
LATCHES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
The FCT8xxT bus interface latches are designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high IOL/IOH.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capaci-
tance bus loading in high-impedance state.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT841T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D8
D9
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Y0
Y1
Y2
Y3
Y4
Y5
Y8
Y9
2571 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 1996
1996 Integrated Device Technology, Inc.
6.22
2571/6
1
IDT54/74FCT841AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
INDEX
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
VCC
Y0
Y1
Y2
Y3
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
4 3 2
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
282726
1
D
D3
D4
2
5
6
7
8
9
10
11
25
Y
Y
Y
2
3
4
24
23
22
21
20
19
Y4
Y5
Y6
Y7
Y8
NC
NC
L28-1
D5
D6
D7
Y5
Y6
Y7
E24-1
15
14
13
1213 1415161718
D9
GND
Y9
LE
11
12
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
2571 drw 02
2571 drw 03
PIN DESCRIPTION
FUNCTION TABLE(1)
Name
DI
I/O
Description
The latch data inputs.
I
Inputs
Internal Output
LE
H
H
L
DI
L
QI
L
YI
Z
Function
OE
H
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
High Z
High Z
H
H
X
L
H
Z
H
NC
L
Z
Latched (High Z)
Transparent
YI
O
The 3-state latch outputs.
L
H
H
L
L
OE
I
The output enable control. When OE is
LOW, the outputs are enabled. When OE
L
L
H
X
H
H
Transparent
is HIGH, the outputs V are in high-
I
NC
NC
Latched
impedance (off) state.
NOTE:
2571 tbl 02
2571 tbl 01
1. H=HIGH, L=LOW, X=Don’tCare, NC=NoChange, Z=HighImpedance
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2571 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
NOTES:
2571 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.22
2
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
VIL
II H
II L
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
—
IOZH
IOZL
II
—
µA
—
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
mV
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
mA
2571 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
V
OH
Output HIGH Voltage
V
V
CC = Min.
IN = VIH or VIL
I
I
I
I
I
I
OH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
OH = –8mA COM'L.
OH = –12mA MIL.
OH = –15mA COM'L.
OL = 32mA MIL.
—
V
V
VOL
Output LOW Voltage
V
V
V
CC = Min.
IN = VIH or VIL
0.5
OL = 48mA COM'L.
I
I
OS
Short Circuit Current
Input/Output Power Off Leakage(5)
CC = Max., V
O
= GND(3)
–60
—
–120 –225
mA
OFF
V
CC = 0V, VIN or V
O
≤ 4.5V
—
±1
µA
2571 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.22
3
IDT54/74FCT841AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS BUS INTERFACE LATCHES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max.
VIN = VCC
—
0.15
0.25
mA/
Outputs Open
OE = GND
LE = VCC
VIN = GND
MHz
One Input Toggling
50% Duty Cycle
VCC = Max.
IC
Total Power Supply Current(6)
VIN = VCC
—
—
1.5
1.8
3.5
4.5
mA
Outputs Open
fi = 10MHz
VIN = GND
50% Duty Cycle
OE = GND
VIN = 3.4
VIN = GND
LE = VCC
One Bit Toggling
VCC = Max.
VIN = VCC
—
—
3.0
5.0
6.0(5)
Outputs Open
fi = 2.5MHz
VIN = GND
50% Duty Cycle
OE = GND
VIN = 3.4
VIN = GND
14.0(5)
LE = VCC
Eight Bits Toggling
2571 tbl 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.22
4
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FCT841BT
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT
Com'l.
Mil.
Com'l.
Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Conditions(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
Unit
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
9.0
13.0
12.0
16.0
11.5
23.0
7.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
10.0
15.0
13.0
20.0
13.0
25.0
9.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
6.5
13.0
8.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
7.5
15.0
10.5
18.0
8.5
ns
DI to YI (LE = HIGH)
tPLH
tPHL
Propagation Delay
LE to YI
ns
ns
ns
15.5
8.0
tPZH
tPZL
Output Enable Time OE to YI
Output Disable Time OE to Y I
14.0
6.0
15.0
6.5
tPHZ
tPLZ
8.0
10.0
7.0
7.5
tSU
tH
Data to LE Set-up Time
Data to LE Hold Time
2.5
2.5
4.0
—
—
—
2.5
3.0
5.0
—
—
—
2.5
2.5
4.0
—
—
—
2.5
2.5
4.0
—
—
—
ns
ns
ns
RL = 500Ω
(3)
tW
LE Pulse Width HIGH
NOTES:
2571 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841CT
FCT841DT
Com'l.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
Com'l.
Mil.
Mil.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Conditions(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
Unit
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
5.5
13.0
6.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
6.3
15.0
6.8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.2
8.0
4.0
8.0
4.8
9.0
4.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
DI to YI (LE = HIGH)
tPLH
tPHL
Propagation Delay
LE to YI
ns
ns
ns
15.0
6.5
16.0
7.3
tPZH
tPZL
Output Enable Time OE to YI
Output Disable Time OE to Y I
12.0
5.7
13.0
6.0
tPHZ
tPLZ
6.0
6.3
tSU
tH
Data to LE Set-up Time
Data to LE Hold Time
2.5
2.5
4.0
—
—
—
2.5
2.5
4.0
—
—
—
1.5
1.0
3.0
—
—
—
—
—
—
—
—
—
ns
ns
RL = 500Ω
(3)
tW
LE Pulse Width HIGH
ns
NOTES:
2571 tbl 09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
6.22
5
IDT54/74FCT841AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS BUS INTERFACE LATCHES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500Ω
Enable Low
VOUT
VIN
Pulse
Generator
Open
All Other Tests
D.U.T.
2571 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
500Ω
T
R
C
L
Generator.
2571 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
t
H
t
SU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
t
W
ASYNCHRONOUS CONTROL
t
REM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
1.5V
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
2571 drw 06
1.5V
0V
CLEAR
t
SU
t
H
CLOCK ENABLE
ETC.
2571 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
V
OL
t
PLH
0.3V
0.3V
V
OL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
V
OH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2571 drw 07
0V
2571 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.22
6
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
Temp. Range
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
CERPACK
L
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
SO
PY
Q
841AT
841BT
841CT
841DT
10-Bit Non-Inverting Latch
54
74
–55°C to +125°C
0°C to +70°C
2571 drw 09
6.22
7
相关型号：
©2020 ICPDF网 联系我们和版权申明