IDT74FCT88915TTDPYG8 [IDT]
PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, GREEN, SSOP-28;
| 型号： | IDT74FCT88915TTDPYG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, FCT Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, GREEN, SSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
IDT74FCT88915TT
55/70/100/133
DESCRIPTION:
FEATURES:
TheFCT88915TTusesphase-locklooptechnologytolockthefrequency
andphaseofoutputstotheinputreferenceclock. Itprovideslowskewclock
distributionforhighperformancePCsandworkstations. Oneoftheoutputsis
fedbacktothePLLattheFEEDBACKinputresultinginessentiallyzerodelay
acrossthedevice. ThePLLconsistsofthephase/frequencydetector,charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915
• Five non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• Output Skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 0.55ns (from tPD max. spec)
• 64/–15mA drive at TTL output voltage levels
• Available in PLCC and SSOP packages
TheFCT88915TTprovideseightoutputswith500psskew. TheQ5outputis
invertedfromtheQoutputs. The2QrunsattwicetheQfrequencyandQ/2 runs
athalftheQfrequency.
TheFREQ_SELcontrolprovidesanadditional÷2optionintheoutputpath.
PLL_ENallowsbypassingofthePLL,whichisusefulinstatictestmodes. When
PLL_ENislow,SYNCinputmaybeusedasatestclock. Inthistestmode,the
inputfrequencyisnotlimitedtothespecifiedrangeandthepolarityofoutputs
iscomplementarytothatinnormaloperation(PLL_EN=1). TheLOCKoutput
attainslogichighwhenthePLLisinsteady-statephaseandfrequencylock.
The FCT88915TT requires external loop filter components as recom-
mended in Figure 2.
FUNCTIONALBLOCKDIAGRAM
FEEDBACK
LOCK
Voltage
Controlled
Oscilator
Phase/Freq.
Detector
0
1
SYNC (0)
SYNC (1)
M
u
x
Charge Pump
LF
REF_SEL
PLL_EN
0
1
2Q
Q0
Mux
(÷1)
(÷2)
1
M
u
x
D
Q
Q
CP
R
R
Divide
-By-2
0
Q1
Q2
Q3
D
Q
Q
Q
Q
Q
FREQ_SEL
RST
CP
D
CP
R
D
CP
R
R
R
R
D
Q4
Q5
Q/2
CP
D
CP
D
Q
CP
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 2001
1
©
2001 Integrated Device Technology, Inc.
DSC-4245/4
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
PINCONFIGURATIONS
1
2
3
28
27
26
Q4
GND
Q5
4
3
2
1
28 27 26
VCC
2Q
25 Q/2
FEEDBK
REF_SEL
SYNC(0)
VCC(AN)
LF
5
VCC
4
GND
RST
25
24
23
Q/2
GND
Q3
24
6
5
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
23 Q3
7
6
VCC
8
22
21
20
19
7
VCC
22
21
20
19
18
17
8
Q2
Q2
9
9
GND
LOCK
10
11
GND
LOCK
GND(AN)
SYNC(1)
GND(AN)
10
11
12
SYNC(1)
FREQ_SEL
GND
PLL_EN
GND
12 13 14 15 16 17 18
13
14
16
15
Q1
VCC
Q0
PLCC
TOP VIEW
SSOP
TOP VIEW
PINDESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
I/O
I
Description
Referenceclockinput
Referenceclockinput
I
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selectsbetween÷1and÷2frequencyoptions(refertofunctionalblockdiagram)
Feedbackinputtophasedetector
I
I
I
Inputforexternalloopfilterconnection
Q0-Q4
O
O
O
O
O
I
Clockoutputs
Q5
2Q
Invertedclockoutput
Clock output (2 x Q frequency)
Q/2
Clock output (Q frequency ÷ 2)
LOCK
Indicates phase lock has been achieved (HIGH when locked)
Asynchronousreset(activeLOW)
RST
PLL_EN
I
Disablesphase-lockforlowfrequencytesting(refertofunctionalblockdiagram)
2
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
Symbol
Description
Max.
Unit
V
(2)
CIN
VIN = 0V
4.5
6
8
pF
pF
VTERM
TerminalVoltagewithRespecttoGND
–0.5to7
(3)
VTERM
TerminalVoltagewithRespecttoGND –0.5toVCC+0.5
V
COUT
VOUT = 0V
5.5
TA
OperatingTemperature
TemperatureUnderBias
StorageTemperature
DCOutputCurrent
0 to +70
–55to+125
–55to+125
–60to120
° C
° C
° C
mA
NOTE:
1. This parameter is measured at characterization but not tested.
TBIAS
TSTG
IOUT
NOTES:
SYNCINPUTTIMINGREQUIREMENTS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
Symbol
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2.0V)
Min.
Max.
Unit
TRISE/FALL
—
3
ns
Frequency Input Frequency, SYNC Inputs
Duty Cycle Input Duty Cycle, SYNC Inputs
10
2Q fmax MHz
2. Input and VCC terminals.
3. Outputs and I/O terminals.
25%
75%
—
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to 70°C, VCC = 5.0V ±5%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
Max.
Unit
V
—
—
—
0.8
1
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
V
IIH
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
VI = VCC
—
µA
µA
V
IIL
VI = GND
—
1
VIK
VCC = Min., IIN = –18mA
–0.7
–1.2
VIH
Input Hysteresis
—
—
2.4
—
—
100
3.5
0.2
2
—
—
0.55
4
mV
V
VOH
Output HIGH Voltage
Output LOW Voltage
VCC = Min.
VCC = Min.
IOH = –15mA
IOL = 64mA
VOL
V
ICCL
ICCH
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
(Test mode, LF connected to GND)
mA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
3
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
QuiescentPowerSupplyCurrent
TTL Inputs HIGH
VCC = Max.
—
0.5
1.5
mA
(3)
VIN = VCC –2.1V
VCC = Max.
ICCD
Dynamic Power Supply
Current(4)
VIN = VCC
—
0.5
0.7
mA/
MHz
pF
AllOutputsOpen
50% Duty Cycle
VCC = Max.
VIN = GND
CPD
IC
PowerDissipationCapacitance
TotalPowerSupplyCurrent(5,6)
—
—
25
65
40
80
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50pF.
Allotheroutputsopen.
VCC = Max.
—
—
—
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50Ω
Thevenin termination. Allotheroutputsopen.
50ΩThevenin termination@33MHz
50Ω Paralell termination to GND @ 33MHz
PD1
PD2
PowerDissipation
PowerDissipation
—
—
120
300
—
—
mW
mW
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
ILOAD = Dynamic Current due to load.
OUTPUTFREQUENCYSPECIFICATIONS
Max.(2)
Symbol
f2Q
Parameter
Operatingfrequency2QOutput
OperatingfrequencyQ0-Q4,Q5Outputs
OperatingfrequencyQ/2Output
Min.
40
55
55
70
70
100
100
50
133
133
Unit
MHz
MHz
MHz
fQ
20
27.5
13.75
35
66.7
33.3
fQ/2
10
17.5
25
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
4
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
Parameter
Condition(1)
Min.
Max.
Unit
(2)
tRISE/FALL
Rise/FallTime
CL = 50pF
1
2.5
ns
AllOutputs
(between0.2VCCand0.8VCC)
Rise/FallTime
RL = 500Ω
tRISE/FALL
CL = 20pF &
0.5(2)
1.6
ns
ns
ns
ns
ns
(7)
2QOutput(3)
tPULSEWIDTH
Q, Q, Q/2 Outputs(3)
tPULSEWIDTH
2QOutput(3)
tPULSEWIDTH
2QOutput(3)
tPD
(between0.8Vand2.0V)
termination
OutputPulseWidth
CL = 50pF
CL = 50pF
0.5tCYCLE–0.5(5)
0.5tCYCLE – 1(5)
0.5tCYCLE –0.5(5)
–0.5
0.5tCYCLE +0.5(5)
0.5tCYCLE + 1(5)
0.5tCYCLE +0.5(5)
+0.5
Q0-Q4, Q5, Q/2 @ VCC/2
OutputPulseWidth
2Q Output @ VCC/2
OutputPulseWidth
Terminationasin
note7
2Q @ 1.5V
SYNC input to FEEDBACK delay
(measured at SYNC0 or 1 and FEEDBACK
inputpins)
Load = 50Ω to VCC/2,
CL = 20pF
(3)
SYNC-FEEDBACK
(9)
0.1MF from LF to Analog GND
CL = 50pF
tSKEWr
(rising)(3,4)
OutputtoOutputSkewbetweenoutputs2Q,
Q0-Q4,Q/2(risingedges only)
OutputtoOutputSkewbetweenoutputs2Q,
Q0-Q4(fallingedgesonly)
—
—
—
500
500
500
10
ps
ps
ps
ms
ns
ns
ns
tSKEWf
(falling)(3,4)
tSKEWALL(3,4)
OutputtoOutputSkew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time requiredtoacquirePhase-Lockfromtime
SYNC input signal is received
Propagation Delay, RST (HIGH-to-LOW) to any
Output(HIGH-to-LOW)
(6)
(2)
tLOCK
1
tRST
1.5(2)
8
Reset – Q
(10)
tREC
ResetRecoveryTime
9
5
—
—
Rising RST edge to falling SYNC edge
Minimum Pulse Width RST inputLOW
(10)
tW
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, CL = 50pF (±2pF), and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF (where C1 is loop filter
capacitor shown in Figure 2).
7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
by IDT, the termination scheme shown in Figure 1 must be used:
Rs
Zo (clock trace)
88915TT
2Q
Output
68040
P-Clock
Input
Rs = Zo - 7Ω
Rp
Rp = 1.5 Zo
Figure 1. MC68040 P-Clock Input Termination Scheme
5
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
GENERAL AC SPECIFICATION NOTES, CONTINUED
8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also, it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration:
PhaseRelationship
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
FrequencyRange(MHz)
Corresponding 2Q Output
FrequencyRange
of the Q Outputs
to Rising SYNC Edge
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Q/2
10to(2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
40to(2Q fMAX Spec)
5 to (2Q fMAX Spec)/8
10 to (2Q fMAX Spec)/4
10 to (2Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
20to(2QfMAX Spec)/2
20to(2QfMAX Spec)/2
20to(2QfMAX Spec)/2
20to(2QfMAX Spec)/2
0°
0°
Any Q (Q0-Q4)
Q5
2Q
180°
0°
Q/2
0°
Any Q (Q0-Q4)
0°
Q5
2Q
180°
0°
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input varies with process, temperature, and voltage. The phase
measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with the loop
filter connection shown in Figure 2 below:
LF
External Loop
Filter
C1
0.1µF
Analog GND
Figure 2. Loop Filter Connection
6
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
BOARD VCC
ANALOG VCC
Analog loop filter/VCO
section of the FCT88915TT
10μF
Low
0.1μF
High
LF
Freq.
Bypass
Freq.
Bypass
0.1μF (Loop
Filter Cap)
ANALOG GND
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the FCT88915TT in a normal digital environment.
BOARD GND
Figure 3. Recommended Loop Filter and Analog Isloation Scheme for the FCT88915TT
NOTES:
1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free
operation:
a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable
voltage transients at the LF pin.
b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915TT's sensitivity to voltage
transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 88915TT's
digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 3 is to give the 88915TT additional protection from the power supply and ground plane transients
that can occur in a high frequency, high speed digital system.
c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of Figure 3, there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board
ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass
capacitors should also be tied as close to the 88915TT package as possible.
7
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
ThefrequencyrelationshipshownhereisapplicabletoallQoutputs(Q0,Q1,
Q2, Q3 and Q4).
50 MHz signal
25 MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always runat2Xthe Q/2frequency, andthe 2Qoutputwillrunat4Xthe Q/2
frequency.
Q4
2Q
RST
Q5
12.5 MHz
signal
Q/2
Q3
Q2
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
LOW
25 MHz
input
25 MHz
"Q"
Clock
Outputs
FCT88915T
T
GND(AN
50 MHz signal
)
12.5 MHz feedback signal
FQ_SEL
Q0
Q1 PLL_EN
HIGH
HIGH
HIGH
2Q
Q/2
Q5
RST
Q4
FEEDBACK
REF_SEL
LOW
Allowable Input Frequency Range:
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW)
12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
Q3
Q2
SYNC(0)
VCC(AN)
LF
FCT88915TT
Figure 4b. Wiring Diagram and Frequency Relationships
with Q4 Output Feedback
GND(AN)
FQ_SEL
PLL_EN
HIGH
Q0
Q1
HIGH
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q
frequencywillequaltheSYNCfrequency. TheQ/2 output willalwaysrunat
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Allowable Input Frequency Range:
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q FMAX Spec)/8 (for FREQ_SEL LOW)
50 MHz feedback signal
HIGH
Figure 4a. Wiring Diagram and Frequency Relationships
with Q/2 Output Feedback
Q4
2Q
RST
Q5
12.5 MHz
input
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
Q/2
LOW
50 MHz
input
25 MHz
Q3
"Q"
Clock
FCT88915TT
Outputs
Q2
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4
frequency(andtherestofthe"Q"outputs)willequaltheSYNCfrequency. The
Q/2 output willalways runat1/2theQfrequency,andthe2Qoutputwillrun
at2Xthe Qfrequency.
GND(AN)
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
Allowable Input Frequency Range:
40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure 4c. Wiring Diagram and Frequency Relationships
with 2Q Output Feedback
8
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
FCT88915TT
PLL
2f
CLOCK
@f
SYSTEM
CLOCK
SOURCE
CMMU
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
FCT88915TT
PLL
2f
CMMU
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
FCT88915TT
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication
and Low Board-to-Board skew
FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY
WhenthePLL_ENpinisLOW,thePLLisbypassedandtheFCT88915TT
isinlowfrequency"testmode". Intestmode(withFREQ_SELHIGH),the2Q
outputisinvertedfromtheselectedSYNCinput,andtheQoutputsaredivide-
by-2(negativeedgetriggered)oftheSYNCinput,andtheQ/2outputisdivide-
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-
by-2oftheSYNC,theQoutputsdivide-by-4,andtheQ/2outputdivide-by-8.
Theserelationshipscanbeseenintheblockdiagram. Arecommendedtest
configurationwouldbetouseSYNC0orSYNC1asthetestclockinput,andtie
PLL_ENandREF_SELtogetherandconnectthemtothetestselectlogic.
Thisfunctionalityisneededsincemostboard-leveltestersrunat1MHzor
below,andtheFCT88915TTcannotlockontothatlowofaninputfrequency.
Inthetestmodedescribedabove,anytestfrequencytestcanbeused.
9
IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
CC
V
VOUT
IN
V
Pulse
Generator
D.U.T.
50pF
CL
500Ω
T
R
Test Circuits For All Outputs
1.5V
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
tCYCLE SYNC INPUT
tPD
FEEDBACK
INPUT
1.5V
Q/2 OUTPUT
tSKEWf
tSKEWr
tSKEWf
tSKEWr
tSKEWALL
1.5V
Q0-Q4
OUTPUTS
tCYCLE "Q" OUTPUTS
1.5V
1.5V
Q5 OUTPUT
2Q OUTPUT
Propagation Delay, Output Skew
(These waveforms represent the configuration shown in Figure 4a)
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input. Therefore, the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency, and the Q/2 output would run at half the SYNC frequency.
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IDT74FCT88915TT
LOWSKEWPLL-BASEDCMOSCLOCKDRIVER
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
X
X
Temp. Range
Device Type
Speed
Package
J
Plastic Leaded Chip Carrier
JG
PY
PYG
PLCC - Green
Small Shrink Outline IC
SSOP - Green
55(1)
55MHz Max. frequency
70MHz Max. frequency
100MHz Max. frequency
133MHz Max. frequency
70(1)
100(1)
133(1)
Low Skew PLL-Based CMOS Clock Driver
0°C to +70°C
88915TT
74
NOTE:
1. When ordering GREEN packages, replace this numeric value with the equivalent letter below.
A= 55 MHz
B= 70 MHz
C= 100 MHz
D= 133 MHz
For example, to order a 133MHz version, Green PLCC, the nomenclature would be 74FCT88915TTDPYG.
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for Tech Support:
clockhelp@idt.com
www.idt.com
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