IDT74LVC11ADC8 [IDT]
AND Gate, LVC/LCX/Z Series, 3-Func, 3-Input, CMOS, PDSO14, 1.27 MM PITCH, SOIC-14;型号: | IDT74LVC11ADC8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | AND Gate, LVC/LCX/Z Series, 3-Func, 3-Input, CMOS, PDSO14, 1.27 MM PITCH, SOIC-14 栅 光电二极管 |
文件: | 总5页 (文件大小:61K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS
IDT74LVC11A
TRIPLE 3-INPUT AND GATE
WITH 5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
TheLVC11Atriple3-input ANDgateis builtusingadvanceddualmetal
CMOS technology. The LVC11A device provides the 3-input AND
function.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
Inputs canbedrivenfromeither3.3Vor5Vdevices.This featureallows
the use ofthis device as a translatorina mixed3.3V/5Vsystemenviron-
ment.
TheLVC11Ahasbeendesignedwitha±24mAoutputdriver. Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
PINCONFIGURATION
VCC
1C
1Y
1
2
14
1A
1B
xA
13
12
11
10
9
xB
xC
xY
2A
3
4
3C
3B
2B
2C
5
6
7
3A
3Y
2Y
FUNCTIONTABLE(1)
GND
8
Inputs
Outputs
xA
L
xB
L
xC
L
xY
L
SOIC/ SSOP/ TSSOP
TOP VIEW
L
L
H
L
L
L
H
H
L
L
L
H
L
L
PINDESCRIPTION
H
H
H
H
L
Pin Number
1, 3, 9
2, 4, 10
7
Symbol
1A - 3A
1B - 3B
GND
Name and Function
L
H
L
L
Data Inputs
Data Inputs
Ground (0V)
Data Outputs
Data Inputs
H
H
L
H
H
NOTE:
12, 6, 8
13, 5, 11
14
1Y - 3Y
1C - 3C
VCC
1. H = HIGH Voltage Level
L = LOW Voltage Level
Positive SupplyVoltage
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
©1999 Integrated Device Technology, Inc.
DSC-5155/3
IDT74LVC11A
3.3VCMOSTRIPLE3-INPUTANDGATEWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
Symbol
–0.5 to +6.5
–65 to +150
–50 to +50
–50
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
° C
mA
mA
COUT
CI/O
5.5
IOUT
DC Output Current
6.5
IIK
Continuous Clamp Current,
VI < 0 or VO < 0
NOTE:
IOK
1. As applicable to the device type.
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
5
µA
µ A
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
50
µ A
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V, VIN = GND or VCC
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
500
µ A
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2
IDT74LVC11A
3.3VCMOSTRIPLE3-INPUTANDGATEWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
CPD
PowerDissipationCapacitanceperGate
CL = 0pF, f = 10Mhz
—
—
pF
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xA, xB, xC to xY
—
7
—
6.2
ns
tPHL
(2)
tSK(o)
OutputSkew
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
Skew between any two outputs of the same package and switching in the same direction.
2
3
IDT74LVC11A
3.3VCMOSTRIPLE3-INPUTANDGATEWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
VIH
VT
0V
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
SAME PHASE
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
Symbol
VLOAD
VIH
VCC(1)=2.5V±0.2V
VCC(2)= 3.3V±0.3V & 2.7V
Unit
V
VOH
VT
VOL
OUTPUT
2 x Vcc
Vcc
6
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
mV
mV
pF
LVC QUAD Link
VHZ
150
Propagation Delay
CL
30
VLOAD
Open
GND
VCC
DISABLE
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
Generator
SWITCH
CLOSED
VLZ
VOL
500Ω
RT
tPHZ
tPZH
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
LVC QUAD Link
0V
Test Circuit for All Outputs
LVC QUAD Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
Enable and Disable Times
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
SWITCHPOSITION
Test
Switch
VLOAD
GND
Open
VIH
DATA
INPUT
VT
Open Drain
Disable Low
Enable Low
0V
tSU
tH
VIH
VT
0V
TIMING
INPUT
Disable High
Enable High
tREM
VIH
SYNCHRONOUS
CONTROL
VT
0V
All Other Tests
VIH
VT
ASYNCHRONOUS
CONTROL
tSU
0V
tH
VIH
LVC QUAD Link
VT
0V
INPUT
Set-up, Hold, and Release Times
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
OUTPUT 1
tSK (x)
tSK (x)
VT
PULSE
VOH
tW
VT
VOL
OUTPUT 2
HIGH-LOW-HIGH
PULSE
VT
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
LVC QUAD Link
LVC QUAD Link
Pulse Width
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74LVC11A
3.3VCMOSTRIPLE3-INPUTANDGATEWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDT
XXXX
XX
LVC
Device Type Package
Temp. Range
Small Outline IC
DC
Shrink Small Outline Package
Thin Shrink Small Outline Package
TSSOP - Green
PY
PG
PGG
Triple 3-Input AND Gate, 24mA
-40°C to +85°C
11A
74
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