IDT74LVC137APG [IDT]
Decoder/Driver, LVC/LCX/Z Series, Inverted Output, CMOS, PDSO16, TSSOP-16;
| 型号： | IDT74LVC137APG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Decoder/Driver, LVC/LCX/Z Series, Inverted Output, CMOS, PDSO16, TSSOP-16 驱动 双倍数据速率 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS
3-LINE TO 8-LINE
IDT74LVC137A
DECODER/DEMULTIPLEXER,
WITH ADDRESS LATCHES
DESCRIPTION:
FEATURES:
–
–
0.5 MICRON CMOS Technology
The LVC137A 3-line to 8-line decoder/demultiplexer is built using
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
advanced dual metal CMOS technology. The LVC137A is designed for
high-performancememory-decodingordata-routingapplications requir-
ing very short propagation delay times. In high-performance memory
systems, this decoder minimizes the effects of system decoding. When
employedwithhigh-speedmemoriesutilizingafastenablecircuit,thedelay
times ofthis decoderandthe enable time ofthe memoryare usuallyless
thanthe typicalaccess time ofthe memory.This means thatthe effective
systemdelayintroducedbythe decoderis negligible.
–
–
–
–
–
–
–
–
VCC = 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
When the latch enable (G2A) input is low, the LVC137A acts as a
decoder/demultiplexer.WhenG2Atransitionsfromlowtohigh,theaddress
presentattheinputs (A,B,andC)is storedinthelatches.Furtheraddress
changes areignored,providedG2Aremains high.Theoutput-enable(G1
andG2B)inputs controlthe outputs independentlyofthe selectorlatch-
enable inputs.Allofthe outputs are forcedhighifG1is loworG2Bis high.
Drive Features for LVC137A:
–
–
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Inputscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC137A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
FunctionalBlockDiagram
15
1
A
Y0
14
Y1
13
2
Y2
B
Select
Inputs
12
Y3
Data
Outputs
11
Y4
3
C
10
Y5
9
Y6
4
Latch
G2A
8
Enable
Y7
5
G2B
Output
6
Enables
G1
EXTENDED COMMERCIAL TEMPERATURE RANGE
MAY 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4753/1
IDT74LVC137A
3.3VCMOS3-LINETO8-LINEDECODER/DEMULTIPLEXER
EXTENDEDCOMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Description
Max.
Unit
1
2
3
A
B
16
15
14
13
(2)
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
VTERM
Terminal Voltage with Respect to GND
– 0.5 to +6.5
V
(3)
VTERM
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
V
TSTG
IOUT
°C
C
DC Output Current
mA
mA
G2A
4
5
SO16-7
SO16-8
SO16-9
SO16-10
IIK
Continuous Clamp Current,
VI < 0 or VO < 0
IOK
ICC
G2B
G1
12
11
10
9
Continuous Current through
±100
mA
6
ISS
each VCC or GND
LVC QUAD Link
7
8
Y7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
GND
SOIC/ SSOP/ TSSOP/ QSOP
TOP VIEW
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
PIN DESCRIPTION
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
Pin Names
Description
G
Output Enable
1
CIN
Input Capacitance
VIN = 0V
4.5
6
8
pF
pF
G2A
G2B
Latch Enable (Active LOW)
Output Enable (Active LOW)
Data Outputs
COUT
Output
VOUT = 0V
5.5
Capacitance
I/O Port
Yx
CI/O
VIN = 0V
6.5
8
pF
A, B, C
Select Data Inputs
Capacitance
LVC QUAD Link
NOTE:
1. As applicable to the device type.
FUNCTION TABLE(1)
Inputs
Select Inputs
Outputs
Latch
Enable
Output
Enable
G2A
X
X
L
G1
X
L
G2B
H
X
L
C
X
X
L
B
X
X
L
A
X
X
L
Y
Y
Y
Y
Y
Y
Y
Y
7
0
1
2
3
4
5
6
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
X
H
H
H
H
L
H
H
X
H
H
L
L
H
X
H
H
L
Outputs corresponding to stored address = L; all other outputs = H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2
IDT74LVC137A
3.3VCMOS3-LINETO8-LINEDECODER/DEMULTIPLEXER
EXTENDEDCOMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°c to +85°c
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max. Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
—
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
0.7
0.8
±5
V
IIH
VI = 0 to 5.5V
µA
µA
IIL
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC – 0.6V
other inputs at VCC or GND
—
—
500
µA
LVC QUAD Link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
2
—
—
V
VCC = 2.3V
1.7
2.2
2.4
2.2
—
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
LVC QUAD Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
c
1998 Integrated Device Technology, Inc.
DSC-123456
3
IDT74LVC137A
3.3VCMOS3-LINETO8-LINEDECODER/DEMULTIPLEXER
EXTENDEDCOMMERCIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, T = 25°C
A
VCC = 2.5V±0.2V
VCC = 3.3V±0.3V
Unit
Symbol
Parameter
Test Conditions
Typical
Typical
pF
CPD
Power Dissipation Capacitance
CL = 0pF, f = 10Mhz
—
25
SWITCHING CHARACTERISTICS (1)
VCC = 2.5V±0.2V
VCC = 2.7V
VCC = 3.3V±0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tW
Parameter
Propagation Delay
A to B, C to Yx
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
—
—
—
—
6.9
8.5
8.2
1
6.2
7.8
7.5
ns
ns
ns
Propagation Delay
G2A to Yx
—
—
—
—
1
1
Propagation Delay
G1 or G2B to Yx
Pulse Duration, G2A
3
2
—
—
—
—
3
—
—
—
—
3
—
—
—
1
ns
ns
ns
ns
tSU
tH
Setup Time, at A, B, and C before G2A↓
Hold Time, at A, B, and C after G2A↓
2.1
1.1
—
1.9
1.1
—
1.2
—
(2)
tSK(0)
Output Skew
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC137A
3.3VCMOS3-LINETO8-LINEDECODER/DEMULTIPLEXER
EXTENDEDCOMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
PROPAGATIONDELAY
TESTCONDITIONS
(1)
(2)
VCC = 2.5V ±0.2V
VCC = 3.3V ±0.3V & 2.7V
Symbol
Unit
VIH
VLOAD
2 x Vcc
Vcc
6
V
SAME PHASE
V
T
VIH
VT
2.7
1.5
300
300
50
V
V
INPUT TRANSITION
0V
tPHL
tPHL
tPLH
tPLH
VCC / 2
150
V
V
OH
T
OUTPUT
V
LZ
mV
mV
VOL
VHZ
CL
150
VIH
OPPOSITE PHASE
INPUT TRANSITION
30
pF
LVC QUAD Link
V
T
0V
LVC QUAD Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
VLOAD
VCC
Open
GND
DISABLE
ENABLE
500Ω
500Ω
VIH
VT
CONTROL
INPUT
VIN
VOUT
Pulse(1, 2)
Generator
D.U.T.
0V
tPZL
tPLZ
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
RT
CL
VLZ
VOL
tPHZ
tPZH
LVC QUAD Link
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
DEFINITIONS:
VT
0V
CL= Load capacitance: includes jig and probe capacitance.
0V
RT = Termination resistance: should be equal to ZOUT of the Pulse
LVC QUAD Link
Generator.
NOTE:
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
SWITCHPOSITION
SET-UP, HOLD, AND RELEASE TIMES
Test
Switch
VIH
VT
0V
DATA
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tSU
tH
VIH
VT
0V
TIMING
INPUT
GND
Open
tREM
VIH
VT
0V
SYNCHRONOUS
CONTROL
LVC QUAD Link
VIH
VT
0V
ASYNCHRONOUS
CONTROL
tSU
OUTPUT SKEW - tsk (x)
tH
VIH
LVC QUAD Link
VT
0V
INPUT
tPLH1
tPHL1
VOH
PULSEWIDTH
VT
LOW-HIGH-LOW
PULSE
OUTPUT 1
tSK (x)
VOL
tSK (x)
VT
VOH
tW
VT
OUTPUT 2
VOL
HIGH-LOW-HIGH
PULSE
VT
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
LVC QUAD Link
LVC QUAD Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC137A
3.3VCMOS3-LINETO8-LINEDECODER/DEMULTIPLEXER
EXTENDEDCOMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
IDT
XXXX
XX
LVC
Temp. Range
Quarter Size Outline Package (SO16-7)
Q
Small Outline IC (SO16-8)
Shrink Small Outline Package (SO16-9)
Thin Shrink Small Outline Package (SO16-10)
DC
PY
PG
3-Line to 8-Line Decoder/Demultiplexer
with Address Latches, ±24mA
137A
74
-40°C to +85°C
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
相关型号：
©2020 ICPDF网 联系我们和版权申明