IDT74LVC161APY8 [IDT]
Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, SSOP-16;
| 型号： | IDT74LVC161APY8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, SSOP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
IDT74LVC161A
COUNTER WITH ASYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
FEATURES:
counting. Synchronousoperationisprovidedbyhavingallflip-flopsclocked
simultaniouslyonthepositive-goingedgeoftheclock(CP). Outputs (Q0 to
Q3) of the counters maybe preset toa highorlowlevel. Alowlevel atthe
parallelenableinput(PE)disables thecountingactionandcauses thedata
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
–
atinputs (D toD )tobeloadedintothecounteronthepositive-goingedge
3
oftheclock0(providedthattheset-upandholdtimerequirements forPEare
met). Presettakes placeregardless ofthelevels atthecountenableinputs
(CEPandCET). Alowlevelatthemasterresetinput(MR)setsallfouroutputs
oftheflip-flops(Q0toQ3)tolowlevelregardlessofthelevelsatCP,PE,CET,
and CEP inputs (thus providing an asynchronous clear function).
–
–
–
–
–
–
–
VCC = 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
The look-aheadcarrysimplifies serialcascadingofthe counters. Both
countenable inputs (CEPandCET)mustbe hightocount. The CETinput
is fedforwardtoenabletheterminalcountoutput(TC). TheTCoutputthus
enabledwillproduceahighoutputpulseofadurationapproximatelyequal
to a high level output of Q0. This pulse can be used to enable the next
cascadedstage. Themaximumclockfrequencyforthecascadedcounters
isdeterminedbytheCPtoTCpropagationdelayandCEPtoCPset-uptime,
accordingtothefollowingformula:
Drive Features for LVC161A:
–
–
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
1
DESCRIPTION:
fmax
=
tp(max) (CP to TC) + tsu (CEP to CP)
TheLVC161Ais ahigh-performance,low-power,low-voltage,Si-gate
CMOSdevice,superiortomostadvancedCMOS-compatibleTTLfamilies.
Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC161A is a presettable synchronous binary counter which
features an internal look-ahead carry and can be used for high-speed
FUNCTIONALDIAGRAM
STATEDIAGRAM
5
3
4
6
0
1
2
3
4
5
6
7
8
D0
D1
D2
D3
9
PE
PARALLEL LOAD
CIRCUITRY
15
14
13
12
CET
CEP
10
15
TC
7
BINARY COUNTER
2
1
CP
MR
11
10
9
Q0
Q1
Q2
Q3
14
13
12
11
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-5156/-
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
FUNCTIONALBLOCKDIAGRAM
D0
D1
D2
D3
CET
CEP
PE
FF3
FF0
FF1
FF2
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
CP
CP
CP
CP
R
D
R
D
R
D
R
D
MR
Q0
Q1
Q2
Q3
TC
2
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
TYPICAL TIMING SEQUENCE
ABSOLUTE MAXIMUM RATINGS (1)
MR
Symbol
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max.
Unit
V
VTERM
TSTG
IOUT
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
PE
°C
D0
D1
DC Output Current
mA
mA
IIK
Continuous Clamp Current,
VI < 0 or VO < 0
D2
IOK
ICC
Continuous Current through
±100
mA
D3
CP
ISS
each VCC or GND
LVC QUAD Link
NOTE:
CEP
CET
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Q0
Q1
Q2
Q3
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
TC
2
15
12
13
14
0
1
CIN
Input Capacitance
VIN = 0V
4.5
6
8
pF
pF
RESET PRESET
COUNT
INHIBIT
COUT
Output
VOUT = 0V
5.5
Capacitance
I/O Port
CI/O
VIN = 0V
6.5
8
pF
Capacitance
LVC QUAD Link
PINCONFIGURATION
NOTE:
1. As applicable to the device type.
16
15
14
VCC
TC
Q0
MR
CP
D0
1
2
PIN DESCRIPTION
Pin Names
Description
3
4
MR
Asynchronous Master Reset (Active LOW)
Clock Input (LOW-to-HIGH, Edge-Triggered)
Data Inputs
Q
1
SO16-7 13
D1
D2
CP
SO16-8
SO16-9
SO16-10
Dx
12
Q2
5
6
7
8
CEP
GND
PE
Count Enable Inputs
D3
11
Q3
Ground (0V)
Parallel Enable Input (Active LOW)
Count Enable Carry Input
Flip-Flop Outputs
CET
PE
CEP
GND
10
9
CET
Qx
TC
Terminal Count Output
Vcc
Positive Supply Voltage
SOIC/ SSOP/ TSSOP/ QSOP
TOP VIEW
3
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
FUNCTION TABLE (1)
OPERATING
INPUTS
OUTPUTS
MODES
Reset (clear)
MR
L
CP
X
CEP
X
CET
X
PE
X
l
Dx
X
l
Qx
L
TC
L
H
X
X
L
L
↑
Parallel load
H
H
H
H
X
h
X
h
l
h
H
count
Q0
*
*
*
L
↑
Count
h
h
h
X
X
X
↑
X
l
X
l
Hold
(do nothing)
X
X
Q0
NOTE:
1. H = HIGH Voltage Level
h = HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW Voltage Level
l = LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition.
Q0 = Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.
X = Don’t care
* = The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).
↑
= LOW-to-HIGH clock transition
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°c to +85°c
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max. Unit
(2)
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
—
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
0.7
0.8
±5
V
IIH
VI = 0 to 5.5V
µA
µA
IIL
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC – 0.6V
other inputs at VCC or GND
—
—
500
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. Clock Pin (CP) requires a minimum VIH of 2.5V.
c
1998 Integrated Device Technology, Inc.
4
DSC-123456
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2.2
—
—
—
—
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3.0V
LVC QUAD Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, T = 25°C
A
VCC = 2.5V±0.2V
VCC = 3.3V±0.3V
Unit
Symbol
Parameter
Test Conditions
Typical
Typical
CPD
Power Dissipation Capacitance
CL = 0pF, f = 10Mhz
—
—
pF
5
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V
VCC = 3.3V±0.3V
Symbol
tPHL
Parameter
Propagation Delay
Min.
Max.
Min.
Max.
Unit
—
9
—
8
ns
tPLH
CP to Qx
tPHL
Propagation Delay
CP to TC
—
—
—
—
5
11
8.8
10
11
—
—
—
—
—
—
—
—
—
—
—
—
4
9.5
7.8
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
CET to TC
tPLH
tPHL
Propagation Delay
MR to Qx
tPHL
tW
Propagation Delay
MR to TC
10
—
—
—
—
—
—
—
500
Clock Pulse Width
HIGH or LOW
Master Reset
width LOW
tW
4
3
tREM
tSU
tSU
tSU
tH
Removal Time
MR to CP
0.5
3.5
3.5
5.5
0
0.5
3
Set-Up Time
Dx to CP
Set-Up Time
PE to CP
3
Set-Up Time
CEP, CET to CP
Hold Time
5
0
ns
ps
Dx, PE, CEP, CET to CP
(2)
tSK(o) Output Skew
—
—
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
6
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
TESTCIRCUITSANDWAVEFORMS
PROPAGATIONDELAY
TESTCONDITIONS
(1)
(2)
VCC = 2.5V ±0.2V
VCC = 3.3V ±0.3V & 2.7V
Symbol
Unit
VIH
VLOAD
2 x Vcc
Vcc
6
V
SAME PHASE
V
T
VIH
VT
2.7
1.5
300
300
50
V
V
INPUT TRANSITION
0V
tPHL
tPHL
tPLH
tPLH
VCC / 2
150
V
V
OH
T
OUTPUT
V
LZ
mV
mV
VOL
VHZ
CL
150
VIH
OPPOSITE PHASE
INPUT TRANSITION
30
pF
LVC QUAD Link
V
T
0V
LVC QUAD Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
VLOAD
VCC
Open
GND
DISABLE
ENABLE
500Ω
500Ω
VIH
VT
CONTROL
INPUT
VIN
VOUT
Pulse(1, 2)
Generator
D.U.T.
0V
tPZL
tPLZ
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
RT
CL
VLZ
VOL
tPHZ
tPZH
LVC QUAD Link
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
0V
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
LVC QUAD Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
SET-UP, HOLD, AND RELEASE TIMES
SWITCHPOSITION
Test
Switch
VIH
VT
0V
DATA
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V
LOAD
tSU
tH
VIH
VT
0V
TIMING
INPUT
GND
Open
tREM
VIH
VT
0V
SYNCHRONOUS
CONTROL
VIH
VT
0V
LVC QUAD Link
ASYNCHRONOUS
CONTROL
tSU
OUTPUT SKEW - tsk (x)
tH
VIH
LVC QUAD Link
VT
0V
INPUT
tPLH1
tPHL1
VOH
PULSEWIDTH
VT
LOW-HIGH-LOW
PULSE
OUTPUT 1
tSK (x)
VOL
tSK (x)
VT
VOH
tW
VT
OUTPUT 2
VOL
HIGH-LOW-HIGH
PULSE
VT
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
LVC QUAD Link
LVC QUAD Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
7
IDT74LVC161A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER
ORDERINGINFORMATION
XX
Device Type Package
XX
IDT
Temp. Range
LVC
XXXX
Q
Quarter Size Outline Package (SO16-7)
DC
PY
PG
Small Outline IC (SO16-8)
Shrink Small Outline Package (SO16-9)
Thin Shrink Small Outline Package (SO16-10)
161A
Presettable Synchronous 4-Bit Binary Counter with Asynchro-
nous Reset, 5 Volt Tolerant I/O, ±24mA
–40°C to +85°C
74
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8
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