IDT74LVC16543APA8 [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56;


型号：	IDT74LVC16543APA8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 光电二极管输出元件逻辑集成电路
文件：	总6页 (文件大小：83K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC16543A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

IDT74LVC16543A

3.3V CMOS 16-BIT

REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

The LVC16543A 16-bit registered transceiver is built using advanced

dual metal CMOS technology. This high-speed, low-power device can be

used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-

enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are

provided for each register to permit independent control in either direction

of data flow. For example, theA-to-B enable (CEAB) must be low to enter

data from the A port or to output data from the B port. LEAB controls the

latch function. When LEAB is low, the latches are transparent. A subse-

quent low-to-high transition of LEAB signal puts theAlatches in the storage

mode. OEAB performs the output enable function on the B port. Data flow

from the B port to theAport is similar but requires using CEBA, LEBA, and

OEBA inputs. Flow-through organization of signal pins simplifies layout.All

inputs are designed with hysteresis for improved noise margin.

All pins of this 16-bit latched transceiver can be driven from either 3.3V

or 5V devices. This feature allows the use of this device as a translator in

a mixed 3.3V/5V supply system.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVC16543A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

FUNCTIONALBLOCKDIAGRAM

2OEBA

1OEBA

2CEBA

1CEBA

2LEBA

1LEBA

2OEAB

1OEAB

2CEAB

1CEAB

2LEAB

1LEAB

2A1

1A1

2B1

1B1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JULY 1999

DSC-4730/2

IDT74LVC16543A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

1OEAB

1OEBA

1LEBA

IOUT

DC Output Current

1LEAB

1CEAB

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1CEBA

GND

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1A1

1A2

VCC

1A3

1B1

1B2

VCC

1B3

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1A4

1A5

1B4

1B5

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

GND

1A6

GND

1B6

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

1A7

1A8

1B7

1B8

2B1

2B2

2B3

6.5

NOTE:

1. As applicable to the device type.

2A1

2A2

2A3

PINDESCRIPTION

Pin Names

Description

GND

xOEAB

xOEBA

xCEAB

xCEBA

xLEAB

xLEBA

xAx

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Enable Input (Active LOW)

GND

2A4

2A5

2A6

VCC

2A7

2A8

2B4

2B5

2B6

VCC

2B7

2B8

B-to-A Enable Input (Active LOW)

A-to-B Latch Enable Input (Active LOW)

B-to-A Latch Enable Input (Active LOW)

A-to-BDataInputsorB-to-A3-StateOutputs

B-to-ADataInputsorA-to-B3-StateOutputs

xBx

GND

(1,2)

FUNCTION TABLE (EACH 8-BIT SECTION)

2CEBA

2LEBA

2CEAB

2LEAB

2OEAB

Inputs

Outputs

xCEAB

xLEAB

xOEAB

xAx

xBx

2OEBA

B⁽³⁾

SSOP/ TSSOP/ TVSOP

TOP VIEW

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

2. A-to-B data flow is shown. B-to-A data flow is similar but uses CEBA, LEBA, and OEBA.

3. Output level before the indicated steady-state input conditions were established.

IDT74LVC16543A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVC16543A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPZH

tPZL

tPHZ

tPLZ

tPHZ

tPLZ

tSU

Parameter

Min.

Max.

Unit

PropagationDelay

—

6.1

1.2

5.4

xAx to xBx or xBx to xAx

PropagationDelay

—

7.4

7.9

7.6

7.1

6.9

1.5

1.2

6.1

6.6

6.3

6.6

6.3

xLEBA or xLEAB to xAx or xBx

OutputEnableTime

xCEBA or xCEAB to xAx or xBx

OutputEnableTime

xOEBA or xOEAB to xAx or xBx

OutputDisableTime

1.5

xCEBA or xCEAB to xAx or xBx

OutputDisableTime

xOEBA or xOEAB to xAx or xBx

Set-upTime,databeforeCE↑

Set-upTime, databeforeLE↑, CELOW

HoldTime, dataafterCE↑

Hold Time, data after LE↑, CE LOW

Pulse Duration, xLEBA or xLEAB, xCEBA or xCEAB LOW

OutputSkew⁽²⁾

1.1

1.9

3.3

—

1.1

1.9

3.3

—

tSU

—

tSK(o)

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC16543A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC16543A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

XXXX

LVC

Device Type Package

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Registered Transceiver with 3-State Outputs,

5 Volt Tolerant I/O

543A

Double-Density with Resistors, ±24mA

Blank

No Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT74LVC16543APA8 [IDT]

相关型号：

IDT74LVC16543APF

IDT74LVC16543APV

IDT74LVC16543APV8

IDT74LVC16601A

IDT74LVC16601APA

IDT74LVC16601APAG

IDT74LVC16601APAG8

IDT74LVC16601APF

IDT74LVC16601APV

IDT74LVC16601APV8

IDT74LVC16601APVG

IDT74LVC16601APVG8