IDT74LVC16Z646APV8 [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56;
| 型号： | IDT74LVC16Z646APV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74LVC16Z646A
3.3V CMOS 16-BIT BUS
TRANSCEIVER/REGISTER
WITH ZERO HOLD TIME, 3-STATE
OUTPUTS, 5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
TheLVC16Z646A16-bitbustransceiver/registerisbuiltusingadvanced
dual metal CMOS technology. This high-speed, low power device is
organizedastwoindependent8-bitD-typetransceiverswith3-stateD-type
registers. Thecontrolcircuitryisorganizedformultiplexedtransmissionof
databetweentheAbusandBbuseitherdirectlyorfromtheinternalstorage
registers. Each 8-bit transceiver/register features direction control (DIR),
over-riding Output Enable control (OE) and Select lines (SAB and SBA) to
select either real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriateclockpins. Flow-throughorganizationofsignalpinssimplifies
layout. All inputs are designed with hysteresis for improved noise margin.
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16Z646A has been designed with a ±24mA output driver. The
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
29
1OE 56
2OE
1
28
1DIR
2DIR
55
30
2CLKBA
1CLKBA
54
1SBA
31
27
2SBA
2
2CLKAB
1CLKAB
26
3
2SAB
1SAB
B REG
1D
B REG
1D
C1
C1
5
15
42
52
2A1
A REG
1D
2B1
1A1
A REG
1D
1B1
C1
C1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
AUGUST 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-5165/1
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1
2
56
55
54
53
52
1OE
1DIR
IOUT
DC Output Current
1CLKBA
1CLKAB
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
1SBA
GND
1B1
1SAB
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
4
5
6
GND
1A1
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1B2
VCC
1A2
VCC
51
50
49
48
7
8
1B3
1B4
1A3
1A4
9
10
47
46
45
44
1B5
1A5
GND
1A6
11
12
13
14
15
16
17
18
GND
1B6
CAPACITANCE (TA = +25°C, F = 1.0MHz)
1A7
1B7
1B8
2B1
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
43
42
1A8
2A1
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
41
6.5
2B2
2A2
NOTE:
40
39
38
2B3
2A3
1. As applicable to the device type.
GND
GND
2B4
2B5
19
20
21
22
23
2A4
2A5
37
36
35
34
33
2B6
VCC
2B7
2A6
VCC
2A7
PINDESCRIPTION
24
2B8
2A8
Pin Names
Description
GND
GND
25
26
27
32
31
30
29
xAx
Data Register A Inputs
Data Register B 3-State Outputs
DataRegisterBInputs
2SBA
2SAB
xBx
2CLKBA
2CLKAB
DataRegisterA3-StateOutputs
Clock Pulse Inputs
28
2OE
2DIR
xCLKAB, xCLKBA
xSAB, xSBA
xOE
OutputDataSourceSelectInputs
OutputEnableInputs(ActiveLOW)
SSOP/ TSSOP/ TVSOP
TOP VIEW
xDIR
DirectionControlInputs
2
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
Inputs
Data I/O(2)
xOE
X
xDIR
X
xCLKAB
xCLKBA
xSAB
xSBA
xAx
Input
Unspecified(2)
xBx
Operation or Function
Store A, B unspecified(2)
Store B, A unspecified(2)
Store A and B data
↑
X
↑
X
X
X
X
X
X
X
L
X
X
X
X
L
Unspecified(2)
X
X
↑
↑
Input
H
H
L
X
Input
Input
X
H or L
H or L
Input
Input
Isolation,holdstorage
L
X
X
Output
Output
Input
Input
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
L
L
X
H or L
X
H
X
X
Input
L
H
X
Output
Output
L
H
H or L
X
H
Input
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
↑ = LOW-to-HIGH transition
2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will
be stored on every LOW-to-HIGH transition of the clock inputs.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
3
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
BUS
A
BUS
B
BUS
A
BUS
B
xCLKBA xSAB
xDIR xOE xCLKAB
xSBA
L
xCLKBA xSAB
xDIR xOE xCLKAB
xSBA
X
X
X
L
L
X
X
L
H
L
X
REAL-TIME TRANSFER
BUS A TO B
REAL-TIME TRANSFER
BUS B TO A
BUS
A
BUS
A
BUS
B
BUS
B
(1) xOE xCLKAB
xSBA
H
X
xCLKBA xSAB
xOE xCLKAB
xSBA
xCLKBA xSAB
xDIR
X
X
xDIR
L
H
X
↑
↑
X
X
X
X
X
X
X
X
H or L
X
X
H
↑
X
L
L
X
H or L
H
X
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED
DATA TO AAND/OR B
NOTE:
1. Cannot transfer data to A Bus and B Bus simultaneously.
4
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
—
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
—
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
2
6
2
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
xAx to xBx or xBx to xAx
PropagationDelay
2
2
7
7
2
2
2
2
2
2
3
0
6
6
CLKBA to xAx, CLKAB to xBx
PropagationDelay
xSBA or xSAB to xAx or xBx
OutputEnableTime
2
8.5
8.5
7
7.5
7.5
6
xOE to xAx or Bx
OutputEnableTime
2
xDIR to xAx or Bx
OutputDisableTime
2
xOE to xAx or Bx
OutputDisableTime
2
7
6
xDIR to xAx or Bx
Set-up Time HIGH or LOW
xAx or xBx before CLKAB↑ or CLKBA↑
Hold Time HIGH or LOW
xAx or xBx after CLKAB↑ or CLKBA↑
Clock Pulse Width HIGH or LOW
OutputSkew(2)
3.5
0
—
—
—
—
tH
tW
3
—
3
—
ns
ps
tSK(o)
—
—
—
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
VLOAD
VIH
6
6
2 x Vcc
Vcc
tPLH
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VT
Vcc / 2
150
V
tPHL
tPLH
VLZ
VHZ
CL
mV
mV
pF
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
150
30
LVC Link
VLOAD
Open
GND
Propagation Delay
VCC
DISABLE
ENABLE
VIH
VT
500Ω
CONTROL
INPUT
VIN
VOUT
0V
Pulse (1, 2)
tPZL
tPLZ
D.U.T.
Generator
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
RT
CL
tPHZ
tPZH
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
Test Circuit for All Outputs
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
VT
0V
Test
Switch
VLOAD
GND
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
tREM
ASYNCHRONOUS
CONTROL
Disable High
Enable High
SYNCHRONOUS
CONTROL
All Other Tests
Open
tSU
tH
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
VT
VOL
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74LVC16Z646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
X
XX
XXXX
IDT
XX
LVC
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Bus Transceiver/Register with Zero Hold Time,
3-State Outputs, 5V Tolerant I/O
646A
16Z
Double-Density, ±24mA
Blank
74
No Bus-hold
-40°C to +85°C
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7
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