IDT74LVC2952APY8 [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SSOP-24;型号: | IDT74LVC2952APY8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SSOP-24 光电二极管 |
文件: | 总6页 (文件大小:73K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS OCTAL BUS
TRANSCEIVER AND
IDT74LVC2952A
REGISTER WITH 3-STATE OUT-
PUTS AND 5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
–
–
0.5 MICRON CMOS Technology
The LVC2952A octal bus transceiver and register is built using ad-
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
vanced dual metal CMOS technology. This high speed low power device
isorganizedas8-bitback-to-backregisterswithseparateinputandoutput
control for indepedent control of data flow in either direction. Data on the
AorBbusisstoredintheregistersonthelow-to-hightransitionoftheclock
(CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or
CLKENBA) input is low. Taking the output-enable (OEABorOEBA) input
low accesses the data of either port.
–
–
–
–
–
–
–
–
VCC = 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
Allpinscanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
Drive Feature for LVC2952A:
Balanced Output Drivers: ±24mA
The LVC2952A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
–
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
11
CLKENAB
10
CLK
3
CLKENBA
CLKBA
OEBA
C1
8
16
1D
B1
C1
1D
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4581/-
IDT74LVC2952A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Max.
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
24
23
22
21
20
19
18
17
16
15
14
13
1
VCC
A8
B8
B7
°C
IOUT
DC Output Current
– 50 to +50
– 50
mA
mA
2
3
4
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
A7
B6
B5
B4
B3
Continuous Current through
±100
mA
A6
ISS
each VCC or GND
A5
8LVC
5
SO24-2
SO24-7
SO24-8
SO24-9
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
A4
6
A3
B2
B1
7
A2
8
OEAB
CLKAB
A1
9
OEBA
10
11
12
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CLKBA
CLKENAB
GND
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
CLKENBA
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
5.5
6.5
8
pF
8
pF
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
Capacitance
8LVC Link
NOTE:
1. As applicable to the device type.
FUNCTION TABLE (1, 2)
PIN DESCRIPTION
Pin Names
Description
Inputs
Outputs
Bx
OEAB
OEBA
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
CLKENAB CLKAB
OEAB
Ax
(3)
B0
H
X
X
L
X
CLKENAB
CLKENBA
CLKAB
CLKBA
Ax
(3)
B0
H or L
L
X
L
↑
↑
X
L
L
L
H
X
L
H
Z
L
X
B-to-A Clock Input
H
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES:
BX
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. A-to-B data flow is shown; B-to-A flow control is similar but uses
CLKENBA, CLKBA, and OEBA.
3. B0 = Level of B before the indicated steady-state input conditions
were established.
2
IDT74LVC2952A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C To +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
—
—
0.7
0.8
±5
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
V
IIH
IIL
VI = 0 to 5.5V
µA
µA
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
VH
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
(2)
—
—
—
—
10
3.6 ≤ VIN ≤ 5.5V
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC - 0.6V,
other inputs at VCC or GND
500
µA
8LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
—
—
V
2
VCC = 2.3V
1.7
2.2
2.4
2.2
—
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
8LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
3
IDT74LVC2952A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, V
= 3.3V ± 0.3V, T = 25°C
CC
A
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
Power Dissipation Capacitance per Transceiver Outputs enabled
Power Dissipation Capacitance per Transceiver Outputs disabled
CL = 0, f = 10Mhz
79
pF
CPD
41
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
—
—
150
—
150
1
—
MHz
ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.8
8.2
7.8
7.8
—
—
—
—
—
1
CLKAB or CLKBA to Bx or Ax
Output Enable Time
OEBA or OEAB to Ax or Bx
Output Disable Time
OEBA or OEAB to Ax or Bx
Set-up Time,
Data Before CLK↑ HIGH
Hold Time,
Data After CLK↑ HIGH
Set-up Time,
—
9
1
ns
ns
ns
ns
ns
ns
ns
ns
—
8.8
—
—
—
—
—
—
1
1.7
1.8
1.3
1.4
3.3
—
1.3
1.1
1.1
1.1
3.3
—
tH
tSU
tH
CLKEN Before CLK↑ HIGH
Hold Time,
CLKEN After CLK↑ HIGH
Pulse Duration,
tW
CLK HIGH or LOW
(2)
tSK(0)
Output Skew
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC2952A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
PROPAGATIONDELAY
VIH
VT
0V
(1)
(1)
(2)
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Symbol
Unit
SAME PHASE
VLOAD
6
6
2 x Vcc
Vcc
V
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VOH
VT
OUTPUT
VCC / 2
150
V
VOL
VLZ
VHZ
CL
mV
mV
VIH
VT
0V
150
OPPOSITE PHASE
INPUT TRANSITION
30
pF
8LVC Link
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
VLOAD
VCC
DISABLE
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse (1, 2)
Generator
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL+VLZ
VOL
RT
tPHZ
tPZH
CL
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VT
0V
VOH-VHZ
LVC Link
0V
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
LVC Link
RT = Termination resistance: should be equal to ZOUT of the Pulse
NOTE:
Generator.
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
SWITCHPOSITION
VIH
VT
0V
DATA
INPUT
Test
Switch
tSU
tH
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
VIH
VT
0V
TIMING
INPUT
tREM
VIH
VT
0V
GND
ASYNCHRONOUS
CONTROL
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
8LVC Link
tSU
tH
OUTPUT SKEW - tsk (x)
VIH
LVC Link
VT
0V
INPUT
PULSEWIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
OUTPUT 1
OUTPUT 2
VOL
VT
tSK (x)
tSK (x)
VOH
tW
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
LVC Link
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC2952A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
LVC
Temp. Range
X
IDT
XX
XXXX
XX
Bus-Hold Device Type Package
Small Outline IC (gull wing) (SO24-2)
SO
PY
Q
Shrink Small Outline Package (SO24-7)
Quarter Size Small Outline Package (SO24-8)
Thin Shrink Small Outline Package (SO24-9)
PG
2952A
Octal Bus Transceiver and Register with 3-State Outputs, ±24mA
Blank
74
No Bus-hold
–40°C to +85°C
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
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