IDT74LVC827A [IDT]
3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O; 3.3V CMOS 10位缓冲器/驱动器具有三态输出和5V兼容的I / O
| 型号： | IDT74LVC827A |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O |
| 文件： | 总6页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS OCTAL
IDT74LVC373A
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
TheLVC373AOctaltransparentD-typelatchisbuiltusingadvanceddual
metalCMOStechnology.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
Whilethelatch-enable(LE)inputishigh,theQoutputsfollowthedata(D)
inputs. When LE is taken low, the Q outputs are latched at the logic levels
set up at the D inputs.
Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs
in either a normal logic state (high or low logic levels) or a high-impedance
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latch. Old data can be
retained or new data can be entered while the outputs are in the high-
impedancestate.
Toensurethehigh-impedancestateduringpoweruporpowerdown,OE
should be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.
• Available in SOIC, SSOP, QSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
1
OE
11
LE
C1
1D
2
1Q
3
1D
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4640/1
IDT74LVC373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
20
19
18
17
16
15
14
13
12
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
1
2
3
4
OE
1Q
IOUT
DC Output Current
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
1D
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
2D
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2Q
5
3Q
6
3D
7
4D
8
CAPACITANCE (TA = +25°C, F = 1.0MHz)
4Q
9
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
GND
10
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
5.5
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
6.5
NOTE:
1. As applicable to the device type.
PINDESCRIPTION
Pin Names
Description
OE
LE
Output Enable Inputs (Active LOW)
Latch Enable Input
xD
xQ
Data Inputs
3-State Data Outputs
(1)
FUNCTION TABLE (EACH LATCH)
Inputs
Outputs
xQ
xD
LE
OE
H
L
H
H
L
L
L
L
H
L
Q(2)
X
X
X
H
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74LVC373A
INDUSTRIALTEMPERATURERANGE
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperLatchOutputsenabled
PowerDissipationCapacitanceperLatchOutputsdisabled
CL = 0pF, f = 10Mhz
46
3
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tW
Parameter
Min.
Min.
Max.
Unit
PropagationDelay
xD to xQ
—
7.8
1.5
6.8
ns
ns
ns
ns
PropagationDelay
LE to xQ
—
—
—
8.2
8.7
7.6
2
7.6
7.7
7
OutputEnableTime
OE to xQ
1.5
1.5
OutputDisableTime
OE to xQ
Pulse Duration LE HIGH
Set-upTime,databeforeLE↓
HoldTime,dataafterLE↓
OutputSkew(2)
3.3
2
—
—
3.3
2
—
—
—
1
ns
ns
ns
ns
tSU
tH
1.5
—
—
1.5
—
tSK(o)
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC373A
INDUSTRIALTEMPERATURERANGE
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
tPLH
tPHL
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
LVC Link
30
Propagation Delay
VLOAD
Open
GND
VCC
DISABLE
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
D.U.T.
VLOAD/2
VLOAD/2
Generator
OUTPUT
NORMALLY
LOW
SWITCH
VLOAD
VT
VOL+VLZ
VOL
500Ω
RT
tPHZ
tPZH
CL
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
GND
VT
LVC Link
0V
0V
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
DATA
INPUT
SWITCHPOSITION
VT
0V
Test
Switch
VLOAD
GND
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
tREM
ASYNCHRONOUS
CONTROL
Disable High
Enable High
SYNCHRONOUS
CONTROL
All Other Tests
Open
tSU
tH
VIH
LVC Link
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
OUTPUT 1
VT
PULSE
tSK (x)
tSK (x)
VOH
tW
VT
VOL
HIGH-LOW-HIGH
PULSE
OUTPUT 2
VT
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
LVC
X
XXXX
XX
Temp. Range
Bus-Hold Device Type Package
SO
PY
Q
Small Outline IC (gull wing)
Shrink Small Outline Package
Quarter Size Small Outline Package
Thin Shrink Small Outline Package
PG
373A
Octal Transparent D-Type Latch with 3-State Outputs, ±24mA
Blank
74
No Bus-hold
–40°C to +85°C
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www.idt.com
6
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