IDT74LVCH162245APA8 [IDT]

Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48;


型号：	IDT74LVCH162245APA8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48 光电二极管
文件：	总7页 (文件大小：97K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

IDT74LVCH162245A

3.3V CMOS 16-BIT

BUS TRANSCEIVER

WITH 5 VOLT TOLERANT I/O

AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 16-bit bus transceiver is built using advanced dual metal CMOS

technology. This high-speed,lowpowertransceiveris idealforasynchro-

nous communication between two busses (A and B). The Direction and

OutputEnable controls are designedtooperate this device as eithertwo

independent 8-bit transceivers or one 16-bit transceiver. The direction

controlpin(DIR)controls the directionofdata flow. The outputenable pin

(OE)overrides thedirectioncontrolanddisables bothports. Allinputs are

designedwithhysteresis forimprovednoise margin.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in SSOP, TSSOP, and TVSOP packages

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVCH162245A (B port) has been designed with a ±24mA output

driver. This driver is capable of driving a moderate to heavy load while

maintainingspeedperformance.

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA (A port)

• High Output Drivers: ±24mA (B port)

The LVCH162245 (A port) has series resistors in the device output

structurewhichwillsignificantlyreducelinenoisewhenusedwithlightloads.

The driverhas beendesignedtodrive ±12mAatthe designatedthreshold

levels.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVCH162245A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

1DIR

2DIR

1OE

1B1

2OE

1A1

2A1

2B1

1A2

2A2

1B2

1B3

2B2

1A3

2A3

2B3

1A4

2A4

1B4

1B5

1B6

2B4

1A5

2A5

2B5

1A6

2A6

2B6

1A7

2A7

1B7

1B8

2B7

1A8

2A8

2B8

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2006

DSC-4597/4

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

1DIR

1B1

1OE

1A1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1B2

1A2

GND

1A3

1A4

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1B3

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1B4

VCC

1B5

VCC

1A5

1B6

GND

1B7

1A6

GND

1A7

1A8

2A1

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

Symbol

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

1B8

COUT

CI/O

6.5

2B1

6.5

NOTE:

2B2

GND

2B3

2A2

GND

2A3

1. As applicable to the device type.

PINDESCRIPTION

Pin Names

Description

2B4

2A4

xOE

xDIR

xAx

xBx

Output Enable Input (Active LOW)

Direction Control Output

Side A Inputs or 3-State Outputs⁽¹⁾

Side B Inputs or 3-State Outputs⁽¹⁾

VCC

2B5

2A5

2B6

2A6

NOTE:

GND

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2B7

2B8

2A7

2A8

2OE

(1)

FUNCTION TABLE (EACH 8-BIT SECTION)

2DIR

Inputs

xOE

xDIR

Outputs

B Data to A Bus

SSOP/ TSSOP/ TVSOP

TOP VIEW

A Data to B Bus

High Z State

NOTE:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS(APORT)

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

1.9

1.7

2.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

—

IOL = 6mA

—

VCC = 2.7V

VCC = 3V

IOL = 4mA

—

IOL = 8mA

—

IOL = 6mA

—

IOL = 12mA

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OUTPUTDRIVECHARACTERISTICS(BPORT)

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS(APORT)⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Unit

tPLH

tPHL

PropagationDelay

xBx to xAx

1.5

5.7

7.9

8.3

—

1.5

4.8

tPZH

tPZL

OutputEnableTime

xOE to xAx

1.5

—

1.5

2.2

—

6.3

7.4

500

tPHZ

tPLZ

OutputDisableTime

xOE to xAx

(2)

tSK(o)

OutputSkew

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

SWITCHINGCHARACTERISTICS(BPORT)⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Unit

tPLH

tPHL

PropagationDelay

xAx to xBx

1.5

4.7

6.7

7.1

—

tPZH

tPZL

OutputEnableTime

xOE to xBx

1.5

—

1.5

—

5.5

6.6

500

tPHZ

tPLZ

OutputDisableTime

xOE to xBx

(2)

tSK(o)

OutputSkew

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

(1, 2)

Pulse

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

Open

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

VIH

ASYNCHRONOUS

CONTROL

Disable High

Enable High

VIH

SYNCHRONOUS

CONTROL

All Other Tests

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH162245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

LVC

IDT

XXXX

Device Type Package

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

SSOP - Green

Thin Shrink Small Outline Package

TSSOP - Green

Thin Very Small Outline Package

TVSOP - Green

PVG

PAG

PFG

16-Bit Bus Transceiver

245A

162

Double-Density with Resistors, 24mA (B Port)

12mA (A Port)

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

IDT74LVCH162245APA8 [IDT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB