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IDT74LVCH16245APF

更新时间：2024-09-18 02:28:02

品牌：IDT

描述：3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD

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IDT74LVCH16245APF 概述

3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD 具有三态输出， 5V兼容I / O和总线保持3.3V CMOS 16位总线收发器

IDT74LVCH16245APF 数据手册

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IDT74LVCH16245A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

3.3V CMOS 16-BIT

IDT74LVCH16245A

BUS TRANSCEIVER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 16-bit bus transceiver is built using advanced dual metal CMOS

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

technology. This high-speed, low power transceiver is ideal for asynchro-

nous communication between two busses (A and B). The Direction and

Output Enable controls are designed to operate this device as either two

independent 8-bit transceivers or one 16-bit transceiver. The direction

control pin (DIR) controls the direction of data flow. The output enable pin

(OE) overrides the direction control and disables both ports. All inputs are

designed with hysteresis for improved noise margin.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in SSOP, TSSOP, and TVSOP packages

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

TheLVCH16245Ahasbeendesignedwitha±24mAoutputdriver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

The LVCH16245A has “bus-hold” which retains the inputs' last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

and eliminates the need for pull-up/down resistors.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

1DIR

2DIR

1OE

1B1

2OE

1A1

2A1

2B1

1A2

2A2

1B2

1B3

2B2

1A3

2A3

2B3

1A4

2A4

1B4

1B5

1B6

2B4

1A5

2A5

2B5

1A6

2A6

2B6

1A7

2A7

1B7

1B8

2B7

1A8

2A8

2B8

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 1999

DSC-4596/1

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

1DIR

1B1

1OE

1A1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1B2

1A2

GND

1A3

1A4

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1B3

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1B4

V^CC

1B5

V^CC

1A5

1B6

GND

1B7

1A6

GND

1A7

1A8

2A1

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

1B8

COUT

CI/O

6.5

2B1

NOTE:

2B2

GND

2B3

2A2

GND

2A3

1. As applicable to the device type.

PINDESCRIPTION

Pin Names

2B4

2A4

Description

VCC

xOE

xDIR

xAx

xBx

Output Enable Inputs (Active LOW)

Direction Control Input

2B5

2A5

Side A Inputs or 3-State Outputs⁽¹⁾

Side B Inputs or 3-State Outputs⁽¹⁾

2B6

2A6

GND

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2B7

2B8

2A7

2A8

2OE

2DIR

(1)

FUNCTION TABLE (EACH 8-BIT SECTION)

Inputs

SSOP/ TSSOP/ TVSOP

TOP VIEW

xOE

xDIR

Outputs

Bus B Data to Bus A

Bus A Data to Bus B

Isolation

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

IDT74LVCH16245A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Unit

PropagationDelay

xAx to xBx, xBx to xAx

OutputEnableTime

xOE to xAx or xBx

OutputDisableTime

xOE to xAx or xBx

OutputSkew⁽²⁾

—

4.7

tPHL

tPZH

—

6.7

7.1

—

1.5

—

5.5

6.6

tPZL

tPHZ

tPLZ

tSK(o)

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16245A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

LVC

IDT

XXXX

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Bus Transceiver with 3-State Outputs

245A

Double-Density, ±24mA

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

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