IDT74LVCH16541APF8 [IDT]

Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48;


型号：	IDT74LVCH16541APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48 光电二极管电视
文件：	总6页 (文件大小：66K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 16-BIT BUFFER/

IDT74LVCH16541A

DRIVER WITH 3-STATE

OUTPUTS, 5 VOLT TOLERANT

I/O AND BUS-HOLD

DESCRIPTION

FEATURES:

This 16-bit buffer/driver is built using advanced dual metal CMOS

technology. This high-speed, low power device is a noninverting 16-bit

buffercomposedoftwo8-bitsectionswithseparateoutput-enablesignals.

Foreither8-bitbuffersection,thetwooutput-enable(1OE1and1OE2or2OE1

and2OE2) inputs must be low for the corresponding Y outputs to be active.

Ifeitheroutput-enableinputishigh,theoutputsofthat8-bitbuffersectionare

inthehigh-impedancestate.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V

devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed

3.3V/5V supply system.

• Available in SSOP, TSSOP, and TVSOP packages

The LVCH16541A has been designed with a ±24mA output driver. The

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

The LVCH16541A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

and eliminates the need for pull-up/down resistors.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

¹OE1

²OE1

¹OE2

²OE2

¹Y1

²Y1

¹A1

²A1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 1999

DSC-4731/2

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

1OE2

1OE1

1Y1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1A1

¹A2

¹Y2

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1A3

NOTE:

1Y3

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

¹Y4

¹A4

VCC

¹A5

¹Y5

¹Y6

1A6

GND

¹A7

GND

1Y7

¹Y8

²Y1

²Y2

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

Symbol

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

¹A8

COUT

CI/O

6.5

²A1

6.5

NOTE:

²A2

1. As applicable to the device type.

GND

2A3

2Y3

²Y4

²A4

PINDESCRIPTION

Pin Names

V^CC

VCC

²A5

Description

xOEx

3-StateOutputEnableInputs(ActiveLOW)

DataInputs⁽¹⁾

²Y5

²Y6

xAx

²A6

xYx

3-StateOutputs

GND

2A7

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2Y7

²Y8

²A8

(1)

FUNCTION TABLE (EACH 8-BIT SECTION)

²OE1

²OE2

Inputs

Outputs

xOE1

xOE2

xAx

xYx

SSOP/ TSSOP/ TVSOP

TOP VIEW

NOTE:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

IOFF

VIK

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

VCC = 2.3V

VCC = 2.7V

VCC = 3V

1.7

2.2

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

IOL = 24mA

VCC = 2.7V

VCC = 3V

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperBuffer/DriverOutputsenabled

PowerDissipationCapacitanceperBuffer/DriverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Min.

Max.

Unit

PropagationDelay

xAx to xYx

—

1.1

4.2

tPHL

tPZH

OutputEnableTime

xOEx to xYx

—

6.9

7.4

—

1.5

1.9

—

5.6

6.8

500

tPZL

tPHZ

OutputDisableTime

tPLZ

xOEx to xYx

OutputSkew⁽²⁾

tSK(o)

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

OPPOSITE PHASE

INPUT TRANSITION

Vcc / 2

150

VLZ

VHZ

LVC Link

150

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

OUTPUT

NORMALLY

LOW

(1, 2)

Pulse

SWITCH

CLOSED

D.U.T.

V^LZ

VOL

Generator

tPHZ

tPZH

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

Enable and Disable Times

NOTE:

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

VIH

DATA

INPUT

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

tSU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

tREM

VIH

Open Drain

Disable Low

Enable Low

ASYNCHRONOUS

CONTROL

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

LVC Link

All Other Tests

Open

Set-up, Hold, and Release Times

VIH

LOW-HIGH-LOW

INPUT

tPLH1

t^PHL1

PULSE

V^OH

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

VOL

LVC Link

Pulse Width

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16541A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

XXXX

LVC

IDT

Device Type Package

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Buffer/Driver with 3 State Outputs

and 5 Volt Tolerant I/O

541A

Double-Density, ±24mA

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

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Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT74LVCH16541APF8 [IDT]

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