IDT74LVCH16646APA [IDT]
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS 5 VOLT TOLERANT I/O AND BUS-HOLD; 3.3V CMOS 16位总线收发器/寄存器,三态输出的5V耐压I / O和总线保持型号: | IDT74LVCH16646APA |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS 5 VOLT TOLERANT I/O AND BUS-HOLD |
文件: | 总8页 (文件大小:115K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74LVCH16646A
3.3V CMOS 16-BIT BUS
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
The LVCH16646A 16-bit bus transceiver and register is built using
advanced dual metal CMOS technology. This high-speed, low power
device is organized as two independent 8-bit D-type transceivers with 3-
state D-type registers.The controls circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly or from the
internalstorageregisters.Each8-bittransceiver/registerfeaturesdirection
control(DIR),over-ridingOutputEnablecontrol(OE)andSelectlines(SAB
andSBA)toselecteitherreal-timedataorstoreddata.Separateclockinputs
areprovidedforAandBportregisters. DataontheAorBdatabus, orboth,
can be stored in the internal registers by the low-to-high transitions at the
appropriateclockpins. Flow-throughorganizationofsignalpinssimplifies
layout. All inputs are designed with hysteresis for improved noise margin.
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
TheLVCH16646Ahasbeendesignedwitha ±24mAoutputdriver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVCH16646A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
FUNCTIONALBLOCKDIAGRAM
29
56
2OE
1OE
1
28
1DIR
2DIR
55
30
2CLKBA
1CLKBA
54
31
27
2SBA
1SBA
2
2CLKAB
1CLKAB
3
26
2SAB
1SAB
1D
C1
1D
One of Eight Channels
C1
One of Eight Channels
1A1 5
15
42
52
2A1
1B1
2B1
1D
C1
1D
C1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-3787/1
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1
2
56
55
54
53
52
1OE
1DIR
IOUT
DC Output Current
1CLKBA
1CLKAB
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
1SBA
GND
1B1
1SAB
GND
1A1
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
4
5
6
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1B2
VCC
1A2
51
50
49
48
VCC
7
8
1B3
1B4
1A3
1A4
9
10
47
46
45
44
1B5
1A5
GND
1A6
CAPACITANCE (TA = +25°C, F = 1.0MHz)
11
12
13
14
15
16
17
18
GND
1B6
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
1A7
1B7
1B8
2B1
6.5
43
42
1A8
2A1
NOTE:
1. As applicable to the device type.
41
2B2
2A2
40
39
38
2B3
2A3
GND
GND
2B4
2B5
19
20
21
22
23
2A4
2A5
PINDESCRIPTION
37
36
35
34
33
32
31
30
29
Pin Names
Description
2B6
VCC
2B7
2A6
VCC
2A7
xAx
Data Register A Inputs(1)
Data Register B Outputs
DataRegisterBInputs(1)
DataRegisterAOutputs
Clock Pulse Inputs
xBx
24
2B8
2A8
xCLKAB, xCLKBA
xSAB, xSBA
xOE
GND
GND
OutputDataSourceSelectInputs
OutputEnableInputs
25
26
27
2SBA
2SAB
xDIR
DirectionControlInputs
2CLKBA
2CLKAB
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
28
2OE
2DIR
SSOP/ TSSOP/ TVSOP
TOP VIEW
2
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
Inputs
Data I/O(2)
xOE
X
xDIR
X
xCLKAB
xCLKBA
xSAB
xSBA
xAx
Input
xBx
Operation or Function
Store A, B unspecified(2)
Store B, A unspecified(2)
Store A and B data
↑
X
X
X
X
X
X
X
X
L
X
X
X
X
L
Unspecified
Input
X
X
↑
↑
Unspecified
Input
H
H
L
X
↑
H or L
X
Input
X
H or L
Input
Input
Isolation,holdstorage
L
X
Output
Output
Input
Input
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
L
L
X
H or L
X
H
X
X
Input
L
H
X
Output
Output
L
H
H or L
X
H
Input
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
↑ = LOW-to-HIGH transition
2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will
be stored on every LOW-to-HIGH transition of the clock inputs.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
3
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
BUS
A
BUS
B
BUS
A
BUS
B
xCLKBA xSAB
xDIR xOE xCLKAB
xSBA
L
xCLKBA xSAB
xDIR xOE xCLKAB
xSBA
X
X
X
L
L
X
X
L
H
L
X
Real-Time Transfer
Bus A to B
Real-Time Transfer
Bus B to A
BUS
A
BUS
A
BUS
B
BUS
B
xCLKBA xSAB
xOE xCLKAB
xSBA
xCLKBA xSAB
xDIR
X
X
xDIR xOE xCLKAB
xSBA
H
X
X
↑
↑
X
X
X
X
X
X
X
X
H or L
X
X
H
↑
X
L
H
L
L
X
H or L
H
X
↑
Storage from
A, B, or A and B
Transfer Stored
Data to A and/or B
4
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
—
—
—
µA
µA
IBHL
VI = 0.7V
—
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
2
1.7
2.2
2.4
2
—
VCC = 2.3V
—
VCC = 2.7V
—
VCC = 3V
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
60
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
12
5
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
Parameter
Min.
150
—
Min.
150
1.3
Max.
—
Unit
MHz
ns
—
PropagationDelay
6.8
5.7
xAx to xBx or xBx to xAx
PropagationDelay
—
—
—
—
—
—
3.2
0
7.9
9.2
8.5
8.5
7.7
7.8
—
1.8
1.7
1.3
1.4
2.1
2
6.7
7.7
6.9
7.2
6.9
7
ns
ns
ns
ns
ns
ns
ns
ns
xCLKBA or xCLKAB to xAx or xBx
PropagationDelay
xSBA or xSAB to xAx or xBx
OutputEnableTime
xOE to xAx or Bx
OutputEnableTime
xDIR to xAx or Bx
OutputDisableTime
xOE to xAx or Bx
OutputDisableTime
xDIR to xAx or Bx
Set-upTime
2.9
0.3
—
xAx or xBx before CLKAB↑ or CLKBA↑
HoldTime
tH
—
—
xAx or xBx after CLKAB↑ or CLKBA↑
Pulse Duration, CLK HIGH or LOW
OutputSkew(2)
tW
3.3
—
3.3
—
ns
ps
tSK(o)
—
—
—
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
6
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
LVC Link
150
Propagation Delay
30
DISABLE
ENABLE
VLOAD
Open
GND
VIH
VT
VCC
CONTROL
INPUT
0V
tPZL
tPLZ
500Ω
VIN
VLOAD/2
VT
VOUT
VLOAD/2
OUTPUT
NORMALLY
LOW
(1, 2)
Pulse
SWITCH
CLOSED
D.U.T.
VLZ
VOL
Generator
tPHZ
tPZH
500Ω
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
CL
VT
0V
0V
LVC Link
LVC Link
Test Circuit for All Outputs
Enable and Disable Times
NOTE:
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
DATA
INPUT
VT
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
tREM
VIH
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
LVC Link
All Other Tests
Open
Set-up, Hold, and Release Times
VIH
VT
LOW-HIGH-LOW
INPUT
0V
tPLH1
tPHL1
VT
PULSE
VOH
VT
tW
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
HIGH-LOW-HIGH
PULSE
tSK (x)
VT
VOH
VT
VOL
LVC Link
Pulse Width
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
7
IDT74LVCH16646A
3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XX
XX
IDT
XXXX
XX
LVC
Device Type Package
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Bus Transceiver/Register with
3-State Outputs and 5 Volt Tolerant I/O
646A
16
Double-Density, ±24mA
H
Bus-hold
74
-40°C to +85°C
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8
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