IDT74LVCH16701APA8 [IDT]
FIFO, 4X18, 6ns, Synchronous, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74LVCH16701APA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4X18, 6ns, Synchronous, CMOS, PDSO56, TSSOP-56 先进先出芯片 光电二极管 |
| 文件： | 总8页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS
IDT74LVCH16701A
18-BIT READ/WRITE BUFFER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
DESCRIPTION:
FEATURES:
The LVCH16701A 18-bit read/write buffer is built using advanced dual
metal CMOS technology. The device is designed as an 18-bit read/write
bufferwithafourdeepFIFOandaread-backlatch.Itcanbeusedasaread/
writebufferbetweenaCPUandamemoryortointerfaceahigh-speedbus
and a slow peripheral. The A-to-B (write) path has a four deep FIFO for
pipelined operations. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (FF). The B-to-A (read) path has a latch.
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
TheLVCH16701Ahasbeendesignedwitha±24mAoutputdriver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
The LVCH16701A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
A1-18
3
18
27
OEBA
29
RESET
55
CLK
Q
2
FIFO
(4 deep)
28
WCE
LATCH
LE
LE
56
RCE
D
30
FF
1
OEAB
18
54
B1-18
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4233/3
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1
2
56
55
54
53
52
OEAB
WCE
A1
RCE
CLK
B1
IOUT
DC Output Current
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
4
5
6
GND
A2
GND
B2
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
B3
51
50
49
48
A3
7
VCC
VCC
B4
8
A4
A5
9
B5
10
47
46
45
44
B6
A6
GND
A7
CAPACITANCE (TA = +25°C, F = 1.0MHz)
11
12
13
14
15
16
17
18
GND
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
B7
B8
COUT
CI/O
6.5
A8
6.5
A9
NOTE:
B9
43
42
1. As applicable to the device type.
A10
A11
B10
41
B11
B12
40
39
38
A12
GND
A13
GND
B13
19
20
21
22
23
37
36
35
34
B14
A14
A15
B15
VCC
A16
A17
VCC
B16
24
25
26
27
33
32
B17
GND
B18
GND
A18
31
30
29
OEBA
LE
FF
28
RESET
SSOP/ TSSOP/ TVSOP
TOP VIEW
2
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Pin Names I/O
Description
A1-18
B1-18
CLK
I/O
I/O
I
18 bit I/O port (1)
18 bit I/O port (1)
Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further
writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low.
WCE
RCE
I
I
Enable pin for FIFO input clock (Active LOW)
Enable pin for FIFO output clock (Active LOW)
Write path FIFO full flag. Goes low when FIFO is full.
FF
O
I
RESET
Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the “empty” condition and FIFO output is forced
high (all ones). The FIFO full flag (FF) will be high immediately after reset. (Active LOW)
OEAB
OEBA
LE
I
I
I
Output Enable pin for B port (Active LOW)
Output Enable pin for A port (Active LOW)
Readpathlatchenablepin. Whenhigh,dataflowstransparentlyfromBporttoAport,BdataislatchedonthefallingedgeofLE.(Note:LEisindependent
of CLK and data)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTIONTABLE(1)
Inputs
Outputs
OEBA
OEAB
LE
H
H
L
RESET
CLK
↑
Ax
Bx
Notes
H
L
H
H
H
H
L
H
H
H
H
H
H
Q(2)(B) Bus Hold
Q(2)(A) -4CLKS Bus Hold
↑
B to A
TransparentMode
L
↑
Qo(B)
H
H
L
X
X
L
↑
Q(2)(A) Bus Hold
Q(2)(B) Bus Hold
A to B - 4 CLKS
↑
L
↑
Q(2)(B) Bus Hold
Q(2)(B) - 4 CLKS Bus Hold
Casenotrecommended
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2. Level of Q before the indicated steady-state input conditions were established.
FUNCTIONAL DESCRIPTION
Thisdeviceisusefulasaread/writebufferformodularhighenddesigns. remains at the output of the FIFO. The FIFO may be reset by the
It provides multi-level buffering in the write path and single deep buffering synchronous RESET input. This resets the read and write pointers to the
inthereadpath,andissuitedtowritebackcacheimplementation. Theread original“empty”conditionandalsosetsallBoutputs=1. Simultaneousread
path provides a transparent latch.
and write attempts (clock data into FIFO as well as clock data out of FIFO)
are possible except on FIFO empty and full boundaries. When the FIFO
isempty,andasimultaneousreadandwriteisattempted,thereadisignored
while the write is executed. If the same is attempted when the FIFO is full,
thewriteisignoredwhilethereadisexecuted. Normaloperationofthefour
deep FIFO in the write path is independent of the read path operation.
ThefourdeepFIFOusesoneclockwithtwoclockenablepins,WCEand
RCEtoclockdatainandout. TheFIFOhasanexternalfullflagwhichgoes
LOW when the FIFO is full. Internal read and write pointers keep track of
the words stored in the FIFO. A write attempt to a full FIFO is ignored. An
attempttoreadfromanemptyFIFOwillhavenoeffectandthelastreaddata
3
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
TIMINGDIAGRAM
READ CYCLES
WRITE CYCLES
Cycle 4
Cycle 4
Cycle 3
Cycle 2
Cycle 3
Cycle 2
Cycle 1
Cycle 1
CLK
RESET
WCE
OEAB
A [1:18]
WORD 3
WORD 1
WORD 2
WORD 4
FF
B [1:18]
WORD 3
WORD 1
WORD 2
WORD 4
RCE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
4
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
—
—
—
µA
µA
IBHL
VI = 0.7V
—
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
2
1.7
2.2
2.4
2
—
VCC = 2.3V
—
VCC = 2.7V
—
VCC = 3V
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
Power Dissipation WCE Mode, OEAB = 0
Power Dissipation RCE Mode, OEBA = 0
RegisteredChannel(BtoA)
CL = 0pF, f = 10Mhz
pF
CPD
CPD
Power Dissipation OEBA = 0; CE = 0
RegisteredChannel
CPD
Power Dissipation OEBA = 0; CE = 1
5
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Min.
Min.
Max.
Unit
PROPAGATION DELAYS
1
2
3
4
5
B1-18 toA1-18
Readpath/latch
Readpath/latch
Writepath
2
2
4.5
4.8
6
ns
ns
ns
ns
ns
LE (LOW to HIGH) to A1-18
CLK to FF
1.5
1.5
—
CLK to B1-18
OutputSkew(2)
Writepath
6
Writepath
1
SETUP & HOLD TIMES
6
7
A1-18 to CLK (LOW to HIGH) Setup
Writepath
1.5
0.9
1.2
1
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
A1-18 to CLK (LOW to HIGH) Hold
B1-18 to LE (HIGH to LOW) Setup
B1-18 to LE (HIGH to LOW) Hold
WCE, RCE (LOW) to CLK Setup
WCE, RCE (LOW) to CLK Hold
RESET (LOW) to CLK Setup
RESET (LOW) to CLK Hold
Writepath
8
Readpath/latch
Readpath/latch
Writepath
9
10
11
12
13
3.5
0
Writepath
Writepath
1.8
0.6
Writepath
ENABLE & DISABLE TIMES
14
15
16
17
OEBA LOW to A1-18 Enable
Writepath
Writepath
Readpath
Readpath
1.5
1.5
1.5
1.5
6
5.7
6
ns
ns
ns
ns
OEBA HIGH to A1-18 Disable
OEBA LOW to B1-18 Enable
OEBA HIGH to B1-18 Disable
5.7
MINIMUM PULSE WIDTHS
18
19
CLK HIGH or LOW Pulse Width
Writepath
5
5
—
—
ns
ns
LE HIGH Pulse Width
Readpath/latch
19
20
Clock Frequency
Clock Cycle Time
83
MHz
ns
12
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
6
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
LVC Link
150
Propagation Delay
30
DISABLE
ENABLE
VLOAD
Open
GND
VIH
VT
VCC
CONTROL
INPUT
0V
tPZL
tPLZ
500Ω
VIN
VLOAD/2
VT
VOUT
VLOAD/2
OUTPUT
NORMALLY
LOW
(1, 2)
Pulse
SWITCH
CLOSED
D.U.T.
VLZ
VOL
Generator
tPHZ
tPZH
500Ω
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
CL
VT
0V
0V
LVC Link
LVC Link
Test Circuit for All Outputs
Enable and Disable Times
NOTE:
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
DATA
INPUT
VT
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
tREM
VIH
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
LVC Link
All Other Tests
Open
Set-up, Hold, and Release Times
VIH
VT
LOW-HIGH-LOW
INPUT
0V
tPLH1
tPHL1
VT
PULSE
VOH
VT
tW
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
HIGH-LOW-HIGH
PULSE
tSK (x)
VT
VOH
VT
VOL
LVC Link
Pulse Width
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
7
IDT74LVCH16701A
3.3VCMOS18-BITREAD/WRITEBUFFERWITH5VTOLERANTI/O
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
X
XX
XXXX
LVC
IDT
XX
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
18-Bit Read/Write Buffer
701A
16
Double-Density, ±24mA
Bus-hold
H
-40°C to +85°C
74
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8
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