IDT74LVCH16952APF8 [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56;
| 型号： | IDT74LVCH16952APF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 光电二极管 电视 |
| 文件： | 总6页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
IDT74LVCH16952A
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
This 16-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power device is organized as two
independent 8-bit D-type registered transceivers with separate input and
output control for independent control of data flow in either direction. For
example, the A-to-B Enable (CEAB) must be LOW to enter data from the A
port.CLKABcontrolstheclockingfunction.WhenCLKABtogglesfromLOW-
to-HIGH,thedatapresentontheAportwillbeclockedintotheregister. OEAB
performs the output enable function on the B port. Data flow from the B port
toAportissimilarbutrequiresusingCEBA, CLKBA, andOEBAinputs. Full
16-bit operation is achieved by tying the control pins of the independent
transceiverstogether.
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16952A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
54
31
1CEBA
2CEBA
55
30
1CLKBA
2CLKBA
28
1
1OEAB
2OEAB
3
26
1CEAB
2CEAB
27
2
1CLKAB
2CLKAB
29
56
1OEBA
2OEBA
C1
CE
1D
C1
CE
1D
52
42
15
5
1B1
2B1
1A1
2A1
C1
CE
C1
CE
1D
1D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4073/1
IDT74LVCH16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
1
2
56
55
54
53
52
OEAB
°C
mA
mA
1
OEBA
1
IOUT
DC Output Current
CLKAB
CLKBA
1
1
1
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
CEAB
GND
1A1
1
CEBA
4
5
6
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
GND
1B1
NOTE:
51
50
49
48
1A2
VCC
1B2
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7
VCC
1B3
8
1A3
9
A
1
4
B
1
4
10
47
46
45
44
1A5
1B5
GND
1B6
1B7
1B8
11
12
13
14
15
16
17
18
PINDESCRIPTION
GND
1A6
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
Description
A-to-B Output Enable Inputs (Active LOW)
B-to-A Output Enable Inputs (Active LOW)
A-to-B Clock Enable Inputs (Active LOW)
B-to-A Clock Enable Inputs (Active LOW)
A-to-B Clock Inputs
1A7
1A8
43
42
A
2
1
2B1
2B2
41
2A2
2A3
B-to-A Clock Inputs
40
39
38
2B3
GND
2B4
2B5
2B6
A-to-BDataInputsorB-to-A3-StateOutputs(1)
B-to-ADataInputsorA-to-B3-StateOutputs(1)
GND
2A4
2A5
2A6
VCC
xBx
19
20
21
22
23
NOTE:
37
36
35
34
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
VCC
2B7
2A7
FUNCTIONTABLE(1,2)
24
25
26
27
33
32
2A8
2B8
Inputs
Outputs
GND
GND
xCEAB
xCLKAB
xOEAB
xAx
X
xBx
B(3)
B(3)
L
CEAB
31
30
29
2
CEBA
2
H
X
L
X
L
L
L
CLKAB
2OEAB
2
CLKBA
2
X
28
OEBA
2
↑
↑
X
L
L
L
L
H
H
SSOP/ TSSOP/ TVSOP
TOP VIEW
X
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
CAPACITANCE (TA = +25°C, F = 1.0MHz)
and xOEBA.
2. H = HIGH Voltage Level
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
6.5
3. Output level of B before the indicated steady-state input conditions were established.
NOTE:
1. As applicable to the device type.
2
IDT74LVCH16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
—
—
—
µA
µA
IBHL
VI = 0.7V
—
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
87
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
43
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
Parameter
Min.
150
—
Max.
—
Min.
150
1.6
Max.
—
Unit
MHz
ns
tPLH
PropagationDelay
7.6
6.6
tPHL
xCLKAB, xCLKBA to xBx, xAx
tPZH
tPZL
tPHZ
tPLZ
OutputEnableTime
—
—
8
1.1
1.9
6.6
6.7
ns
ns
xOEBA, xOEAB to xAx, xBx
OutputDisableTime
7.1
xOEBA, xOEAB to xAx, xBx
tSU
tH
Set-up Time, data before xCLKAB↑, xCLKBA↑
Hold Time, data after xCLKAB↑, xCLKBA↑
Set-up Time, xCEAB, xCEBA before xCLKAB↑, xCLKBA↑
Hold Time, xCEAB, xCEBA after xCLKAB↑, xCLKBA↑
Pulse Duration HIGH or LOW, xCLKAB or xCLKBA
OutputSkew(2)
3.4
0.5
1.8
1.1
3.3
—
—
—
—
—
—
—
2.8
0.5
1.4
1.9
3.3
—
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
tSU
tH
tW
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
LVC Link
150
Propagation Delay
30
DISABLE
ENABLE
VLOAD
Open
GND
VIH
VT
VCC
CONTROL
INPUT
0V
tPZL
tPLZ
500Ω
VIN
VLOAD/2
VT
VOUT
VLOAD/2
OUTPUT
NORMALLY
LOW
(1, 2)
Pulse
SWITCH
CLOSED
D.U.T.
VLZ
VOL
Generator
tPHZ
tPZH
500Ω
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
CL
VT
0V
0V
LVC Link
LVC Link
Test Circuit for All Outputs
Enable and Disable Times
NOTE:
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
DATA
INPUT
VT
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
tREM
VIH
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
LVC Link
All Other Tests
Open
Set-up, Hold, and Release Times
VIH
VT
LOW-HIGH-LOW
INPUT
0V
tPLH1
tPHL1
VT
PULSE
VOH
VT
tW
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
HIGH-LOW-HIGH
PULSE
tSK (x)
VT
VOH
VT
VOL
LVC Link
Pulse Width
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
X
XX
XXXX
LVC
IDT
XX
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Registered Transceiver
with 3-State Outputs
952A
16
Double-Density, ±24mA
Bus-hold
H
74
-40°C to +85°C
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www.idt.com
6
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