IDT74LVCH2573AQ8 [IDT]

Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, QSOP-20;


型号：	IDT74LVCH2573AQ8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, QSOP-20 光电二极管
文件：	总6页 (文件大小：62K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH2573A

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

3.3V CMOS OCTAL

TRANSPARENT D-TYPE LATCH

IDT74LVCH2573A

WITH 3-STATE OUTPUTS, 5 VOLT

TOLERANT I/O AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

The LVCH2573A octal transparent D-type latch is built using advanced

dualmetalCMOStechnology.Thedevicefeatures3-stateoutputsdesigned

specificallyfordrivinghighlycapacitiveorrelativelylow-impedanceloads,

andisparticularlysuitableforimplementingbufferregisters,input-output(I/

O) ports, bidirectional bus drivers, and working registers.

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• Rail-to-rail output swing for increased noise margin

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

Whilethelatch-enable(LE)inputishigh,theQoutputsfollowthedata(D)

inputs. When LE is taken low, the Q outputs are latched at the logic levels

at the D inputs.

Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs

in either a normal logic state (high or low logic levels) or a high-impedance

state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus

lines significantly. The high-impedance state and increased drive provide

thecapabilitytodrivebuslineswithoutinterfaceorpullupcomponents. OE

doesnotaffecttheinternaloperationsofthelatch. Olddatacanberetained

ornewdatacanbeenteredwhiletheoutputsareinthehigh-impedancestate.

TheLVCH2573Ahasseriesresistorsinthedeviceoutputstructurewhich

willsignificantlyreducelinenoisewhenusedwithlightloads.Thisdriverhas

been developed to drive ±12mA at the designated thresholds.

Inputs can be driven from either 3.3V or 5V devices. This feature allows

theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.

The LVCH2573A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

and eliminates the need for pull-up/down resistors.

• Available in SOIC, SSOP, QSOP, and TSSOP packages

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

FEBRUARY 2000

DSC-4942/1

IDT74LVCH2573A

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

V^CC

°C

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

GND

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

5.5

SOIC/ SSOP/ QSOP/ TSSOP

TOP VIEW

6.5

NOTE:

1. As applicable to the device type.

PINDESCRIPTION

Pin Names

Description

Output Enable Inputs (Active LOW)

Latch Enable Input

Data Inputs⁽¹⁾

3-State Data Outputs

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

(1)

FUNCTION TABLE (EACH LATCH)

Inputs

Outputs

Q⁽²⁾

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

2. Output level before the indicated steady-state input conditions were established.

IDT74LVCH2573A

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH2573A

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC – 0.2

VCC = 2.3V

VCC = 2.7V

VCC = 3V

1.9

1.7

2.2

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

IOL = 6mA

VCC = 2.7V

VCC = 3V

IOL = 4mA

IOL = 8mA

IOL = 6mA

IOL = 12mA

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

Parameter

Min.

Max.

Unit

PropagationDelay

xD to xQ

1.5

9.5

1.5

PropagationDelay

LE to xQ

1.5

8.5

6.5

OutputEnableTime

OEx to xQ

OutputDisableTime

OEx to xQ

Pulse Duration, LE HIGH

SetupTime,databeforeLE↓

HoldTime,dataafterLE↓

3.3

2.5

1.5

—

3.3

2.5

1.5

—

tSU

tSK(o)

OutputSkew⁽²⁾

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH2573A

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

TESTCIRCUITSANDWAVEFORMS

VIH

SAME PHASE

INPUT TRANSITION

TESTCONDITIONS

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

tPLH

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

tPLH

tPHL

Vcc / 2

150

VIH

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

LVC Link

Propagation Delay

VLOAD

Open

GND

VCC

DISABLE

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

D.U.T.

VLOAD/2

Generator

OUTPUT

NORMALLY

LOW

SWITCH

VLOAD

V^OL+VLZ

VOL

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

GND

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

VIH

LVC Link

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

VOL

LOW-HIGH-LOW

OUTPUT 1

PULSE

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH2573A

3.3VCMOSOCTALTRANSPARENTD-TYPELATCH

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

XXXX

Temp. Range

Bus-Hold Device Type Package

Small Outline IC (gull wing)

Shrink Small Outline Package

Quarter Size Small Outline Package

Thin Shrink Small Outline Package

2573A

Octal Transparent D-Type Latch with 3-State Outputs, ±12mA

Bus-hold

–40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

logichelp@idt.com

(408) 654-6459

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

IDT74LVCH2573AQ8 [IDT]

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