IDT74SSTUBH32865ABKG8 [IDT]
28-BIT 1:2 REGISTERED BUFFER FOR DDR2; 28位1 ： 2寄存缓冲器支持DDR2
| 型号： | IDT74SSTUBH32865ABKG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 |
| 文件： | 总17页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
IDT74SSTUBH32865A
The IDT74SSTUBH32865A includes a parity checking
function. The IDT74SSTUBH32865A accepts a parity bit
from the memory controller at its input pin PARIN,
compares it with the data received on the D-inputs and
indicates whether a parity error has occurred on its
open-drain PTYERR pin (active LOW).
Description
This 28-bit 1:2 registered buffer with parity is designed for
1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load. The IDT74SSTUBH32865A
operates from a differential clock (CLK and CLK). Data are
registered at the crossing of CLK going high, and CLK
going low.
Features
• Double Drive strength for heavily-loaded DIMM
applications
The device supports low-power standby operation. When
the reset input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs except PTYERR are forced low. The LVCMOS
RESET input must always be held at a valid logic high or
low level.
• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs
and outputs
• Supports LVCMOS switching levels on CSGateEN and
RESET inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 160-ball LFBGA package
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
Applications
In the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the IDT74SSTUBH32865A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
• Ideal for DDR2 400, 533, 667, and 800
The device monitors both DCS0 and DCS1 inputs and will
gate the Qn outputs from changing states when both DCS0
and DCS1 are high. If either DCS0 and DCS1 input is low,
the Qn outputs will function normally. The RESET input has
priority over the DCS0 and DCS1 control and will force the
Qn outputs low and the PTYERR output high. If the
DCS-control functionality is not desired, then the
CSGateEnable input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs.
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Block Diagram
(CS ACTIVE)
VREF
D
R
Q
PARIN
PARITY
GENERATOR
AND
PYTERR
Q0A
22
CHECKER
D
R
Q
Q
Q
Q
Q
Q
D0
Q0B
Q21A
D
R
D21
Q21B
QCS0A
DCS0
D
R
QCS0B
QCS1A
CSGateEN
DCS1
D
R
QCS1B
QCKE0A,
QCKE1A
DCKE0,
DCKE1
2
2
D
R
QCKE0B,
QCKE1B
QODT0A,
QODT1A
DODT0,
DODT1
2
2
D
R
QODT0B,
QODT1B
RESET
CLK
CLK
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Pin Configuration
1
2
3
4
5
6
7
8
9
10
11 12
1
VREF
D1
2
3
4
5
6
7
8
9
10
11
12
QCKE1A QCKE0A
NC
D2
PARIN
NC
NC
NC
NC
Q21A
Q21B
Q19A
Q19B
Q18A
Q18B
Q17B
Q17A
A
B
C
D
E
F
A
B
C
D
E
F
QCKE0B
QCKE1B
QODT0B QODT0A
QODT1B QODT1A
NC
D3
D6
D4
D5
VDDL
GND
GND
GND
GND
GND
GND
VDDL
GND
NC
NC
GND
Q20B
Q16B
Q1B
Q20A
Q16A
Q1A
GND
GND
VDDR
VDDR
GND
VDDR
GND
D7
VDDL
VDDR
D8
VDDL
VDDL
VDDL
VDDL
GND
VDDL
GND
GND
VDDL
GND
VDDR
VDDR
D11
D18
D9
D12
Q2B
Q2A
G
H
J
CSGate
EN
Q5B
Q5A
D15
GND
G
H
J
CLK
CLK
RESET
D0
QCS0B
QCS1B
Q6B
QCS0A
QCS1A
Q6A
DCS0
DCS1
D14
VDDR
GND
K
L
VDDR
VDDR
GND
VDDR
M
N
P
R
D10
D16
D21
D20
GND
VDDL
VDDL
VDDL
GND
VDDR
VDDR
GND
Q10B
Q9B
Q10A
Q9A
K
L
D17
D19
VDDL
VDDL
VDDR
GND
Q11B
Q15B
Q11A
Q15A
GND
GND
GND
GND
M
N
P
R
T
D13
DODT1 DODT0
DCKE0 DCKE1
Q14B
Q0B
Q14A
Q8B
T
MCL
MCL
PTYERR MCH
Q3B
Q3A
Q12B
Q12A
Q7B
Q7A
Q4B
Q4A
Q13B
Q13A
U
Q0A
Q8A
VREF
MCL
NC
MCH
V
NOTE:
U
V
1. An empty cell indicates no ball is populated at
that gridpoint. NC denotes a no-connect (ball
present but not connected to the die). MCL denotes
a pin that Must be Connected LOW. MCH denotes
a pin that Must be Connected HIGH.
160-Ball BGA
TOP VIEW
160-Ball BGA
TOP VIEW
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Ball Assignment
Signal Group
Signal Name
Type
Description
DCKE0, DCKE1,
DODT0, DODT1
Ungated Inputs
SSTL_18
DRAM function pins not associated with Chip Select.
Chip Select Gated
Inputs
DRAM inputs, re-driven only when Chip Select is
LOW.
D0 ... D21
SSTL_18
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one
will be low when a valid address/command is present.
The register can be programmed to re-drive all
D-inputs only (CSGateEN high) when at least one
Chip Select input is LOW.
Chip Select Inputs
DCS0, DCS1
Q0A...Q21A,
Q0B...Q21B,
QCSnA,B
QCKEnA,B,
QODTnA,B
Outputs of the register, valid after the specified clock
count outputs and immediately following a rising edge
of the clock.
Re-Driven
SSTL_18
SSTL_18
Input parity is received on pin PARIN and should
maintain odd parity across the D0...D21 inputs, at the
rising edge of the clock.
Parity Input
PARIN
When LOW, this output indicates that a parity error
was output identified associated with the address
and/or command inputs. PTYERR will be active for
two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on
the industry-standard DDR-II register with parity (in
JEDEC definition).
Parity Error
PTYERR
Open Drain
Chip Select Gate Enable. When HIGH, the D0..D21
inputs will be latched only when at least one Chip
Program Inputs
Clock Inputs
CSGateEN
1.8V LVCMOS Select input is LOW during the rising edge of the
clock. When LOW, the D0...D21 inputs will be latched
and redriven on every rising edge of the clock.
Differential master clock input pair to the register. The
CLK, CLK
SSTL_18
register operation is triggered by a rising edge on the
positive clock input (CLK).
MCL, MCH
Must be connected to a logic LOW or HIGH.
Asynchronous reset input. When LOW, it causes a
reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR
signal.
RESET
VREF
1.8V LVCMOS
Miscellaneous
Inputs
Input reference voltage for the SSTL_18 inputs. Two
0.9V nominal pins (internally tied together) are used for increased
reliability.
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Function Table
Inputs1
Outputs
RESET DCS0 DCS1 CSGate CLK
EN
CLK
Dn,
DODTn,
DCKEn
Qn
QCS0x QCS1x QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
X
↑
↓
L
H
X
L
L
L
L
L
L
↑
↓
H
H
L
L
X
L or H
L or H
Q
Q
Q
Q
0
0
0
0
L
H
H
H
L
X
↑
↓
L
L
L
L
H
L
L
X
↑
L or H
↑
↓
L or H
↓
H
X
H
H
H
L
X
Q
Q
Q
Q
0
0
0
0
H
H
H
H
H
H
H
H
H
X or
X
L
L
H
L
L
L
L
X
↑
↓
H
X
H
H
H
L
X
L or H
↑
L or H
↓
Q
Q
Q
Q
0
0
0
0
H
H
H
H
H
H
X or
L
L
L
H
H
H
L
L
↑
↓
H
X
H
H
H
L
L or H
↑
L or H
↓
Q
Q
Q
Q
0
0
0
0
0
0
0
H
H
H
X or
L
Q
Q
Q
H
H
H
H
L
↑
↓
H
X
H
L or H
L or H
Q
Q
Q
0
0
0
X or
X or
X or
L
L
L
L
Floating Floating Floating Floating Floating Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
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COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
Inputs1
Outputs
RESET DCS0 DCS1
CLK
CLK
Σ of Inputs = H (D1 - D21)
PARIN2
PTYERR3
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
↑
↓
Even
Odd
L
H
L
↑
↓
L
L
X
↑
↓
Even
Odd
H
L
L
X
↑
↓
H
H
H
L
X
L
↑
↑
↓
↓
Even
Odd
L
X
L
L
X
L
↑
↓
Even
Odd
H
L
X
L
↑
↓
H
H
H
H
X
↑
↓
X
X
X
PTYERR
PTYERR
H
0
0
X
L or H
L or H
X
X or
X or
X or
X or
X or Floating
X or Floating
Floating Floating Floating Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
PARIN arrives one clock cycle after the data to which it applies.
This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
2
3
PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
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Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Item
Rating
Supply Voltage, VDD
-0.5V to 2.5V
1
Input Voltage Range, VI
-0.5V to VDD + 2.5V
-0.5V to VDDQ + 0.5V
50mA
1,2
Output Voltage Range, VO
Input Clamp Current, IIK
Output Clamp Current, IOK
50mA
Continuous Output Clamp Current, IO
50mA
Continuous Current through each VDD or GND
100mA
0m/s Airflow
1m/s Airflow
44.3°C/W
3
Package Thermal Impedance (θja)
38.1°C/W
Storage Temperature
-65 to +150°C
1
The input and output negative voltage ratings may be exceeded if the ratings of the I/P and
O/P clamp current are observed.
2
3
This current will flow only when the output is in the high state level VO > VDDQ.
The package thermal impedance is calculated in accordance with JESD 51.
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Operating Characteristics
The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device
operation. The differential inputs must not be floating unless RESET is LOW.
Symbol
VDD
VREF
VTT
VI
Parameter
Min.
1.7
Typ.
1.8
Max.
1.9
Units
I/O Supply Voltage
V
V
V
V
Reference Voltage
0.49 * VDD
VREF - 0.04
0
0.5 * VDD
VREF
0.51 * VDD
VREF + 0.04
VDD
Termination Voltage
Input Voltage
VIH
AC High-Level Input Voltage
AC Low-Level Input Voltage
DC High-Level Input Voltage
DC Low-Level Input Voltage
High-Level Input Voltage
Low-Level Input Voltage
Common Mode Input Range
Differential Input Voltage
High-Level Output Current
Low-Level Output Current
VREF + 0.25
Dn, PARIN,
DCSn,
DCKEn,
DODTn
VIL
VREF - 0.25
V
V
VIH
VREF + 0.125
0.65 * VDDQ
VIL
VREF - 0.125
VIH
RESET,
CSGateEN
VIL
0.35 * VDDQ
1.125
VICR
VID
0.675
600
V
CLK, CLK
mV
IOH
-12
12
mA
IOL
IERROL
TA
PTYERR LOW Level Output Current
Operating Free-Air Temperature
25
0
mA
+70
°C
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COMMERCIAL TEMPERATURE GRADE
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 1.8V 0.1V.
Symbol
VOH
Parameter
Test Conditions
Min.
Typ. Max.
Units
Output HIGH Voltage IOH = -12mA, VDDQ = 1.7V
Output LOW Voltage IOL = 12mA, VDDQ = 1.7V
1.2
V
V
V
VOL
0.5
0.5
PTYERR Output
LOW Voltage
IERROL = 25mA, VDD = 1.7V
VERROL
IIL
All Inputs
VI = VDD or GND; VDD = 1.9V
-5
+5
μA
μA
Static Standby
IO = 0, VDD = 1.9V, RESET = GND
200
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
10
IDD
Static Operating
mA
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK =
VIL(AC)
150
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
Dynamic Operating
(clock only)
μA/Clock
MHz
500
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle. One data input
switching at half clock frequency, 50%
duty cycle.
IDDD
μA/Clock
MHz/
Data
Dynamic Operating
(per each data input)
50
Dn, PARIN
CLK and CLK
RESET
VI = VREF 350mV
2
3
3
CIN
VICR = 1.25V, VIPP = 360mV
VI = VDD or GND
4
pF
5
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COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V 0.1V
Symbol
fCLOCK
tW
Parameter
Min.
Max.
Units
MHz
ns
Clock Frequency
410
Pulse Duration; CLK, CLK HIGH or LOW
1
1
tACT
Differential Inputs Active Time
10
15
ns
2
tINACT
Differential Inputs Inactive Time
ns
DCS0 before CLK↑, CLK↓, DCS and CSGateEN
HIGH; DCS1 before CLK↑, CLK↓, DCS0 and
CSGateEN HIGH
0.6
Setup
Time
tSU
ns
DCSn, DODT, DCKE, and Dn after CLK↑, CLK↓
PARIN after CLK↑, CLK↓
0.5
0.5
0.4
0.4
DCSn, DODT, DCKE, and Dn after CLK↑, CLK↓
PARIN after CLK↑, CLK↓
Hold
Time
tH
ns
1
VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of tACT(max) after RESET is taken HIGH.
VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
2
time of tINACT(max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
VDD = 1.8V 0.1V
Symbol Parameter
Min.
410
1.1
Max.
Units
MHz
ns
fMAX
Max Input Clock Frequency
1
tPDM
Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to PTYERR
HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to PTYERR
HIGH to LOW Propagation Delay, RESET↓ to Qn↓
1.6
0.8
1.7
3
2
tPDQ
tPDMSS
tLH
0.4
ns
1
ns
1.2
1
ns
tHL
3
ns
tPHL
tPLH
3
ns
LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑
3
ns
1
2
Design target as per JEDEC specifications.
Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
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Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
VDD = 1.8V 0.1V
Parameter
dV/dt_r
Min.
Max.
Units
V/ns
V/ns
V/ns
1
1
4
4
1
dV/dt_f
1
dV/dt_Δ
1
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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Parity Logic Diagram
22
22
Dn
QnA
QnB
Q
D
D
D
LATCHING AND
PTYERR
D
RESET FUNCTION
PARIN
CLOCK
Register Timing
n - 1
CLK
n
n +1
n + 2
n + 3
n + 4
n + 5
CLK
tSU
tH
Dn
tSU
tH
PARIN
Qn
tPDM,
tPDMSS
tPDM
tPDH
PTYERR
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Test Circuits and Waveforms (VDD = 1.8V 0.1V)
VDD/2
RL = 50Ω
VDD
Test
Point
DUT
CLK
ZO = 50Ω
ZO = 50Ω
RL = 1KΩ
DUT
Test
Point
TL = 50Ω
ZO = 50Ω
TL = 350ps, 50Ω
CLK
Out
CLK Inputs
Test
Point
Out
Test Point
CLK Inputs
CLK
CLK
CL = 20 pF
RL = 1KΩ
Test Point
RL = 100Ω
Test Point
Production-Test Load Circuit
Simulation Load Circuit
CLK
CLK
VID
VICR
VICR
tPLH
tPHL
VTT
VDD
0V
LVCMOS
RESET
Input
VOH
VOL
Output
VTT
VDD/2
VDD/2
tINACT
tACT
Voltage Waveforms - Propagation Delay Times
90%
IDD
10%
LVCMOS
VIH
VIL
RESET
Input
VDD/2
Voltage and Current Waveforms Inputs Active and Inactive
Times
tRPHL
VTT
VOH
VOL
Output
tW
Voltage Waveforms - Propagation Delay Times
VID
Input
VICR
VICR
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
Voltage Waveforms - Pulse Duration
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
20% (unless otherwise specified).
CLK
CLK
VID
VICR
4. The outputs are measured one at a time with one transition per
measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.
VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.
VIL = GND for LVCMOS input.
tSU
tH
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Setup and Hold Times
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
13
IDT74SSTUBH32865A
7103/10
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Test Circuits and Waveforms (VDD = 1.8V 0.1V)
VDD
VDD
DUT
DUT
RL = 50Ω
RL = 1KΩ
Out
Out
Test Point
Test Point
CL = 10 pF
CL = 10 pF
Load Circuit: Error Output Measurements
Load Circuit: High-to-Low Slew-Rate Adjustment
LVCMOS
RESET
Input
VCC
0V
VCC/2
Output
VOH
80%
tPLH
VOH
0V
20%
dt_f
0.15V
Output
Waveform 2
dv_f
VOL
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
Timing
Inputs
VICR
tHL
VICR
VI(PP)
DUT
Out
Test Point
CL = 10 pF
VCC
VOL
Output
Waveform 1
RL = 50Ω
VCC/2
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Load Circuit: Low-to-High Slew-Rate Adjustment
Timing
Inputs
dt_r
VICR
tHL
VICR
VI(PP)
VOH
dv_r
80%
VOH
0V
0.15V
Output
Waveform 2
20%
VOL
Output
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input
slew rate = 1 V/ns 20% (unless otherwise specified).
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
14
IDT74SSTUBH32865A
7103/10
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Package Outline and Package Dimensions - BGA
Package dimensions are kept current with JEDEC Publication No. 95
0.925 Ref
C
ROW A,
COLUMN 1
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
D
J
K
L
d
M
N
P
R
T
b
0.975
Ref
U
V
h
e
TYP
E
T
0.10
C
ALL DIMENSIONS IN MILLIMETERS
T
BALL GRID
REF. DIMS
d
h
D
E
Min/Max
1.10/1.30
e
Horiz
12
Vert
18
Total
160
Min/Max
0.35/0.45
Min/Max
0.27/0.37
b
c
13.00 Bsc
9.00 Bsc
0.65 Bsc
0.975 0.925
NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
15
IDT74SSTUBH32865A
7103/10
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Ordering Information
IDT
XX
SSTUBH XX
XXX
XX
X
Family
Device Type Package
Shipping
Carrier
Temp. Range
8
Tape and Reel
BKG
Low Profile, Fine Pitch, Ball Grid Array - Green
865A 28-Bit 1:2 Registered Buffer for DDR2
32
74
Double Density
0°C to +70°C (Commercial)
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
16
IDT74SSTUBH32865A
7103/10
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
United States
800 345 7015
#20-03 Wisma Atria
+408 284 8200 (outside U.S.)
Singapore 238877
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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