IDT75T54100S66BS304 [IDT]
Microprocessor Circuit, CMOS, PBGA304, 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304;
| 型号： | IDT75T54100S66BS304 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Microprocessor Circuit, CMOS, PBGA304, 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 外围集成电路 |
| 文件： | 总11页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
52100 Device
Application Note AN-268
Initialization of
Application
IDT75T54100
Note
IP Co-Processor
AN-268
Overview
Background Information
Thisapplicationnote"InitializationofIDT75T54100IPCo-Processor"
device describes how to initialize the IPC from power up. A single
IDT75T54100 device can be used or multiple devices can be grouped
together for depth expansion. The first part of this application note will
discuss how to initialize a single device. It will explain the initialization
procedurerequiredinachronologicalorderanddiscussthefeaturesthat
are selectable bythe user. The secondpartofthis applicationnote will
explain the differences in the initialization sequence required when
hookingupmultipledevices inadepthexpandedIPCsystem.
TheIPC(InternetProtocolCo-Processor)familywasdevelopedfor
a wide range ofcommunication andnetworkingapplications. The IPC
family is intended for use in applications that require high speed data
searchingsuchasrouters,highlayerswitchingandintheconvergence
of voice, data, and video.
The IDT75T54100 is part of IPC family of products and is a high
performance pipelined, synchronous 64K x 72 IPC. It utilizes content
addressablememorytechnologytoperformpatternrecognitionfunctions.
Each location in the IPC has a Data entry. The IPC has a 72-bit bi-
directionalbus,whichisa16-bitmultiplexedaddressand72-bitdatabus
thatcansupport66millionlookupspersecond. RefertotheIDT75T54100
Datasheetforafulldevicedescription.
Figure 1.0 Single IPC Device
RST
REQSTB
VDD
PHASEN
CONFIGIN
CLK2X
CE/OE
WE
COMMAND BUS [6:0]
INDEX BUS [20:0]
REQUEST BUS [71:0]
IDT's IPC
75T54100
MATCHIN 0
MATCHIN 1
MATCHIN 2
MATCHIN 3
MATCHIN 4
MATCHIN 5
MATCHIN 6
GND
RDACK
HITACK
MATCHOUT
CONFIGOUT
VALID
5331 drw 01
MAY 2001
6.42
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DSC-5331/00
©2001IntegratedDeviceTechnology,Inc.
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Introduction:
◆ Part One: Single Device Initialization
◆ Part Two: Multiple Device Initialization
PartOneofthisapplicationsnotedescribestheproceduretoinitialize
asingleIPCdevice. Figure1.0showsthehardwareconnectionsforthe
IDT75T54100device. Theprocedureisbrokendownintothesequences
as listedbelowwitheachsequence describedonits ownpage.
PartTwoofthisapplicationsnotedescribesageneraloverviewhow
toinitializeadepthexpandedmultipledeviceIPCsystem. Thedifferences
in the procedure compared to a single device is broken down into the
sequencesaslistedbelow.
✦ Powering Up a Single Device
✦ PoweringUpMultiple Devices
✦BackgroundWrite ofData Array
✦BackgroundWrite ofData Array
✦InitializationofGlobalMaskRegisters(GMRs)
✦InitializationofReplyWidthRegisters(RWRs)
✦InitializationofSystemConfigurationRegister(SCR),
Read Only Registers
✦InitializationofGlobalMaskRegisters(GMRs)
✦InitializationofReplyWidthRegisters(RWRs)
✦InitializationofSystemConfigurationRegister(SCR)
✦ Single Device Summary Table
Anexampleofamultipledevicesystemisdescribedinthefollowing
section. Figure2.0showsthehardwareconnectionsoffourIDT75T54100
devicesinadepthexpandedconfiguration.
✦ Figure 2.0 Example: Multiple IPC Devices
✦Example:MultipleIPCDevices
2
©2001IntegratedDeviceTechnology,Inc.
Introduction
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Application Note AN-268
Initialization of IDT's IP Co-Processor 75P52100 Device
✦ Powering Up a Single Device
ASIC/FPGA Handshaking of signals:
Sequence:
TheusermustinitiallysettheLCbitintheSystemConfigurationRegister
toenablethehandshakingofsignalsbacktotheASIC/FPGA. Thisenables
the RDACK, HITACK and VALID signals to be driven.
SettheREQSTBsignalHighfortwoCLK2Xcyclestosignalthestart
ofavalidIPCoperationanddothefollowing: OntheCommandBusselect
theWriteinstruction,settheCMDbits[3:0]to“0100”andzerosontherest
oftheCommandBus. OntheRequestBus,selecttheSystemConfiguration
Register,settheRequestBus bits [8:1]to“00000011”andzeros tothe
restoftheCommandbusbits.
NextdeactivatetheREQSTBsignal(Low),settheRequestBusbit[28]
toa“1”andzerostotherestofthebusfortwoCLK2Xcycles. Thiswillset
theLCbitintheSystemConfigurationRegistertoa"1",andzerostothe
remainingbits ofthe SCR. The restofthe SCRis configuredinthe last
sequence as shown in Table 5.0.
TheResetsignal(RST)mustbeactive(Low)onpowerupandmust
remainlowwhileallthepowersignals(VDD,VDDQ,VMATCH)andtheclock
signals(CLK2X,PHASEN)becomestable. TheVDDsupplyneedtobegin
ramping up first, followed by the VDDQ supply, and the by the VMATCH
supply. Forpowerdownreversethis order. TheIPCwillrespondtothe
reset by asynchronously tri-stating the I/O’s and output pins which
prevents bus contention. The internal logic and System Configuration
Registercomesoutofresetsynchronouslyaftertheclocksignalsstabilize
and VMATCH, VDD and VDDQ supplies ramp to operating levels. The
Enable(En)bitintheSystemConfigurationRegisteris resetto“0”.
Device Identification:
Afterthepowersuppliesandclocksignalshavestabilized,theIPC
requiresthattheRSTandREQSTBsignalsbelowandtheclocksignals
beactiveforaminimumofthirty-twoCLK2Xclockcyclestoinsureproper
initialization. NextdeactivatetheRSTsignaltocommenceIPCoperations.
SettheCONFIGINsignalhighforaminimumofsixteenCLK2Xclockcycles
tosettheDeviceIDintheDepthExpansionRegister. Oncethesixteen
CLK2X cycles have passed the IPC is ready to begin initialization
procedures.
Table1.0PowerSequence
# of CLK2X
cycles
Step Pins / Signals Procedure
Description
RST must be active (low) at power up and remain active until Step 3.
Power supplies and Clock signals need to ramp up to operating
conditions and become stable. VDDQ can not ramp up ahead of VDD.
Activate
RST,V
MATCH,
Reset, Ramp
up supply &
clock signals
V ,V
,
DD DDQ
1(1)
NA
CLK2X,
PHASEN
Reset internal
logic and
registers
After signals of Step 1 are stable, REQSTB and RST must be low for thirty-two
REQSTB,
RST
2
3
CLK2X cycles to insure that all internal logic and registers are fully reset.
32
16
De-activate RST signal to commence IPC operations. Set CONFIGIN signal high
for a sixteen CLK2X cycles to set the Device ID in the Device Expansion Register
CONFIGIN
REQSTB
Set High
Activate
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Command
Bus
Select Write
Instruction
Using Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
4a(2)
2
Request
Bus
Using Request Bus select System Configuration Register,
set Request Bus bits [8:1] to "0000 0011", zeros to rest of bus.
Select SCR
De-activate
Set LC bit
REQSTB
De-activate REQSTB (Low).
4b(2)
2
Request
Bus
Using RequestBus, set the LC bit [28] to a 1 in the SCR, zeros to rest of bus.
The Background Write of Data Array is described in the next section.
5331 tbl 01
NOTE:
1. It is very important that the voltage on the input pins never exceeds the VDDQ level by more than 300mV. Higher voltages could turn on the ESD diodes and the
device could be exposed to very high electrical currents which would permanently damage the device.
2. If the ASIC/FPGA does not require the handshake signals during initialization then the LC bit does not have to be enabled until the System Configuration Register is
configured.
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3
©2001IntegratedDeviceTechnology,Inc.
Powering Up A Single Device
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
✦ Background Write of Data Array
Overview:
WhentheIPCdevicepowersuprandominformationisstoredinthe
DataArray. ItisrecommendedthattheentireDataArraybeinitializedto
preventafalsematchfromoccurringinanun-initializedlocation. TheData
Arrayshouldbeinitializedtoallzeros.
Sequence:
DataArray
TheproceduretoinitializethatDataArrayisasfollows:Signalthestart
ofthe a validoperationbyactivatingthe REQSTBsignal(High)fortwo
CLK2Xcycles. OntheCommandBusselecttheWriteinstruction,setthe
CMDbits[3:0]to“0100”andzerostotherestoftheCommandBus. On
theRequestBus,selecttheAccessTypesetbits[25:24]to“01”forData
Array,settheGMRSelectbits[23:22]to"11"fornomasking,theAddress
fieldbits[15:1]toallzeros(initialAddress)andtherestoftheRequestBus
bitstozeros.
NextdeactivatetheREQSTBsignal(Low),settheRequestBusbits
[71:0]toall0'sfortwoCLK2Xcycles. Repeatthissequenceforallofthe
64KDataentries,incrementtheAddresslocationby1untilalloftheentries
havebeeninitialized.
Table2.0BackgroundSequence
# of CLK2X
cycles
Step Pins / Buses
Procedure
Activate
Description
REQSTB
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Command
Select Write
Instruction
5a(3)
Bus
2
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
Request
Bus
Select Data
Entries
Using Request Bus set: Access Type bits [25:24] to "01" for Data, GMR Select bits [23:22] to "11"
for no masking, Address field bits [15:1] to all zeros (initial Address) and zeros to the rest of bus.
REQSTB
De-activate
De-activate REQSTB (Low).
5b(3)
2
Request
Bus
Write 0's to
Data Array
Set "0's" on all Request Bus bits [71:0].
Repeat Step 5 for every Data Address location.
The Initialization of the Global Mask Registers is described in the next section.
5331 tbl 02
NOTE:
3. Repeat this step for the entire Data Array, increment the Address location by 1 until all 64K Data entries are initialized. This takes 262,144 CLK2X cycles.
4
©2001IntegratedDeviceTechnology,Inc.
Background Write of Data and Mask Arrays
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Application Note AN-268
Initialization of IDT's IP Co-Processor 75P52100 Device
✦ Initialization of Global Mask Registers (GMRs)
Overview:
Table 3.1 — GMRs Addresses
TheGlobalMaskRegisters(GMRs)donothaveanydefinedinitialized
state.IftheuserintendsonusingtheGMRsthentheappropriateregister(s)
must be initialized. If the user does not intend on using the GMRs, no
initializationisrequired. Thereareatotalof15GlobalMaskRegistersin
theIPCthatareusedduringlookupandwriteoperations.Thereareseven
GMRsassignedforx72lookupwidths,fourforx144Lookupwidthsand
four for x288 Lookup widths. There are three GMRs used for write
instructions. Allwritesareof72bits. EachGMRcontains72bits. Table
3.1showstheaddressassignmentofeachregister.
Address
0001 0000
0001 0001
0001 0010
Register
Function
Global Mask Register 10
Global Mask Register 11
Global Mask Register 12
72 bit Lookup / Write
72 bit Lookup / Write
72 bit Lookup / Write
0001 0011
Global Mask Register 13
72 bit Lookup
0001 0100
0001 0101
0001 0110
0010 0000
0010 0001
0010 0100
0010 0101
0011 0000
0011 0001
0011 0010
0011 0011
Global Mask Register 14
Global Mask Register 15
Global Mask Register 16
Global Mask Register 20
Global Mask Register 21
Global Mask Register 24
Global Mask Register 25
Global Mask Register 30
Global Mask Register 31
Global Mask Register 32
Global Mask Register 33
72 bit Lookup
72 bit Lookup
72 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
Sequence:
TheproceduretoinitializetheGMRsisasfollows:Signalthestartof
thenextvalidoperationbyactivatingtheREQSTBsignal(High)fortwo
CLK2Xcycles. OntheCommandbusselecttheWriteinstruction,setthe
CMDbits[3:0]to“0100”andzero’stotherestoftheCommandBus. On
theRequestBusselecttheaddressoftheGMR,usingRequestBusbits
[8:1]andzeros totherestoftheRequestBus bits.
NextdeactivatetheREQSTBsignal(Low),settheconfigurationofthe
GMRaddressedonRequestBusbits[71:0]fortwoCLK2Xcycles. Repeat
this sequence for every GMR that is to be used.
Table3.0GMRSequence
5331 tbl 03
# of CLK2X
cycles
Step Pins / Buses
REQSTB
Procedure
Activate
Description
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Command
Select Write
Instruction
6a(4)
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
2
Bus
Request Bus Select GMR
On the Request Bus, set the GMR address on bits [8:1], set zeros on the rest of Request Bus.
De-activate REQSTB (Low).
REQSTB
De-activate
6b(4)
2
Configure
GMR
Request Bus
Configure the GMR using Request Bus bits [71:0].
The initializations of the Reply Width Registers is described in the next section.
5331 tbl 04
NOTE:
4. Repeat this step for each register. To determine the total number of CLK2X cycles needed, add four CLK2X cycles for every register initialized.
6.42
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©2001IntegratedDeviceTechnology,Inc.
Initialization of Global Mask Registers (GMRs)
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
✦ Initialization of Reply Width Registers (RWRs)
Overview:
TheReplyWidthRegisters(RWRs)donothaveanydefinedinitialized
Table 4.1 — RWRs Addresses
stateandmustbeinitialized. TherearefourReplyWidthRegistersinthe
IPCthatareusedforlookupandwriteoperations. Theinformationstored
intheRWRsforthespecifiedwidthissentalongwiththeIndexafteralookup
operation. IftheuserintendsonusingthisfeaturethentheRWRsshould
beconfiguredasneeded. Iftheuserdoesnotintendonusingthisfeature
then the RWRs need to be configure to all zeros. Table 4.1 shows the
addressassignmentsofeachregister.
Address
Register
Function
0000 0100
Reply Width Register 0
Reply Width Register 1
Reply Width Register 2
Reply Width Register 3
Device Operation
Device Operation
Device Operation
Device Operation
0000 0101
0000 0110
0000 0111
Sequence:
TheproceduretoinitializetheReplyWidthRegistersissimilartothat
of GMRs. Signal the start of the next valid operation by activating the
REQSTBsignal(High)fortwoCLK2Xcycles. OntheCommandbusselect
theWriteinstruction,settheCMDbits[3:0]to“0100”andzero’stotherest
oftheCommandBus. OntheRequestBusselecttheaddressoftheRWR,
usingRequestBusbits[8:1]andzerostotherestoftheRequestBusbits.
NextdeactivatetheREQSTBsignal(Low),settheconfigurationofthe
RWRaddressedonRequestBusbits[71:0]fortwoCLK2Xcycles. Repeat
this sequence foreveryRWRthatis tobe used.
5331 tbl 06
Table4.0SRRSequence
# of CLK2X
cycles
Step Pins / Buses
REQSTB
Procedure
Activate
Description
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
7a(4)
2
Command
Bus
Select Write
Instruction
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
Request Bus Select RWR
On the Request Bus, set RWR address on bits [8:1], set zeros on the rest of Request Bus.
De-activate REQSTB (Low).
REQSTB
De-activate
7b(4)
2
Configure
RWR
Request Bus
Configure the RWR using Request Bus bits [71:0].
The initialization of the System Configuration Register is described in the next section.
5331 tbl 05
NOTE:
4. Repeat this step for each register. To determine the total number of CLK2X cycles needed, add four CLK2X cycles for every register initialized.
6
©2001IntegratedDeviceTechnology,Inc.
Initialization of Reply Width Registers (RWRs)
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Application Note AN-268
Initialization of IDT's IP Co-Processor 75P52100 Device
✦ Initialization of System Configuration Register (SCR)
Overview:
ThefinalregisterthatneedstobeinitializedistheSystemConfigu-
andzero’stotherestoftheCommandBus. OntheRequestBusselect
ration Register to enable the device for operation. The Index Bus will theSCR,settheRequestBusbits[8:1]to"00000011"andzerostothe
remain tri-stated until the Enable bit (EN) is set to a 1 in the System
ConfigurationRegister. Afterthisregisterisconfiguredthedeviceisready
foroperation.
restoftheRequestBusbits.
Next deactivate the REQSTB signal (Low) for two CLK2X cycles.
UsingtheRequestBusconfiguretheSCRasfollows: SettheReserved
bits [39:32], [27:12]and[4:2]to0's; Setbits [31:28]to1's (sets the EN,
SR,LS,LCbits),SR=1meansZBTTM SRAMattachedtoIndexBus; Set
the IPC Grp bits [11:5] to 0's; Set the PD bits [1:0] to "00" , a delay of 0
issetsotheRDACK,HITACKandVALIDsignalsaredrivenwiththeIndex;
SetzerostotherestoftheRequestBusbits. RefertotheIDT75T54100
DatasheetforfurtherdetailsontheSystemConfigurationRegister.
Sequence:
TheproceduretoinitializetheSystemConfigurationRegisteristhe
sameastheGMRsandRWRs.Signalthestartofthenextvalidoperation
byactivatingtheREQSTBsignal(High)fortwoCLK2Xcycles. Onthe
CommandbusselecttheWriteinstruction,settheCMDbits[3:0]to“0100”
Table5.0SCRSequence
# of CLK2X
cycles
Step Pins / Signals Procedure
Description
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
REQSTB
Activate
Command
Bus
Select Write
Instruction
Using the Command Bus select Write instruction,
set CMD [3:0] bits to "0100", zeros to rest of bus.
8a
2
Using Request Bus select System Configuration Register,
set Request Bus bits [8:1] to "0000 0011", zeros to rest of bus.
Request Bus Select SCR
REQSTB
De-activate
De-activate REQSTB (Low).
8b(5)
2
Configure
SCR
Using Request Bus configure SCR, set EN, SR, LS and LC bits [31:28] to 1's and
zeros to restof bus. SR=1 defines ZBT SRAM output timing has been selected.
Request Bus
TM
Commence Normal Operation.
5331 tbl 07
NOTE:
5. Refer to the Datasheet for more details on the System Configuration Register and Output Timing (with ZBTTM SRAM).
✦ Read Only Registers
TheIdentificationRegister,InternalTestRegister,DepthExpansion
Register and the Search Result Registers are read only registers and
cannotbeinitializedthroughanIPCwriteoperation. Theinformationstored
intheIdentificationRegisterandInternalTestRegisterisencodedinthe
deviceduringmanufacturing. Theinformation(DeviceID)storedinthe
Depth Expansion Register is hardware controlled by the CONFIGIN
signalandisprogrammedinStep3. TheSearchResultRegisterswillbe
dynamicallychangingasthedeviceisused. Itisimportanttorealizethat
theseregistersinitializeinarandomstateandshouldnotbeusedforan
IndirectWriteorReadoperationuntilaftertheyhavebeenupdatedfrom
a previous Lookup operation.
6.42
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©2001IntegratedDeviceTechnology,Inc.
Initialization of System Configuration Register (SCR)
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Table 6.0 Single Device Summary Table
Step
Pins / Signals
Procedure
Description
CLK2X cycles
V ,
Activate Reset,
Ramp up supply
& clock signals
RST, DD
RST must be active before powering up the device and remain active until Step 3.
Power supplies and Clock signals need to ramp up to operating conditions and become stable.
VDDQ can not ramp up ahead of VDD.
1(1)
NA
V
,V
DDQ MATCH
CLK2X,PHASEN,
Reset internal logic
and registers
After signals of Step 1 are stable, REQSTB and RST must be low for thirty-two
REQSTB,
RST
2
3
32
16
CLK2X cycles to insure that all internal logic and registers are fully reset.
De-activate RST signal to commence IPC operations. Set CONFIGIN signal high
for sixteen CLK2X cycles to set the Device ID in the Device Expansion Register.
CONFIGIN
REQSTB
Set High
Activate
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
4a(2)
4b(2)
2
2
Command Bus Select Write Instruction
Using Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
Using Request Bus select SCR, set Request Bus bits [8:1] to "0000 0011", zeros to rest of bus.
De-activate REQSTB (Low) .
Request Bus
REQSTB
Select SCR
De-activate REQSTB
Set LC bit
Request Bus
REQSTB
Using Request Bus, set the LC bit [28] to a 1 in the SCR, zeros to rest of bus.
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
Activate
Command Bus Select Write Instruction
5a(3)
5b(3)
2
2
Using Request Bus set: Access Type bits [25:24] to "01" for Data, GMR Select bits [23:22] to "11"
for no masking, Address field bits [15:1] to all zeros (initial Address) and zeros to the rest of bus.
Request Bus
Select Data Entries
REQSTB
De-activate
De-activate REQSTB (Low).
Request Bus
Write 0' s to Data
Set "0's" on all Request Bus bits [71:0].
Repeat Step 5 for every Data Address location.
REQSTB Activate
6a(4) Command Bus Select Write Instruction
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
On the Request Bus set the GMR address bits [8:1], set zeros on the rest of Request Bus.
De-activate REQSTB (Low).
2
2
2
2
Request Bus
REQSTB
Select GMR
De-activate
6b(4)
Request Bus
REQSTB
Configure GMR
Activate
Configure the GMRusing Request Bus bits [71:0].
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
On the Request Bus set the RWR address bits [8:1], set zeros on the rest of Request Bus.
De-activate REQSTB (Low).
7a(4) Command Bus Select Write Instruction
Request Bus
REQSTB
Select RWR
De-activate
7b(4)
8a
Request Bus
REQSTB
Configure RWR
Activate
Configure the RWRusing Request Bus bits [71:0].
Activate REQSTB (High) for two CLK2X cycles to signal the start of a valid operation.
Using the Command Bus select Write instruction, set CMD [3:0] bits to "0100", zeros to rest of bus.
Command Bus Select Write Instruction
2
Request Bus
REQSTB
Select SCR
De-activate
Using Request Bus select SCR, set Request Bus bits [8:1] to "0000 0011", zeros to rest of bus.
De-activate REQSTB (Low).
8b(5)
2
Using Request Bus configure SCR, set EN, SR, LS and LC bits [31:28] to 1's and
zeros to rest of bus. SR=1 defines ZBT SRAM output timing has been selected.
Request Bus
Configure SCR
TM
Commence Normal Operation.
5331 tbl 08
NOTE:
1. It is very important that the voltage on the input pins never exceeds the VDDQ level by more than 300mV. Higher voltages could turn on the ESD diodes and the
device could be exposed to very high electrical currents which would permanently damage the device.
2. If the ASIC/FPGA does not require the handshake signals during initialization then the LC bit does not have to be enabled until the SCR is configured.
3. Repeat this step for the entire Data Array, increment the Address location by 1 until all 64K Data entries are initialized. This takes 262,144 CLK2X cycles.
4. Repeat this step for each register. To determine the total number of CLK2X cycles needed, add four CLK2X cycles for every register initialized.
TM
5. Refer to the Datasheet for details on the System Configuration Register description and Output Timing (with ZBT SRAM).
8
©2001IntegratedDeviceTechnology,Inc.
Single Device Summary Table
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Application Note AN-268
Initialization of IDT's IP Co-Processor 75P52100 Device
✦ Multiple Device Initialization
Introduction
◆ Background Write of Data Array
Basic terminology is used to explain the possible options when
cascadingmultipleIPCdevices. WhendescribinganIPCsystem,there
canbeuptoeightIPC’s inonesystem. InaIPCsystemthedevicewith
aDeviceID#of0isthehighestprioritydeviceandthefirstIPCinthesystem.
ThedevicewiththehighestDeviceID#isthelastIPCinthesystemand
isthelowestprioritydevice. ThelowestprioritydeviceintheIPCsystem
actsasthemasterdevice,itistheonlydevicethatknowsifamatchisfound
inanyofthehigherprioritydevices. Thelast(lowestpriority)devicemust
havetheLastIPC(LC)bitset(High)initsSystemConfigurationRegister.
SettingtheLCbitmakesitresponsiblefordrivingtheRDACK,HITACK
andVALIDsignalsforthesystemtotheASIC/FPGA.
Itis recommendedthattheentireDataArrayineachofthe
devices inthe IPCsystemare initialized. Ifinanyofthe IPCdevices
theentirearrayisnotfullyinitializedtoaknownstateafalsematch
mightberealizedatanun-initializedlocation.
◆ Initialization of Global Mask Registers (GMRs)
If there is a need to use GMRs then the user must initialize the
appropriate register(s) in each of the IPC devices. If the user does not
intendonusingtheGMRs,noinitializationisrequired.
AnIPCsystemcansupportuptoeightdistinctIPCgroups. AnIPC
groupisdefinedaseitherasingleIPCdeviceormultipleIPCdevicesthat
drive a specific bank of SRAMs. The last device in the IPC group is
responsiblefordrivingtheSRAMcontrolsignalsandIndexBuswhenno
operationisongoing,whichpreventstheIndexBusfromfloating. Thelast
(lowestpriority)deviceintheIPCgroupmusthavetheLastSRAM(LS)
bitset(High)initsSystemConfigurationRegistertodrivetheSRAMcontrol
signals.
◆ Initialization of Reply Width Registers (RWRs)
IneachoftheIPCdevicesintheIPCsystem,itisrecommendedthat
allfourReplyWidthRegistersbeinitializedwiththeDeviceIDinthethree
widthfieldsineachoftheregisters. Thisusefulsotheusercanidentifywhich
IPCdevicehadthematchintheIPCsystem.
◆ Initialization of System Configuration Register (SCR)
Thedifferenceininitializingamultipledevicesystemcomparedtoa
singledevice(PartOne)isdescribedineachofthesequencesasfollowed:
Themajordifferenceininitializingmultipledevicesisinthesetupofthe
SystemConfigurationRegisterineachoftheIPCdevices. Thelast(lowest
priority)deviceintheIPCsystemisresponsiblefordrivingtheRDACK,
HITACKandVALIDsignalsforthesystemtotheASIC/FPGAandmust
be the only device to have the Last IPC (LC) bit [28] set in its System
ConfigurationRegister.
◆ Powering up the Multiple Devices
Device Identification:
Tosetthe Device IDofmultiple IPC’s, the CONFIGINsignalofthe
highestpriorityIPCneedstobesethigh. TheCONFIGOUTsignalistied
totheCONFIGINsignalofthenexthighestprioritydeviceandsoonfor
therestofthedevicesinthesystem. AftertheCONFIGINsignalshasbeen
active (High) for 16 CLK2X cycles the IPC will to begin to drive the
CONFIGOUTsignaltothenextdeviceinthesystem. Todeterminethe
total number ofCLK2X cycles neededtosetthe Device ID ineachIPC
TheotherdifferenceisinthesetupoftheIPCGrpbits. TheIPCGrp
field bits [11:5] are defined as follows: Bit 5 corresponds to IPC0, bit 6
corresponds toIPC1andsoonthroughbit11correspondingIPC6. To
determineanIPCgroup,onlythebitsthatrepresenttothehigherpriority
devicesintheIPCgroupmustbesethigh,thebitthatrepresentsthelowest
prioritydeviceintheIPCgroupmustbesetlow.Thebits thatrepresent
theotherdeviceswithintheIPCsystembutnotwithintheIPCgroupmust
alsobesetlow. Thelowestprioritydevicerecognizes theIPCGrpfield
bitsandtheLastSRAM(LS)bittodetermineitsresponsibilitytodrivethe
SRAMcontrolssignalsandtheIndexBusfortheIPCgroupitbelongsto.
In defining IPC group the Pipeline Delay (PD) field bits [1:0], IPC
Group(IPCGrp)fieldbits [11:5]andSRAMtype(SR)fieldbit[30]must
besetthesameineachofthedevicesintheIPCgroup. Thelast(lowest
priority)device inthe IPCgroupwillbe the onlydevice toalsohave the
LastSRAM (LS) bit[29]setinits SCR.
device, add 16 CLK2X cycles for each IPC device in the system.
ASIC/FPGA Handshaking of signals:
Onlythelast(lowestpriority)deviceintheIPCsystemmusthave
theLCbitset(High)initsSystemConfigurationRegistertostartthe
handshakingofsignalsbacktotheASIC/FPGA. Alloftheother
devices inthe IPCsystemcannothave the LCbitset.
6.42
9
©2001IntegratedDeviceTechnology,Inc.
MultipleDeviceInitialization
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Figure 2.0 Example: Multiple IPC Devices
RST
REQSTB
PHASEN
VDD
CONFIGIN
CLK2X
IPCO (Device ID# O) it is the high-
estprioritydeviceintheIPCsystem.
COMMAND BUS [6:0]
REQUEST BUS [71:0]
ID T's IP C
MATCHIN 0
MATCHIN 1
MATCHIN 2
MATCHIN 3
MATCHIN 4
MATCHIN 5
MATCHIN 6
75 T5410 0
IP C 0
IPC0 and IPC1 are both in IPC Grp
Zero bits[11:5] "0000001".
IPC1 is the lowest priority device in
IPC Grp 0. The last SRAM (LS) bit
is set in the its SCR.
GND
CONFIGOUT
MATCHOUT
RST
REQSTB
PHASEN
CLK2X
CONFIGIN
CE
/
OE
WE
ZBTTM
.
SRAMs
INDEX BUS [20:0]
ID T 's IP C
7 5 T 5 4 1 0 0
IP C 1
MATCHIN 0
MATCHIN 1
MATCHIN 2
MATCHIN 3
MATCHIN 4
MATCHIN 5
MATCHIN 6
.
GND
CONFIGOUT
MATCHOUT
RST
REQSTB
PHASEN
CLK2X
CONFIGIN
ID T 's IP C
7 5 T 5 4 1 0 0
IP C 2
MATCHIN 0
MATCHIN 1
MATCHIN 2
MATCHIN 3
MATCHIN 4
IPC3 (Device ID# 3) it is the lowest
priority device in the IPC system
and the lowest priority device in IPC
Grp 1. The last SRAM (LS) bit is set
in the its SCR.
IPC2 and IPC3 are both in IPC Grp
One bits[11:5] "0000100".
MATCHIN 5
MATCHIN 6
GND
CONFIGOUT
MATCHOUT
RST
REQSTB
P HAS EN
CONFIGIN
CLK2X
CE
/
OE
WE
ZBTTM
.
SRAMs
ID T 's IP C
7 5 T5 4 1 0 0
IP C 3
INDEX BUS [20:0]
MATCHIN 0
MATCHIN 1
MATCHIN 2
MATCHIN 3
MATCHIN 4
MATCHIN 5
MATCHIN 6
Last IPC (LC) bit is set in the SCR of
IPC3 and will drive these signals to
the ASIC/FPGA.
GND
RDACK
HITACK
MATCHOUT
CONFIGOUT
VALID
10
5 33 1 drw0 2
©2001IntegratedDeviceTechnology,Inc.
Figure 2.0 Example: Multiple IPC Devices
Initialization of IDT75T54100 IP Co-Processor
Application Note AN-268
Application Note AN-268
Initialization of IDT's IP Co-Processor 75P52100 Device
✦ Example: Multiple IPC Devices
Overview
◆ Initialization of Global Mask Registers (GMRs)
TheproceduretoinitializetheGMRsineachoftheIPCdevicesisthe
same except for Device ID. In Step 6a of Table 3.0 when selecting the
GMR, it is also necessary to set the Device ID on the Request Bus as
describedpreviously.
Figure2.0showsthehardwareconnectionsforfourdevicesinanIPC
system. IntheIPCsystem,IPC0isthehighestprioritydeviceandIPC3
is thelowestprioritydevice. IPC3beingthelowestprioritydeviceinthe
IPCsystemistheonlydeceivetohavetheLC(LastIPC)bitsetinitsSystem
ConfigurationRegister. InthisexampletheIPCsystemismadeupoftwo
IPC groups. IPC0 and IPC1 are part of IPC Grp Zero, IPC2 and IPC3
arepartofIPCGrpOne. BothIPC1andIPC3arethelowestprioritydevice
in the their respective IPC Groups therefore they are the only device to
havetheLS(LastSRAM)bitsetintheirSystemConfigurationRegisters.
Thedifferenceininitializingthisexamplecomparedtoasingledevice(Part
◆ Initialization of Reply Width Registers (RWRs)
ItisrecommendedthattheReplyWidthRegistersineachoftheIPC
devices be initialized with its Device ID. In Step 7a of Table 4.0 when
selectingtheRWR,itisalsonecessarytosettheDeviceIDontheRequest
Bus as describedpreviously. InStep7bofTable 4.0whenconfiguring
theRWRsettheDeviceIDoftheIPCaddressedinthethreewidthfields
andzerostotherestoftheRequestBusbits. RefertotheIDT75T54100
DatasheetforfurtherdetailsontheReplyWidthRegisters.
One)isdescribedineachofthefollowingsequenceslistedbelow.
◆ Powering up the Multiple Devices
Device Identification:
The CONFIGIN signal of IPC0 needs to be set high. The CONFI-
GOUT signal of IPC0 is tied to the CONFIGIN signal of IPC1 and so on
fortherestofthedevicesintheIPCsystem. AftertheCONFIGINsignal
of IPCO has been high for 16 CLK2X cycles it will to begin to drive the
CONFIGOUTsignaltothenextdeviceintheIPCsystem. Step3ofTable
1.0forthis example willtake 16x4CLK2Xcycles tosetthe Device IDin
eachofthedeviceintheIPCsystem. EachdevicemusthaveitsDevice
ID set before moving on to Step 4 of Table 1.0.
◆ Initialization of System Configuration Register (SCR)
InthisexampletheSystemConfigurationRegisterofeachoftheIPC
devicesissetupuniquely. TosettheSCRofIPC0,IPC1,IPC2andIPC3
repeattheprocedureforeachofthedevices. InStep8aofTable5.0when
selectingtheSCR,itisnecessarytoselecttheIPCdeviceusingtheRequest
Bus bits [33:26]as describedpreviously. InStep8b ofTable 5.0when
configuring the SCR set each IPC up as shown in Table 7.0 below and
zerostotherestoftheRequestBusbits.
ASIC/FPGA Handshaking of signals:
IPC3beingthe lastIPCneeds tohave the LCbitsetinits System
ConfigurationRegistertoenablethehandshakingofsignalsbacktothe
ASIC/FPGA. InStep4a ofTable 1.0whenselectingthe System
ConfigurationRegister,itisalsonecessarytoselectIPC3usingthe
Device IDfieldofthe RequestBus. Setthe Device IDfieldbits [33:26]
to“00000011”.
Table 7.0 — SCR Bit Assignment
IPC
Res. EN SR LS LC Res. IPC Grp Res. PD
[4:2] [1:0]
Device [39:32] [31] [30] [29] [28] [27:12] [11:5]
IPC0
IPC1
IPC2
IPC3
0's
0's
0's
0's
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
1
0's
0's
0's
0's
0000 001 0's
00
00
◆ Background Write of Data Array
0000 001 0's
0000 100 0's
0000 100 0's
The procedure to initialize the Data Array in each of the IPC
devices is the same except for Device ID. In Step 5a of Table 2.0
whenselectingthe Data entry, itis alsonecessarytosetthe Device ID
onthe RequestBus. SetRequestBus bits [33:26]to“00000000”to
select IPC0, to “00000001” for IPC1, to “00000010” for IPC2 and
“00000011” for IPC3.
00
00
5331 tbl 09
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6.42
11
©2001IntegratedDeviceTechnology,Inc.
Example: Multiple IPC Devices
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