IDT77V222L155PG8 [IDT]
ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208;
| 型号： | IDT77V222L155PG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总24页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 155 Mbps ATM SAR CONTROLLER
IDT77V222
WITH ABR SUPPORT FOR PCI-BASED
NETWORKINGAPPLICATIONS
Integrated Device Technology, Inc.
KEY FEATURES
• Full-duplex Segmentation and Reassembly (SAR) at
155Mbps"wire-speed"(310Mbpsaggregatespeed)
• Operates with ATM Networks up to 155.52 Mbps
• Stand-alone Controller: Embedded Processor not required
• Performs ATM Layer Protocol Functions
• Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
• Supports Constant Bit Rate (CBR), Variable Bit Rate
(VBR), and Unassigned Bit Rate (UBR), and Available Bit
Rate (ABR) Service Classes
• Null Cell Disable Option During Transmit
• RM Cell Handling
• Option to Select ITU or ATM Null Cell Format
• NAND, Scan, and Output Test Modes
• UTOPIA Level 1 Interface to PHY
• Utility Bus Interface for PHY Management
• Serial EEPROM Interface
• EPROM Interface
• PCI 2.1 Compliant
• Segments and Reassembles CS-PDUs into Host Memory
• Up to 256 Open Transmit Connections
• Compact PCI R1.0 Hot Swap Friendly Compliant
• UNI 3.1, TM 4.0 compliant
• Up to 256 Smultaneous Receive Connections
• ABR, VBR, UBR Selectable per VC Time-out
• Automatic AAL5 Padding
• Four Buffer Pools for Independent or Chained Reassembly
• Buffer Management Options for MPEG Operation
• Supports Any Buffer Alignment Condition
• Free Bufffer Queues Mapped Into PCI Memory Space
• Rx FIFO Size (Configurable to 1024 Kbytes)
• Configurable Transmit FIFO Depth for Reduced Latency
• Supports Big and Little Endian Data Transfers
• UTOPIA Master/Slave mode
• Meets PCI Bus Power Management and Interface Specifi-
cation Revision 1.1
• Pin Compatible with IDT 77211/77222 SAR
• Software Compatible with the IDT 77222
• Commercial and Industrial Temprature Ranges
• 208-Lead PQFP Package (28 x 28mm)
• Software Drivers:
SARWIN2DemonstrationProgram
NDISDriver
Vx Works (3rd party)
Linux(3rdparty)
SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM
16K x 32
EPROM
SRAM
PCI BUS
8
32
Rx UTOPIA Bus
8
2
155Mbps
IDT77V222
155Mbps
PCI ATM
ABR SAR
33MHZ
32
Tx UTOPIA Bus
PHY
8
2
Utility Bus
8
80.0MHZ OSC.
EEPROM
5351 drw 01
NICStAR is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
JANUARY2001
©2001IntegratedDeviceTechnology,Inc.
DSC-5351/8
1
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
DESCRIPTION
The IDT77V222 NICStAR™ is a member of IDT's family of IDT77V222intoATMcellpayloads. Fromthis,theIDT77V222
products for Asynchronous Transfer Mode (ATM) networks. then creates complete 53-byte ATM cells which are sent
The IDT77V222 performs both the ATM Adaptation Layer through the network. The IDT77V222's on-chip PCI bus
(AAL) Segmentation and Reassembly (SAR) function and the master interface provides efficient, low latency DMA trans-
ATM layer protocol functions.
fers with the host system, while its UTOPIA interface provides
A Network Interface Card (NIC) or internetworking product direct connection to PHY components used in 25.6 Mbps to
based on the IDT77V222 uses host memory, rather than local 155 Mbps ATM networks.
memory, to reassemble Convergence Sublayer Protocol
The IDT77V222 is fabricated using state-of-the-art CMOS
Data Units (CS-PDUs) from ATM cell payloads received from technology, providing the highest levels of integration, perfor-
the network. When transmitting, as CS-PDUs become ready, mance and reliability, with the low-power consumption char-
they are queued in host memory and segmented by the acteristics of CMOS.
T x
8
/
Transmit
Control
Tx U topia
Bus
U topia
Interface
32
S R A M
Bus
/
SR AM IN TER FA CE
PCI
32
PCI Bus
/
Interface
R x
Receive
C ontrol
R x U topia
Bus
8
/
Utopia
Interface
8
/
U tility
EEPRO M O UT
EEP RO M IN
5351 drw 02
Block Diagram of the 77V222 ABR SAR
2
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PACKAGE PINOUT
208 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5
Vcc
AD(31)
AD(30)
AD(29)
AD(28)
AD(27)
AD(26)
GND
1
GND
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7
2
PHY_INT
PHY_RST
UTL_ALE
Index
3
4
5
UTL_RD
UTL_W R
GND
6
7
8
UTL_AD(7)
UTL_AD(6)
UTL_AD(5)
UTL_AD(4)
Vcc
GND
9
AD(25)
AD(24)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
C/BE(3)
IDSEL
AD(23)
AD(22)
GND
GND
AD(21)
Vcc
UTL_AD(3)
GND
UTL_AD(2)
UTL_AD(1)
UTL_AD(0)
Vcc
SAR_CLK
GND
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
GND
EEDO
IDT77V222 SAR Controller
With ABR Support
208 Pin PQFP
Pinout
EEDI
EESCLK
EECS
Vcc
GND
E_CE
C/BE(2)
Vcc
SR_I/O(31)
SR_I/O(30)
SR_I/O(29)
GND
PU-208
FRAM E
IRDY
Refer to PSC-4053 for
detailed package drawing
TRDY
DEVSEL
STOP
GND
SR_I/O(28)
SR_I/O(27)
SR_I/O(26)
SR_I/O(25)
SR_I/O(24)
Vcc
GND
INTA
Vcc
SR_I/O(23)
GND
PERR
SERR
PAR
SR_I/O(22)
SR_I/O(21)
SR_I/O(20)
SR_I/O(19)
SR_I/O(18)
SR_I/O(17)
GND
C/BE(1)
AD(15)
GND
GND
AD(14)
AD(13)
AD(12)
AD(11)
AD(10)
AD(9)
AD(8)
GND
SR_I/O(16)
SR_I/O(15)
SR_I/O(14)
SR_I/O(13)
SR_I/O(12)
SR_I/O(11)
Vcc
1 1 1 1 1
0 0 0 0 0
0 1 2 3 4
5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9
3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
5351 drw 03
3
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PACKAGE DRAWING
1.228 ±0.016 (31.2 ±0.4)
1.10 ±0.004 (28.0 ±0.1)
208
157
Index
1
156
0.02 ±0.004
(0.5 ±0.1)
0.008 ±0.004
(0.2 ±0.1)
105
52
104
53
0.133 ±0.004
(3.37 ±0.1)
0.013 ±0.002
(0.33 ±0.06)
0.024 ±0.008
(0.6 ±0.2)
0.063 (1.6)
5351 drw 04
4
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DEFINITIONS
Pin #
Name
I/O
I
Bus Name
power
PCI
Description
1
V
CC
2
AD(31)
AD(30)
AD(29)
AD(28)
AD(27)
AD(26)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
3
PCI
4
PCI
5
PCI
6
PCI
7
PCI
8
power
power
PCI
9
GND
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AD(25)
AD(24)
C/BE(3)
IDSEL
AD(23)
AD(22)
GND
I/O
I/O
I/O
I
address/data line
address/data line
bus command
bus ID select
PCI
PCI
PCI
I/O
I/O
I
PCI
address/data line
address/data line
PCI
power
power
PCI
GND
I
AD(21)
I/O
I
address/data line
V
CC
power
PCI
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
GND
I/O
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
address/data line
PCI
PCI
PCI
PCI
power
power
PCI
GND
I
C/BE(2)
I/O
I
bus command
V
CC
power
PCI
I/O
I/O
I/O
I/O
I/O
I
cycle frame
ꢀrame
IRDY
PCI
initiator ready
PCI
target ready
TRDY
DEVSEL
STOP
GND
PCI
target indicating address decode
target requesting master to stop
PCI
power
power
PCI
GND
I
O
"interrupt" "A" "request"
INTA
V
CC
I
power
PCI
I/O
O
data parity error
PERR
SERR
PAR
PCI
system error
I/O
I/O
I/O
I
PCI
parity (for AD[0:31] and C/BE[0:3])
bus command
C/BE(1)
AD(15)
GND
PCI
PCI
address/data line
power
power
PCI
GND
I
AD(14)
AD(13)
AD(12)
AD(11)
I/O
I/O
I/O
I/O
address/data line
address/data line
address/data line
address/data line
PCI
PCI
PCI
5351 tbl 01
5
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DEFINITIONS (CON’T.)
Pin #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Name
AD(10)
AD(9)
AD(8)
G ND
I/O
I/O
I/O
I/O
I
Bus Name
PCI
Description
address/data line
address/data line
address/data line
PCI
PCI
pow er
pow er
pow er
PCI
V
CC
I
G ND
C/BE(0)
AD(7)
I
I/O
I/O
I
bus command
PCI
address/data line
V
CC
pow er
PCI
AD(6)
AD(5)
AD(4)
G ND
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
PCI
PCI
pow er
pow er
PCI
G ND
I
AD(3)
AD(2)
AD(1)
AD(0)
G ND
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
PCI
PCI
PCI
pow er
pow er
SRAM
G ND
O
O
W rite enable
SR_WE
SR_A13
SR_A8
SR_A9
SR_A11
70
71
72
73
74
O
O
O
O
O
SRAM
SRAM
SRAM
SRAM
SRAM
Address line
Address line
Address line
Address line
O utput Enable control
SR_OE
SR_A10
SR_CS
G ND
75
76
O
O
SRAM
SRAM
Address line
Chip Select
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
I
I
pow er
pow er
pow er
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
pow er
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
G ND
G ND
I
V
CC
I
SR_A12
SR_A7
O
O
O
O
O
O
O
O
O
I
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
SR_A6
SR_A5
SR_A4
SR_A3
SR_A2
SR_A1
SR_A0
G ND
G ND
I
SR_I/O (0)
SR_I/O (1)
SR_I/O (2)
SR_I/O (3)
SR_I/O (4)
I/O
I/O
I/O
I/O
I/O
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
5351 tbl 02
6
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DEFINITIONS (CON’T.)
Pin #
Name
SR_I/O (5)
G ND
I/O
I/O
I
Bus Name
SRAM
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
pow er
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
pow er
SRAM
pow er
SRAM
SRAM
SRAM
SRAM
SRAM
pow er
SRAM
SRAM
SRAM
EPRO M
Description
97
D ata input/output line
98
99
SR_I/O (6)
SR_I/O (7)
SR_I/O (8)
SR_I/O (9)
SR_I/O (10)
G ND
I/O
I/O
I/O
I/O
I/O
I
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
V
CC
I
SR_I/O (11)
SR_I/O (12)
SR_I/O (13)
SR_I/O (14)
SR_I/O (15)
SR_I/O (16)
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
SR_I/O (17)
SR_I/O (18)
SR_I/O (19)
SR_I/O (20)
SR_I/O (21)
SR_I/O (22)
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
SR_I/O (23)
I/O
I
D ata input/output line
V
CC
SR_I/O (24)
SR_I/O (25)
SR_I/O (26)
SR_I/O (27)
SR_I/O (28)
G ND
I/O
I/O
I/O
I/O
I/O
I
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
D ata input/output line
SR_I/O (29)
SR_I/O (30)
SR_1/O (31)
I/O
I/O
I/O
O
D ata input/output line
D ata input/output line
D ata input/output line
EPRO M chip select
E_CE
132
133
134
135
136
137
138
139
140
141
142
143
144
V
CC
I
O
O
I
pow er
EECS
EESCLK
EEDI
EEPRO M
EEPRO M
EEPRO M
EEPRO M
pow er
chip select
clock
Data input
Data output
EEDO
O
I
G ND
SAR_CLK
I
SAR clock input
V
CC
I
pow er
Utility
Utility
Utility
pow er
Utility
UTL_AD(0)
UTL_AD(1)
UTL_AD(2)
G ND
I/O
I/O
I/O
I
address/data bus
address/data bus
address/data bus
UTL_AD(3)
I/O
address/data bus
5351 tbl 03
7
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DEFINITIONS (CON’T.)
Pin #
145
146
147
148
149
150
151
Name
I/O
Bus Name
pow er
Utility
Description
V
CC
I
UTL_AD(4)
UTL_AD(5)
UTL_AD(6)
UTL_AD(7)
G ND
I/O
I/O
I/O
I/O
I
address/data bus
address/data bus
address/data bus
address/data bus
Utility
Utility
Utility
pow er
Utility
O
w rite control
read control
UTL_WR
UTL_RD
UTL_ALE
PHY_RST
PHY_INT
G ND
152
O
Utility
153
154
O
O
Utility
PHY
a ddress latch enable
rest control
155
I
PHY
interrupt input from PHY
156
157
158
I
I
pow er
pow er
Utility
V
CC
O
chip select (0)
chip select (1)
UTL_CS(0)
159
O
Utility
UTL_CS(1)
TxData(0)
TxData(1)
TxData(2)
TxData(3)
G ND
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
O
UTO PIA
UTO PIA
UTO PIA
UTO PIA
pow er
transm it data bit 0
transm it data bit 1
transm it data bit 2
transm it data bit 3
O
O
O
I
TxData(4)
TxData(5)
O
UTO PIA
UTO PIA
pow er
transm it data bit 4
transm it data bit 5
O
V
CC
I
TxData(6)
TxData(7)
G ND
O
UTO PIA
UTO PIA
pow er
transm it data bit 6
transm it data bit 7
O
I
TxSO C
O
UTO PIA
UTO PIA
UTO PIA
UTO PIA
pow er
transmit start of cell
Tx_Ctrl_O ut
Tx_Ctrl_In
TxCLK
O
transmit control outp ut (see Diagram 5)
transm it control inp ut (see Diagram 5)
trans mit data sync clock
I
I/O
G ND
I
RxData(0)
RxData(1)
RxData(2)
RxData(3)
G ND
I
UTO PIA
UTO PIA
UTO PIA
UTO PIA
pow er
receive data bit 0
receive data bit 1
receive data bit 2
receive data bit 3
I
I
I
I
RxData(4)
RxData(5)
RxData(6)
RxData(7)
RxSO C
I
UTO PIA
UTO PIA
UTO PIA
UTO PIA
UTO PIA
UTO PIA
UTO PIA
pow er
receive data bit 4
I
receive data bit 5
I
receive data bit 6
I
receive data bit 7
I
receive start of cell
Rx_Ctrl_O ut
Rx_Ctrl_In
G ND
O
receive control outp ut (see Diagram 5)
receive control inp ut (see Diagram 5)
I
I
I/O
I
RxClk
UTO PIA
UTO PIA
UTO PIA
UTO PIA
rece ive data sync clock
PHY _Clk
TxParity
trans m it sync clock input
O
I
transmit data parity bit
UTO PIA_M ode
UTO PIA M aster/Slave mode select ("0" = M aster ; "1" = Slave)
5351 tbl 04
8
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DEFINITIONS (CON’T.)
Pin #
Name
I/O
Bus Name
PCI
Description
193
O
hot sw ap friendly status LED
HS_LED
HS_Enum
NC
194
O
PCI
hot swap friendly configuration signal
no connection
195
196
197
198
199
---
---
V
V
CC
CC
I
I
pow er
pow er
CLKout
O
I
SA R_Clk divided by 3
PCI
hot swap friendly handle sw itch
test mode c ontrol (see Table 1)
test mode c ontrol (see Table 1)
HS_Handle
Test[1]
Test[0]
G ND
200
201
202
203
I
I
I
I
pow er
pow er
pow er
PCI
system bus reset
bus clock
RST
CLK
GNT
REQ
204
205
206
207
208
I
I
PCI
PCI
bus grant signal from arbiter
bus request
O
I
PCI
V
CC
pow er
pow er
G ND
I
53 51 tb l 0 5
9
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
SS - 0.3
SS - 0.3
SS - 0.3
0
Max.
3.6
Unit
V
V
CC
IN
O UT
Supply Voltage
Input Voltage
V
V
V
V
5 .5
V
V
O utput Voltage
G round Voltage
Storage Temperature
V
CC + 0.3
0
V
V
SS
V
T
stg
-55
+125
°C
53 51 tb l 0 6
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
3.0
0
Max.
Unit
V
VCC
Supply Voltage
Input Voltage
3.6
VI
VCC
V
T
A1
Commerical operating temperature
Industrial operating temperature
Input TTL rise time
0
+70
+85
2
°C
°C
ns
TA2
-40
____
titr
titf
____
Input TTL rall time
2
ns
5351 tbl 07
CLOCKING
Symbol
Parameter
Rate
Min.
77
Max.
80
Unit
MHz
MHz
MHz
MHz
SAR_CLK SAR clock input freq.
PHY_CLK PHY clock input freq.
PCI_CLK PCI clock input freq.
155Mb/s
25Mb/s
155Mb/s
25Mb/s
33MHz
25
80
19.44
3
40
40
0
33.3
MHz
5351 tbl 08
CAPACITANCE
Symbol
Parameter
Condition
except PCI Bus
all outputs
Min.
Max.
Typical
Unit
pF
____
____
____
____
____
CIN
Input Capacitance
4
6
COUT
Cbid
Output Capacitance
8
pF
____
Bi-Directional Capacitance
PCI Bus Input Capacitance
PCI Bus Clock Input Capacitance
PCI Bus ID Select Input Capacitance
all bi-directional pins
10
pF
____
Cinpci
Cclkpci
Cidsel
PCI Bus inputs
10
12
8
pF
____
____
____
5
pF
____
____
pF
5351 tbl 09
10
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
DC OPERATING CONDITIONS
Symbol
Parameter
Low -level TTL input voltage
High-level TTL input voltage
Low -level TTL output voltage
High-level TTL output voltage
Condition
Min.
Max.
Typical
Unit
V
____
____
Vil
-0.7V
(.3)VCC
CC + 0.2V
____
____
____
____
____
____
____
Vih
(.5)VCC
V
V
____
Vol
0.4
V
____
Voh
Iol
V
CC - 0.4V
12
V
____
____
____
Low -level TTL output current:
SR_A(13-0)
V
SS + 0.4V
CC - 0.4V
SS + 0.4V
mA
____
____
Ioh
Iol
High-level TTL output current:
SR_A(13-0)
V
V
-4
6
mA
mA
Low -level TTL output current:
Rx_Ctrl_Out, RxClk, TxSOC,
TxData (7-0), Tx_Ctrl_Out, TxParity,
TxClk, WE, OE, CS,
SR_D31-0
____
____
____
____
____
____
Ioh
Iol
High-level TTL output current:
Rx_Ctrl_O ut, RxClk, TxSoc,
TxData7-0, Tx_Ctrl_Out, TxParity,
TxClk, SR_WE, SR, OE, SR_CS,
SR_I/O(31-0)
V
CC - 0.4V
SS + 0.4V
2.4V
-2
3
mA
mA
mA
uA
Low -level TTL output current:
UTL_AD(7-0), UTL_RD
V
,
UTL_WR, UTL_ALE,
UTL_CS0/1, EESCLK, EECS,
EEDO , PHY_RST
Ioh
High-level TTL output current:
-1
UTL_AD(7-0_, UTL_RD
,
UTL_WR, UTL_ALE,
UTL_CS0/1, EESCLK, EECS,
EEDO , PHY_RST
____
Iil
Input leakage current
V
SS < VIN < Vdd
-1
1
____
____
Ityp
Dynamic Supply Current
300
195
mA
5351 tbl 10
11
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
AC OPERATING CONDITIONS
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Ref. Level
Output Ref. Level
AC Test Load
0 to 3.0V
2ns
1.5V
1.5V
See Figure Below
5351 tbl 11
6
5
4
3
1.5V
50
Ω
∆
tCD
(Typical, ns)
I/O
Z = 50Ω
0
2
1
20 30 50
80 100
Capacitance (pF)
200
5351 drw 05
UTOPIA Master
UTOPIA Slave
77V222
77V222
ATM device
PHY device
TxData
TxData
TxParity
TxSoc
TxData
TxParity
RxData
RxParity
TxParity
TxSoc
RxSoc
RxEnb
RxClav
TxSoc
Tx_Ctrl_Out
Tx_Ctrl_In
Tx_Ctrl_Out
Tx_Ctrl_In
TxEnb
TxClav
TxData
TxSoc
TxEnb
TxClav
RxData
RxSoc
Rx_Ctrl_Out
Rx_Ctrl_In
RxData
RxSoc
RxEnb
RxClav
RxData
RxSoc
Rx_Ctrl_Out
Rx_Ctrl_In
UTOPIA_Clk
UTOPIA_Clk
UTOPIA_Clk
UTOPIA_Clk
Note:
1. Connect a pullup resistor to PHY_CIK (pin 190) when the 77V222 is configured for UTOPIA Slave mode.
5351 drw 06
Diagram 5. UTOPIA Modes
12
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
NANDCHAIN
The NAND Chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly
soldered on a PCB.
All signal pads are linked in a NAND chain, which is enabled by asserting a high, or “1”, on Test[0] (pin 201), and a low,
or "0" on Test[1] (pin 200). Asserting a “1” on the other inputs forces EEDO (pin 136) to “1”. By successively setting the
inputs to “0”, starting at HS_Handle (pin 199) and moving to RST (pin 203), EEDO will toggle with each change.
1. Apply a "1" to Test[0] and a "0" to Test[1].
2. Set all the I/O's in the chain to "0" and EEDO should be a "1".The connection order of the pins in the chain are shown
in the NAND Tree Pin Order table located on the following page.
3. Set HS_Handle to a "0" and the EEDO should be a "0".
4. Leaving HS_Handle at a "1" set HS_Enum to "1" and EEDO should be a "1".
5. Repeat for all remaining I/O's in the NAND chain.
Test[0]
Test[1]
Mode
0
0
0
1
Normal operation.
NAND test. EEDO (pin 136) is the output of the NAND chain w hen
using the NAND test mode.
1
1
0
1
Scan test. EEDI (pin 135) is scan data input, EEDO (pin 136) is
scan data output, and EESCLK (pin 134) is scan clock.
O utput test. All outputs equal EEDI (pin 135).
5351 tbl 12
Table 1. Test Modes
13
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
NAND
Tree Order
Pin
#
NAND Tree Pin
NAND Tree Pin
NAND Tree Pin
NAND Tree Pin
Order
#
Order
#
Order
#
Order
#
1
2
199
194
193
192
191
190
189
187
186
185
184
183
182
181
179
178
177
176
174
173
172
171
169
168
166
165
163
162
161
160
159
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
158
155
154
153
152
151
149
148
147
146
144
142
141
140
138
135
134
133
131
130
129
128
126
125
124
123
122
120
118
117
116
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
115
114
113
111
109
108
107
106
103
102
101
100
99
94
76
75
74
73
72
71
70
69
68
66
65
64
63
62
60
59
58
56
55
51
50
49
48
47
46
45
42
41
40
39
38
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
36
33
32
31
30
29
27
24
23
22
21
20
18
15
14
13
12
11
10
7
95
3
96
4
97
5
98
6
99
7
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
97
96
95
94
93
92
90
89
6
88
5
87
4
86
3
85
2
84
206
205
204
203
83
82
81
79
77
53 51 tbl 13
Table 2. NAND Tree Pin Order
14
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
PCI BUS (SEE FIGURE 1& 2)
Symbol
Parameter
Min.
Max.
Unit
tval
CLK to O utput Signal Valid Delay: AD31-0, C/BE3-0, PAR,
2
11
ns
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
tval(ptp)
ton
CLK to O utput Signal Valid Delay: REQ
2
2
12
ns
ns
_ __ _
Float to Signal Active Delay: AD31-0, C/BE3-0, PAR,
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
_ __ _
toff
tsu
Signal Active to Flo at Delay: AD31-0, C/BE3-0, PAR,
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
28
ns
ns
_ __ _
Input Setup Time to CLK: AD31-0, C/BE3-0, PAR,
7
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR, GNT
_ __ _
_ __ _
tsu(ptp)
th
Input S etup Time to CLK: GNT, (REQ
)
10(12)
0
ns
ns
Input Hold Time from CLK: AD31-0, C/BE3-0, PAR,
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR, GNT
_ __ _
_ __ _
trst-pw r
trst-clk
trst-off
Reset Active Time After Pow er Stable
Reset Active Tim e After CLK Stable
1
ns
ns
ns
100
_ __ _
Reset Active to O utput Float Delay: AD31-0, C/BE3-0, PAR,
40
ꢀRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
_ __ _
_ __ _
thigh
tlow
Clock high time
Clock low time
11
11
ns
ns
53 51 tb l 1 4
15
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
UTOPIA BUS (SEE FIGURE 3)
Symbol
Parameter
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
____
t1
t2
t3
t4
t5
t6
t7
t8
t9
TxClk, RxClk Delay from PHY_CLK
5
TxData(7-0), TxSOC, Tx_Ctrl_Out, TxParity Output Valid from TxClk
Tx_Ctrl_In Setup Time to TxClk
1
10
1
15
____
____
Tx_Ctrl_In Hold Time from TxClk
Rx_Ctrl_Out Output Valid from RxClk
RxData(7-0), RxSOC Setup Time to RxClk
RxData(7-0), RxSOC Hold Time from RxClk
Rx_Ctrl_In Setup Time to RxClk
1
15
____
10
1
____
____
____
10
0
Rx_Ctrl_In Hold Time from TxClk
ns
5351 tbl 15
UTILITY BUS WRITE CYCLE (SEE FIGURE 4)
Symbol
Parameter
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
tw1
UTL_ALE Pulse Width
25
____
tw2
25
UTL_CS0/1 Output Valid to UTL_ALE falling edge
UTL_WR Output Valid from UTL_ALE falling edge
UTL_CS0/1 Pulse Width
____
tw3
80
____
tw4
275
185
245
30
____
____
____
____
____
____
tw5
UTL_WR Pulse Width
tw6
UTL_ALE falling edge to UTL_CS0/1, UTL_WR rising edge
UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge
UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge
UTL_AD(7-0) Data Setup Time to UTL_CS0/1, UTL_WR rising edge
UTL_AD(7-0) Data Hold Time from UTL_CS0/1, UTL_WR rising edge
tw7
tw8
10
tw9
185
10
tw10
ns
5351 tbl 16
UTILITY BUS READ CYCLE (SEE FIGURE 5)
Symbol
Parameter
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
tr1
UTL_ALE Pulse W idth
25
____
tr2
25
UTL_CS0/1 Output Valid to UTL_ALE falling edge
UTL_RD O utput Valid from UTL_ALE falling edge
UTL_CS0/1 Pulse W idth
____
tr3
80
____
tr4
275
185
250
30
____
____
____
____
____
____
____
tr5
UTL_RD Pulse W idth
tr6
UTL_ALE falling edge to UTL_RD rising edge
UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge
UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge
UTL_AD(7-0) D ata Setup Time to UTL_CS0/1 rising edge
UTL_AD(7-0) Data Hold Time from UTL_CS0/1 rising edge
UTL_ALE falling edge to UTL_CS0/1 rising edge
tr7
tr8
10
tr9
80
tr10
tr11
10
225
ns
5351 tbl 17
16
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
SRAM BUS WRITE CYCLE (SEE FIGURE 6)
Symbol
Parameter
Min.
2
Max.
Unit
ns
_ __ _
t1
t2
t3
t4
t5
t6
SR_A(1 3-0) Setup Time to SR_WE falling edge
_ __ _
_ __ _
0
ns
SR_CS falling edge to SR_WE falling edge
25
11
7
ns
SR_CS pulse w idth
_ __ _
_ __ _
_ __ _
SR_I/O (3 1-0) Setup Time to SR_WE rising edge
SR_I/O (31 -0) Hold Time from SR_WE rising edge
ns
ns
10
ns
SR_WE pulse w idth
5351 tbl 18
SRAM BUS READ CYCLE (SEE FIGURE 7)
Symbol
Parameter
Min.
Max.
Unit
_ ___
t1
t2
SR_A(13-0) to SR_I/O (31-0) Valid
15
ns
_ ___
25
ns
SR_OE pulse w idth
53 51 tb l 1 9
Note : SR _I/O (31 - 0 ) Se tup a nd Hold time s are guaranteed by d esig n w hen t1 acce ss time is met.
EPROM (SEE FIGURE 8)
Symbol
Parameter
Min.
Max.
Unit
ns
_ ___
t1
t2
t3
t4
SR_I/O (7 -0) Hold Time from E_CE rising edge
0
_ ___
75
ns
E_CE pulse w idth
_ ___
SR_A(13-0) Change to SR_I/O (7-0) Valid
SR_ A(13-0) pulse w idth
70
ns
_ ___
75
ns
5351 tbl 20
EEPROM (SEE FIGURE 9)
Symbol
Parameter
M in.
100
10
M ax.
Unit
ns
Comments
____
____
____
t1
t2
t3
SAR_CLK to Output Signal Valid Delay: EECS, EEDO, EECLK
EEDI Input Setup Time to SAR_CLK
software controlled
software controlled
ns
EEDI Input Hold Time from SAR_CLK
0
ns
software controlled
5351 tbl 21
17
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tcyc
ton
tval (ptp)
tval
tlow thigh
toff
PCI_CLK(I)
AD31-0(O)
Add
Data0
Data2
Data3
Data1
C/BE3-0(O)
Cmd
BE3-0
tval
toff
FRAME(O)
ton
tval
toff
tval
IRDY(O)
tsu
DEVSEL(I)
tsu
th
tsu
TRDY(I)
REQ(O)
tval(ptp)
tval
ParD0
ton
toff
PAR(O)
ParD3
ParA
ParD1
ParD2
tsu(ptp)
GNT(I)
5351 drw 07
th
Figure 1. The IDT77V222 as a PCI master (illustrates a 4-word write by the IDT77V222 to host memory)
18
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tsu
th
PCI_CLK(1)
Data1
BE3-0
AD31-0(1)
Data0
Data2
ParD1
Data3
ParD2
Add
C/BE3-0(1)
Cmd
tsu
ParA
PAR(1)
ParD3
ParD0
th
tsu
FRAME(1)
th
IRDY(1)
toff
th
toff
DEVSEL(1)
tval,
ton
toff
TRDY(O)
PERR(O)
tval,
ton
SERR(O)
tval,
ton
REQ(1)
REQ(O)
tsu
5351 drw 08
tval
Figure 2. The IDT77V222 as a PCI target
(illustrates a 4-word write operation by the host device driver to the IDT77V222 )
19
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
t1
PHY_C lk(I)
t3
t7
t4
t5
t6
t2
t8
t9
TxC lk,R xClk(O )
TxD ata 7-0(O )
TxSO C (O )
Tx_C trl_O ut(O )
TxParity(O )
(I)
Tx_C trl_In
R x_C trl_O ut(O )
RxData 7-0(I)
R xS O C (I)
Rx_C trl_In(I)
5351 drw 09
Figure 3. UTOPIA Bus Timing
20
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tw11
tw6
tw1
tw7
tw2
tw8
tw3
UTL_ALE(O)
tw4
UTL_CS0/1(O)
tw5
tw10
tw9
UTL_WR(O)
UTL_AD(7-0)(I/O)
(O) Valid Data
Address (O)
5351 drw 10
Figure 4. Utility Bus Write Cycle
tr6
tr11
tr1
tr7
tr2
tr8
tr3
UTL_ALE
tr4
UTL_CS0/1
tr5
tr10
tr9
UTL_RD
Address (O)
(I) Valid Data
UTL_AD7-0
5351 drw 11
Figure 5. Utility Bus Read Cycle
21
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
t1
SR_A(18-0)
t3
t2
SR_CS
t6
t5
t4
SR_WE
SR_I/O(31-0)
5351 drw 12
Figure 6. SRAM Bus Write Cycle Timing
t1
SR_A(18-0)
SR_CS
t2
SR_OE
SR_I/O(31-0)
5351 drw 13
Figure 7. SRAM Bus Read Cycle Timing
t3
t4
SR-A (18-0)
t1
t2
E_CE
Valid Data
SR_I/O(7-0)
5351 drw 14
Figure 8. EPROM Timing
22
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
t1
SAR_CLK
EECS
EECLK
EEDO
EEDI
t3
t2
5351 drw 15
Figure 9. EEPROM Timing
SOFTWARE AND SOFTWARE DRIVERS
Several software vendors have writen IDT77V222 software drivers for various operating systems. Please contact your
local IDT sales representative for a vendor list, or e-mail atmhelp@idt.com.
IDT offers the Sarwin2 demo driver and application suite, which can be used to evaluate the IDT77V222 when used with
a IDT NIC reference or evaluation adapter. It may also be used as a reference for sample source code when developing a
proprietary device driver. Please contact your IDT sales representative or e-mail atmhelp@idt.com to obtain a free cdrom.
NIC Reference and Evaluation Adapters
NIC Reference and Evaluation adapters are available in several form factors. Bill of Materials (BOM) and schematics are
available upon request for each of the NIC adapters. A list of current NIC adapter offerings can be found at www.idt.com.
Note: The Micro ABR SAR User Manual provides a detailed description of the 77V222 operation and registers.
23
IDT77V222155Mb/sATMSegmentation&Reassembly(SAR)Controller
with ABR for the PCI Local Bus
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
ORDERING INFORMATION
NNNNN
A
NNN
A
A
IDT
Device Type
Power
Speed
Package
Process/
Temp. Range
(Blank)
I
Commercial
Industrial
208-pin Plastic Quad Flatpack
PG
155
L
Speed in Mps
Low Power CMOS
77V222 3.3V 155Mbs ATM Segmentation &
Reassembly (SAR) Controller for the
PCI Local Bus
5351 drw 16
Notes:
Refer to PSC-4053 for detailed package drawing.
Refer to errata list for revision history and how to identify revision.
DatasheetDocumentHistory
09/29/99: CreatedNewDocument
01/10/00: Changed VIH from Vcc+0.3 to 5.5V to reflect 5.5V tolerant Inputs.
03/27/00: Corrected pins 173 and 200 in 5351drw03.
04/11/00: Corrected table 5351tbl12.
04/26/00: Added information in Pin Description for TxCLK and RxCLK.
07/11/00: Changed pin names on Package Pinout for pin 77. Corrected pin descriptions for pins 62, 68, 77, 79,
90, 174, 189 and 199. Changed DC Operating conditions for Vil and Vih. Updated AC Test Condi-
tions table and drawing. Updated UTOPIA Bus, Utility Bus Read and Write, SRAM Bus Read and
Write, and EEPROM timing diagrams and tables. Added information on NAND Chain. Changed data
sheet from Advanced to Preliminary.
08/25/00: Updated UTOPIA Bus timing table.
10/06/00: Corrected Utopia Slave mode drawing 5351drw06 and added Max Cout parameter in Table
5350tbl09. Additional changes made to reflect Rev B silicon include changed Test[1] from pin 201 to
pin 200, changed Test[0] from pin 200 to pin 201, changed bit order for Test[1:0] in Test Mode table
5351tbl12, removed PCI timing violation for "th" hold time.
01/16/01: Changed from Preliminary to Final data sheet. Added to and rearranged the Features list.
IntegratedDeviceTechnology,Inc.reservestherighttomakechangestothespecificationsinthisdatasheetinordertoimprovedesignorperformanceandtosupplythebestpossibleproduct.
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