IDT77V7111PF [IDT]
Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64, 14 X 14 MM, TQFP-64;
| 型号： | IDT77V7111PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64, 14 X 14 MM, TQFP-64 |
| 文件： | 总12页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
IDT77V7101
GIGABIT ETHERNET
SERDES TRANSCEIVER
Features
Applications
◆
◆
IEEE802.3zGigabitEthernetcompatible
IEEE802.3zGigabitmedia interfaces:
◆
1.25 Gbps full duplex transmission and reception in a single IC
Opticalinterface throughfibermodule
10-bit parallel TX and RX interfaces based on EIA/TIA X3T11
SignalDetect,internalorexternal
Code GroupRealignmentwithDisable
InternalLoopbackmode
62.5MHz recovered clock
Low power 3.3V CMOS
– 1000BASE-LXOptical
· – 1000BASE-SX Optical
◆
◆
◆
Provides the PMAfunctionofthe PHY
Highspeedcustomserialinterface
Backplane seriallink
Bus extension
◆
◆
◆
◆
◆
◆
◆
◆
Description
◆
Fewexternalcomponents required
64-pin10mmand14mmpackages
TheIDT77V7101is amonolithic1.25Gigabits persecond(Gbps)
Ethernet Serializer/Deserializer (SerDes) Transceiver. It is de-
signedtoprovide the PhysicalMediumAttachment(PMA)portionof
the IEEE 802.3z PHY layer.
◆
◆
Pin-outs are compatible withindustrystandarddevices
IDT77V7101/7111
PMA CHIP
PCS CHIP
TXER
TXEN
TXD[7:0]
GTX_CLK
COL
TRANSMIT
BLOCK
TXCG[9:0]
TXP
TXN
TERMINATION
NETWORK
TRANSMIT
SECTION
TCLK
RPT
LEDs
RESET
CRS
MDIO
MDC
e
c
M
a
f
CONTROL
EWRAP
SDT
I
r
D
t
E
M
LINK
CONFIG
I
RXP
RXN
I
TERMINATION
NETWORK
M
RECEIVE
SECTION
G
COMDET
ENCDET
RXER
RXDV
RXD[7:0]
RXCLK
RECEIVE
BLOCK
RCLK[1:0]
RXCG[9:0]
7101 drw 01
Figure 1. Typical Application Block Diagram
APRIL 2000
1
DSC-7101-1
©2000IntegratedDeviceTechnology,Inc.
IDT77V7101
Gigabit Ethernet Serdes Transceiver
Datasheet
b
TXP
TXN
TX SERIAL DATA
TXCG[9:0]
DRIVER
125M Hz
TCLK
ENABLEO P
TX CLOCK
1,250M Hz
CLOCK
M ULTIPLIER
PLL
PLLCAP1
PLLCAP2
SDTSEL
SDT
SIGNAL
DETECT
EW RAP
ENABLE
EQUSEL
RX CLO CK
DATA
RECO VERY
&
1
0
RE-TIM ED RX
SERIAL DATA
RXP
RXN
RXCG [9:0]
RX
RX SERIAL DATA
EQUALIZER
RECO VERED
RX CLOCK
1,250M Hz
125M Hz
RX CLO CK
DIVIDER
RCLK[1]
RCLK[0]
62.5M Hz (V7101)
125M Hz (V7111)
COM DET
ENDET
COM M A
DETECT
RE-SYNC
Figure 2. IDT77V7101 Internal Block Diagram
Transmit Clock (TCLK)
FunctionalDescription
The user-supplied 125MHz transmit reference clock (TCLK) is
usedforseveralfunctions.As thetransmitcodegroupclock,its rising
edgesdirectlystrobethe10-bitinputdatalatchtosamplethetransmit
code groupbus, TXCG[9:0]. Therefore, its edges mustbe properly
alignedtothe incomingparalleltransmitdata.
Overview
Figure 1 shows a block diagram of a typical application. The
parallelinterfaceconnectstoaPhysicalCodingSublayer(PCS)chip.
The serialinputs andoutputs connectdirectlytoa fiberopticmodule
foropticaltransmission.
TCLKalsoservesasthefrequencyreferencefortheTransmitPLL
ClockMultiplier,whichuses ittosynthesizetheinternalclocksignals
necessary for 1.25 Gbps signaling.
Figure2shows aninternalblockdiagramoftheIDT77V7101.The
TXCG[9:0] inputs receive parallel 10-bit transmit code groups,
alreadyencodedin8B/10BformatbythePCSchip.Thecodegroups
are latched on the rising edges of the incoming 125MHz reference
clock(TCLK).Thentheyare serialized,andthe bitstreamis retimed
by an internal PLL that multiplies TCLK up to 1250MHz. This data
streamistransmittedthroughPECLdriversintothecableorfiberoptic
module.
The 77V7101receives serialdata fromthe fiberopticmodule. It
deserializes the data into10-bitreceive code groups,andrecovers
a receive clock(RCLK)fromthe data stream.RCLKis usedtoclock-
out the receive code groups to the PCS chip.
RCLK is output at 62.5MHz in two complementary phases as
RCLK[0]andRCLK[1]. RCLK[0]andRCLK[1]are usedtoclockout
alternatingcode groups.
ASignalDetectI/Opinhas beenprovided. Forfiberopticmedia,
itcanbe configuredas aninput,allowingthe fibermodule toperform
signaldetection.
Transmit Data Path
Itis assumedthattheoriginal8-bituserdatatobetransmittedhas
alreadybeen8B/10B-encodedinto10-bittransmitcode groups by
external PCS logic before being sent to the IDT77V7101 for
transmission.TheincomingcodegroupsarereceivedontheTransmit
Code Group bus, TXCG[9:0], and are sampled on the rising edges
ofTCLKbytheinputdatalatch.Figure6showsthetimingrelationship
between the clock and the parallel data, and the “AC Electrical
Characteristics” section shows the timing requirements for these
signals.
Theparalleltransmitdataissenttotheparallel-to-serialconverter.
This uses the internalclocksignals synthesizedbythe transmitPLL
toconvertthe 10-bittransmitdata fromparalleltoserialformat,and
to retime each bit at 1250MHz. The least significant bit TXCG[0] is
2
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
eachoccurrenceofacomma+causesrealignmentofthebitpositions
ofthe receivedcomma+code grouptomatchthe standard8B/10B
format.Realignmentmaybe achievedbydroppingbits fromthe data
streamwhennecessary.Comma+charactersarealwaysclockedout
by the rising edge of RCLK[1]. In the case of the 77V7101 this may
entailstretchingRCLK[1:0]halfacycle(nominally8ns).Subsequent
code groups retain this bit and clock alignment unless shifted by
errors.IfENDET=0,realignmentandclockstretchingare disabled.
The COMDEToutputis anindicatorforthe detectionofcomma+
characters. When ENDET is high and a comma+ character is
detected,COMDETwillgohighforhalfanRCLKperiod,followingthe
rising edge of RCLK[0]. Otherwise, it will remain low.
transmittedfirst.
The TransmitLine Drivertransmits the serialdata indifferential
formontothetransmithalfofthechosenmedium.TheLineDrivercan
connectdirectlytocoppermediasuchas150Ωtwinaxcable(through
DC-blockingcapacitors),orthrougha fiberoptictransceivermodule
tofiberopticcable.
TheLineDriveris asource-followerthatprovides avoltage-mode
differentialPECL-level-compatibleoutput.Ithas adifferentialsource
impedanceofapproximately30Ω.ENABLEOPmustbeheldtoalogic
high level for normal operation. When ENABLEOP is held low, the
Line Driver output is set to a high impedance state.
Refertothe“MediumAttachment”sectionbelowformoreinformation
on connecting the line driver to various media.
Proper operation of COMDET, RCLK[1:0], and the code group
alignmentfunctionrequires thatcomma+characters notbereceived
back-to-back, as perstandard8B/10Bencoding.
ReceiveEqualization
The77V7101/7111hasanequalizationcircuitatthereceiverinput
tocompensatethesignaldistortioncausedbyunequalizedcable.For
operationovershortcables orlonginternallyequalizedcables,the
equalizer can be either enabled or disabled.
Usersmaywishtodisableitincaseswherecrosstalkorreflections
rather than electrical line length are the major causes of signal
impairment, such as when the serial link runs through a crowded
backplaneorpoorlymatchedconnectorratherthanalongunequalized
cable. Doingsocanimprovethetoleranceoftheseimpairments.The
equalizercanalsobe disabledforthe same reasonwheninterfacing
tofiberoptictransceivers ortoshortorinternally-equalizedcables.
Signal Detect
The Signal Detect pin SDT is a bi-directional pin controlled by
SDTSEL.WhenSTDSELis high,SDTis anoutputthatremains high
whenthereceivesignalamplitudeexceedstheSignalDetectthreshold
VSD, and receive data will be output normally at RXCG[9:0]. (Note
thatthisdoesnotindicatethatacompliant1000BASE-Xsignalisbeing
received.)Areceivesignalamplitudebelowthethresholdcauses the
SDToutputtoremainlow,andtheRXCG[9:0]outputs toallbeforced
to logic 1. This helps prevent the generation of random data at the
receiveroutputs inthe absence ofvalidincomingdata.
When SDTSEL is low, SDT becomes a PECL input to allow
external devices such as fiber optic modules to perform the Signal
Detectfunction.Signaldetectionshouldcausetheexternaldeviceto
drive SDTtoPECLlogic1,while insufficientsignalamplitude should
drive SDT to PECL logic 0. As before, a logic 0 at SDT will cause
RXCG[9:0] outputs to all be forced to logic 1.
ClockRecovery
After the serial input signal has passed through the front end’s
equalizingamplifier,a receive clockmustbe recoveredwithwhichto
sample the incomingdata stream.Clockrecoveryis automatic,with
no user intervention such as PLL training necessary. The internal
Receive PLLlocks the phase ofits VCOtothatofthe incomingdata
toproduce a bit-clock.This bit-clockis thendivideddowntobecome
the internal125MHzcode-groupclock(ICLK).Finally,the recovered
receive clockis outputas complementarysignals (180°outofphase
witheachother)atRCLK[0]andRCLK[1]at62.5MHzinthe77V7101,
and at 125MHz in the 77V7111. In the 77V7101, the 62.5MHz
RCLK[0] and RCLK[1] signals are used to clock out alternating
125MHzcodegroups.Inthe77V7111,125MHzRCLK[1]orRCLK[0]
signals provide rising-edge or falling-edge clocking of all receive
code groups, respectively.
InternalLoopback
Loopbackmodepermitstestingmostoftheinternalcircuitrywithout
usinganexternalmedium,andis enabledbyholdingEWRAPhigh.
Transmit code groups sent to the TXCG[9:0] inputs are processed
normally by the transmit circuitry, then looped back through the
receive circuitrytothe RXCG[9:0]outputs as iftheywere incoming
serialdata.Attheloopbackpoint,transmitserialdatais divertedfrom
before the Line Driver,andreplaces the equalizeroutputas the input
tothe clockanddata recoverycircuits.Nearlyallthe internalcircuits
exceptforthe Line DriverandReceive Equalizerare exercised,with
allinternalSerializer,Deserializer,andclockfunctions occurringat
theirnormalrates.
DataRecovery
Following equalization and buffering, the receive serial data
stream is retimed by the recovered bit-clock, then converted from
serialtoparallelformusingbothbit-andcode-group-clocks.Parallel
receive data is clocked into the output data latch by the internal
125MHzcode-group-clock, andoutputatthe Receive Code Group
bus, RXCG[9:0]. RCLK[1:0] are used to clock out the data from
RXCG[9:0] as described in “Clock Recovery” above.
Loopbackmode holds the Line DriveroutputatPECLlogic1.For
normaloperation, EWRAP mustbe heldlow.
MediumAttachment
(Serial Interface)
Figure 3shows a typicalmethodofconnectingeitherfiberoptic
links.Inthis case 150Ω bias resistors are connectedfromTXPand
TXNtoground.AC-couplingoftransmitteroutputtocableis used,as
required by IEEE 802.3z. The optional series resistors RSER may
beaddedtohelpabsorbreflectionsduetomismatchedloads.Typical
Code Group Alignment
Acodegroupalignmentfunctiondetects thepresenceofcomma+
characters (0011111xxx) in the receive data stream. If ENDET=1,
3
6.42
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
values range from0-50Ω.The amountofoutputattenuationdesired
shouldalsobeconsideredwhensettingthesevalues.Loadterminations,
transmission lines (including traces) and connectors should be
selectedordesignedtohave matchingimpedances.
VCC (5V)
0.1uF
FIBER OPTIC
LINK
68.1
68.1
0.01uF
0.01uF
150
0.01uF
TXP
TXN
TD+
TD-
RD+
RD-
RXP
RXN
100
0.01uF
150
191
191
270
270
100 OHM DIFFERENTIAL
TRACE PAIRS
7101 drw 05
Figure 3. Typical 1000BASE-LX/SX Medium Attachment (Fiber Optic half link shown)
NOTES:
1. The optional series RSER resistors may be added to help absorb reflections due to mismatched loads. Typical values range from 0-50Ω, depending on the characteristic
impedance of the transmission lines and the amount of acceptable attenuation.
2. Termination circuits at the fiber optic module are typical values for a module running on a 5V supply, with 100Ω differential impedance at each load end. Modules
with other supply voltages may require adjustment of these circuit values to achieve the recommended input voltages. Follow fiber optic module manufacturer’s
recommendations for setting input voltages, receiver bias resistors, and termination impedance.
4
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
64
61 60 59
56 55 54
51 50
53 52 49
63 62
58 57
oPin 1 Index
1
SDTSEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
2
COMDET
GND
TXCG0
TXCG1
TXCG2
VDD
3
4
RXCG0
RXCG1
RXCG2
VDD
5
6
TXCG3
TXCG4
TXCG5
TXCG6
VDD
7
8
RXCG3
RXCG4
9
IDT77V71x1
10
11
12
13
14
15
16
RXCG5
RXCG6
VDD
TXCG7
TXCG8
TXCG9
RXCG7
RXCG8
RXCG9
GND
GND
GND
PLLCAP1
19 20
24 25
29 30
26 27 28 31 32
17 18
21 22 23
7101 drw 06
Figure 4. Pin Assignments
5
6.42
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
PinDescriptions
Transmit-SideSignals
Pin #
Name
Type
Description
22
TCLK
TTL Input
The transmit code group clock, 1/10 the serial baud rate, whose rising edges are used
to sample the incoming transmit code groups (TXCG[9:0]). TCLK is also the reference
clock used by the transmit PLL to synthesize the high-speed serial data clock.
13,12,11,9,
8,7,6,4,3,2
TXCG[9:0]
TXP,TXN
TTL Inputs
HS Output
The PMA chip's transmit code group input port, accepting 10-bit parallel transmit data
already encoded in 8B/10B format. This bus is clocked into the chip on the rising edge
of TCLK. TXCG[0] is the least significant bit and the first to be transmitted.
The high-speed + and - serial data differential outputs to the cable or fiber optic
transmitter. For output = "1", TXP > TXN.
62,61
7101 tbl 01
Receive-SideSignals
Pin #
Name
Type
Description
54, 52
RXP, RXN
HS Input
The high-speed serial data differential inputs from the twisted-pair cable or fiber optic
receiver. For input = "1", RXP > RXN.
34,35,36,38,
39,40,41,43,
44,45
RXCG[9:0]
TTL Outputs
TTL Outputs
The PMA chip's receive code group output port, presenting 10-bit receive data on
alternate rising edges of RCLK[0] and RCLK[1] (V7101), or on all rising edges of
RCLK[1] (V7111). If ENCDET = 1, comma + code groups are realigned and forced to be
clocked by RCLK[1]. RXCG[9:0] are forced high when SDT = 0. RXCG[0] is the least
significant bit and the first to be received.
30
31
RCLK1
RCKL0
The complementary receive clock outputs, recivered from the received serial data. The
V7101 RCLK[1:0] outputs are 1/20 the serial baud rate, and clock-out alternate receive
code groups from RXCG[9:0] on their rising edges. If ENCDET= 1. RCLK[1] clocks all
comma + characters. The V7111 RCLK[1:0] outputs are 1/10 the serial baud rate, and
RCLK[1] provides all positive-edge clocking.
7101 tbl 02
6
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
ControlSignals
Pin #
Name
Type
Description
47
COMDET
TTL Output
When ENCDET = 1 and a comma + character is detected in the receive bit stream.
COMDET will go high for half an RCLK period in the V7101, or one clock period in the
V7111, following the rising edge of RCLK[0].
59
24
49
ENABLEOP
ENCDET
EQUSEL
TTL Input
TTL Input
TTL Input
A high level on this pin is required to activate the Line Driver, which otherwise remains in
a high impedance state. An internal 50k pull-up resistor prevents "floating". Hold
ENABLEOP high for normal operation.
A logic 1 input enables code group realignment on comma + reception. A logic 0 input
keeps current word alignment and disables COMDET. An internal 50k pull-up resistor
prevents "floating".
Mode Select input for Equalizer. If EQUSEL = 0, equalization is on.
If EQUSEL = 1, equalization is off. Equalization may be turned on for all cable lengths.
An internal 50k pull-down resistor prevents "floating". Hold EQUSEL low for normal
operation.
19
EWRAP
TTL Input
Analog
"Enable Wrap," this signal must be at a logic low level for normal operation. A high logic
level forces the transmit data to be looped back from TXCG[9:0] to RXCG[9:0],
exercising most of the internal circuitry. An internal 50k pull-down resistor prevents
"floating". Hold EWRAP low for normal operation.
16
17
PLLCAP1
PLLCAP2
A .001µF capacitor is connected between these pins to set the loop filter characteristics
of the transmit PLL.
26
SDT
Bi-directional
PECL Input
TTL Output
Signal Detect, with direction controlled by SDTSEL. If SDTSEL is high, SDT is a TTL
output, where a logic 1 indicates that the receiver input level is above the internal "signal
detect" threshold. if SDTSEL is low, SDTbecomes a PECL input, enabling signal
detection by external devices such as fiber optic transceivers. In any case, a logic 0 at
SDT forces all RXCG[9:0] signals high, while a logic 1 allows normal operaiton.
48
SDTSEL
TTL Input
Signal Detect direction control. If SDTSEL = 0, SDT is a PECL level input. If SDTSEL = 1,
SDT is a TTL output. (See SDT description above.) An internal 50k pull-up resistor
prevents "floating". Hold SDTSEL high for normal operation.
23
27
UNUSED
UNUSED
TTL Input
Output`
This pin must be connected to VCC.
This pin should be left unconnected.
7101 tbl 03
PowerSupplyPins
Pin #
Name
Type
Description
5,10,18,20,
28,29,37,42,
50,53,55,57,
60,63
VDD
Power
Positive supply pins.
1,14,15,21,
25,32,33,46,
51,56,58,64
GND
Power
Ground supply pins.
7101 tbl 04
7
6.42
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
ElectricalSpecifications
(1)
AbsoluteMaximumRatings
Parameter
Min.
-0.5
-0.5
Max.
+5
Unit
V
DC Supply Voltage (VDD)
Terminal Voltage with respect to GND
Terminal Voltage with respect to VDD
Storage Temperature Range
+5
V
+0.5
+150°
V
-40°
Celsius
7101 tbl 05
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
RecommendedOperatingConditions
Symbol
Parameter
Min.
3.15
0
Typ.
Max.
3.45
70
Unit
VDD
DC supply voltage
3.3
V
TA
Ambient Temperature
°C
7101 tbl 06
DC Electrical Characteristics (Includes all I/O pins except TXP, TXN, RXP, RXN)
Symbol
Parameter
Test Conditions(1)
Min.
Typ.
Max.
Unit
(2)
IL
DD
0.80
(2)
V
IL, TTL
TTL Input Low Voltage
PECL Inp ut Hig h Vo ltage
PECL Inp ut Low Voltage
Inp ut Hig h Current
-0.3
V
(3)
V
IL, PECL
SDTSEL is low
SDTSEL is low
DD = 3.45V, VIN = 2.4V
DD
DD = 3.15V, IOUT = -400
DD = 3.15V, IOUT = 1mA
V
DD - 1.165
V
DD + 0.5
V
(3)
V
IL, PECL
-0.3
V
DD - 1.475
V
I
IH
V
40
µ
µ
A
A
IL
2.2
0
V
OH
Output High Voltage
Output Low Voltage
Input Cap acitance
V
µ
A
V
DD
V
V
OL
V
0.5
4
V
pF
mA
V
C
IH
I
DD
Transce iver VDD Supply Curre nt
DC supply voltage
T
A
= 25
°
180
3.3
V
DD
3.15
3.45
D
7101 tbl 07
NOTE:
1. Test conditions are Recommended Operating Conditions unless otherwise noted.
2. Not for SDT.
3. For SDT only, when SDTSEL is logic low.
8
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
AC Electrical Characteristics
Symbol
Parameter
Test Conditions(1)
Min.
Typ.
Max.
Unit
MBaud
MHz
ppm
%
(2)
BD
f
Serial Baud Rate
1000
1250
1360
REF
BD
f /10
f
TCLK Reference Frequency
TCLK Frequency Tolerance
TCLK Duty Cycle
TOL
f
-100
40
+100
60
DC, TC
t
JTT
t
TCLK Jitter
40
ps RMS
ns
R, TC
t
TCLK Rise Time
0.8V to 2.0V
2.0V to 0.8V
0.7
0.7
2.4
2.4
F, TC
t
TCLK Fall Time
ns
BD
RCLK Frequency (77V7101)
RCLK Frequency (77V7111)
RCLK Rise Time
f /20
MHz
MHz
ns
RCLK
f
BD
f /10
R, RC
t
L
0.8V to 2.0V, C = 10pF
0.7
0.7
40
2.4
2.4
60
F, RC
t
L
RCLK Fall Time
0.8V to 2.0V, C = 10pF
ns
DC, RC
t
L
RCLK Duty Cycle
1.4V to 1.4V, C = 10pF
%
A-B
t
0
1
L
RCLK to RCLK rising edge skew
(77V7101)
1.4V to 1.4V, C = 10pF
7.5
8.5
ns
(3)
R, RX
L
t
RXCG Rise Time
0.8V to 2.0V, C = 10pF
0.7
0.7
2.5
1.5
0.7
0.7
2.0
1.0
1
1
ns
(3)
F, RX
L
t
RXCG Fall Time
0.8V to 2.0V, C = 10pF
ns
SU, RX
L
t
RXCG Setup Time to rising RCLK
RXCG Hold Time from rising RCLK
TXCG Rise Time
{0.8,2.0}V to 1.4V, C = 10pF
ns
HO, RX
L
t
1.4V to {0.8,2.0}V, C = 10pF
ns
(3)
R, TX
t
0.8V to 2.0V
ns
(3)
F, TX
t
TXCG Fall Time
0.8V to 2.0V
ns
SU, TX
t
TXCG Setup Time to rising TCLK
TXCG Hold Time to rising TCLK
Transmit Latency
{0.8,2.0}V to 1.4V
1.4V to {0.8,2.0}V
ns
ns
HO, TX
t
(4)
LAT, TX
t
16
34
ns
(5)
LAT, RX
t
Receiver Latency
ns
SD
V
Signal Detect Threshold
HS Input Differential Voltage
HS Output Differential Voltage
HS Output Differential Off Voltage
HS Output Differential Rise Time
HS Output Differential Fall Time
Total Transmit Jiffer
200
200
100
mV pk-pk
mV pk-pk
mV pk-pk
mV pk-pk
ps
IHS
V
2000
2000
170
OHS
V
1100
OHS, OFF
V
R, HS
t
85
85
327
F, HS
t
327
ps
(6)
TOTAL
J
192
ps pk-pk
7101 tbl 08
NOTES:
1. Test conditions are Recommended Operating Conditions unless otherwise noted.
2. 1250 Mbaud ±100ppm is the rate specified by IEEE 802.3z.
3. IEEE does not specify code group maximum rise and fall times, but TXCG and RXCG inputs and outputs must meet the required setup and hold times.
4. Transmitter latency is the time from the positive edge of TCLK that clocks in a particular transmit code group to the differential first edge of the first bit of that code
group to be transmitted at TXP/N. Reference levels are 1.4V for TCLK, and zero-crossing for AC-coupled TXP-TXN.
5. Receiver latency is the time from the differential first edge of the first bit of a particular code group received at RXP/N to the positive edge of the RCLK output
(RCLK0 or RCLK1) that clocks out that code group. Reference levels are 1.4V for RCLK and zero-crossing for AC-coupled RXP-RXN.
6. Total jitter at this component level is specified by IEEE 802.3z at TP1, as they define test points. See subclauses 38.5, 38.6.8-9, and 39.3.3 for system level
specifications and measurement methods.
9
6.42
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
TimingDiagrams
1.4V
TCLK
tSU, TX
2.0V
VALID
DATA
VALID
DATA
TXCG[9:0]
0.8V
tHO, TX
7101 drw 07
Figure 5. Transmit Parallel Interface Timing Diagram
1.4V
RCLK[1]
tSU, RX
2.0V
COMMA+
RXCG[9:0]
CODE GROUP
0.8V
2.0V
tHO, RX
COMDET
0.8V
tSU, RX
1.4V
RCLK[0]
7101 drw 08
t A-B
Figure 6. Receive Parallel Interface Timing Diagram (V7101)
1.4V
2.0V
RCLK[1]
tSU, RX
COMMA+
RXCG[9:0]
COMDET
CODE GROUP
0.8V
2.0V
tHO, RX
0.8V
1.4V
RCLK[0]
7101 drw 09
Figure 7. Receive Parallel Interface Timing Diagram (V7111)
10
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
PackageDimensions
Draft Angle = 11° -13°
64
A2
1
A1
.
e
0.20 Rad Typ.
64-Pin
TQFP
PP64
or
E1
E
PN64
0.20 Rad Typ.
4° ± 4°
A
D1
D
7101 drw 10
L
b
PP64
PN64
SYMBOL
MIN.
NOM.
MAX.
1.60
0.15
MIN.
NOM.
MAX.
____
____
____
____
A
1.60
0.15
A1
0.05
0.10
1.40
0.05
0.10
1.40
A2
1.35
1.45
1.35
1.45
____
____
____
____
D
12.00
10.00
12.00
16.00
14.00
16.00
____
____
____
____
____
____
____
____
____
____
____
____
D1
E
E1
10.00
14.00
____
____
L
0.45
0.75
0.45
0.75
____
____
____
____
e
0.50
0.22
0.80
0.37
b
0.17
0.27
0.30
0.45
7101 tbl 09
Dimensions are in millimeters
Amorecomprehensivepackageoutlinedrawingis availablefromtheIDTwebsite.
11
6.42
IDT77V7101
Datasheet
Gigabit Ethernet Serdes Transceiver
OrderingInformation
IDT
77
V
7
1
0
1
T
,
Device Supply Network Speed Option Ports
Package
Type Voltage
Type
77 = Networking Product
V = 3.3V supply
7 = Ethernet
,
1 = 1.25 Gbit/s
0 = Standard 62.5 MHz RCLK
1 = Optional 125 MHz RCLK
1 = 1-port device
TF = 10x10mm TQFP PP64
PF = 14x14mm TQFP PN64
CORPORATE HEADQUARTERS
for SALES:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
12
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