IDT79RV3041-33J [IDT]
RISC Microprocessor, 32-Bit, 33MHz, CMOS, PQCC84, CAVITY DOWN, PLASTIC, LCC-84;
| 型号： | IDT79RV3041-33J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISC Microprocessor, 32-Bit, 33MHz, CMOS, PQCC84, CAVITY DOWN, PLASTIC, LCC-84 时钟 外围集成电路 装置 |
| 文件： | 总34页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79R3041™
INTEGRATED RISController™ FOR
LOW-COST SYSTEMS
IDT79R3041
IDT79RV3041
Integrated Device Technology, Inc.
• Double-frequency clock input
• 16.67MHz, 20MHz, 25MHz and 33MHz operation
• 20MIPS at 25MHz
• Low cost 84-pin PLCC packaging
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-word read buffer supports burst or simple block
reads
FEATURES:
• Instruction set compatible with IDT79R3000A
and RISController Family MIPS RISC CPUs
• High level of integration minimizes system cost
— RISC CPU
— Multiply/divide unit
— Instruction Cache
— Data Cache
— Programmable bus interface
• On-chip DMA arbiter
• On-chip 24-bit timer
• Boot from 8-bit, 16-bit, or 32-bit wide PROMs
• Pin-andsoftware-compatiblefamilyincludesR3041,R3051,
R3052™, and R3081™
• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point emulation software
— Page Description Languages
— Programmable port width support
• On-chip instruction and data caches
— 2KB of Instruction Cache
— 512B of Data Cache
• Flexible bus interface allows simple, low-cost designs
— Superset pin-compatible with RISController
— Adds programmable port width interface
(8-, 16-, and 32-bit memory sub-regions)
— Adds programmable bus interface timing support
(Extended address hold, Bus turn around time,
Read/write masks)
SBrCond(3:2)
Clock
Generator
Unit
Master Pipeline Control
ClkIn
System Control
Coprocessor
Integer
CPU Core
Int(5:3), SInt(2:0)
Exception/Control
Registers
General Registers
(32 x 32)
ALU
Shifter
Bus Interface
Registers
PortSize
Register
Counter
Registers
Mult/Div Unit
TC
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
32
Instruction
Cache
2kB
Data
Cache
512B
Data Bus
R3051 Superset
Bus Interface Unit
4-deep
Write
Buffer
4-deep
DMA
BIU
Control
Read
Arbiter
Buffer
Data
Unpack
Unit
Data
Pack
Unit
Timing/ Interface
Control
Address/
Data
DMA Rd/Wr SysClk
2905 drw 01
Ctrl
Ctrl
Figure 1. R3041 Block Diagram
RISController, R3041, R3051, R3052, R3081, ORION, IDT/sim, and IDT/kit are trademarks, and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 1996
©1996 Integrated Device Technology, Inc.
DSC-2905/5
1
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
able with the RISController family, by dramatically lowering
the cost of using the MIPS architecture. The R3041 is de-
signed to achieve minimal system and components cost, yet
maintain the high-performance inherent in the MIPS architec-
ture. The R3041 also maintains pin and software compatibility
with the RISController and R3081.
The RISController family offers a variety of price/perfor-
mance features in a pin-compatible, software compatible
family. Table 1 provides an overview of the current members
of the RISController family. Note that the R3051, R3052, and
R3081 are also available in pin-compatible versions that
include a full-function memory management unit, including
64-entry TLB. The R3051/2 and R3081 are described in
separate manuals and data sheets.
INTRODUCTION
The IDT RISController family is a series of high-perfor-
mance 32-bit microprocessors featuring a high-level of inte-
gration, and targeted to high-performance but cost sensitive
embedded processing applications. The RISController family
is designed to bring the high-performance inherent in the
MIPS RISC architecture into low-cost, simplified, power sen-
sitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, theRISControllerfamilyisabletooffer35MIPS
of integer performance at 40MHz without requiring external
SRAM or caches.
Figure 1 shows a block level representation of the func-
tionalunitswithintheR3041. TheR3041canbeviewedasthe
embodiment of a discrete solution built around the R3000A.
By integrating this functionality on a single chip, dramatic cost
and power reductions are achieved.
Further, the RISController family brings dramatic power
reductiontotheseembeddedapplications, allowingtheuseof
low-cost packaging. Thus, the RISController family allows
customer applications to bring maximum performance at
minimum cost.
An overview of these blocks is presented here, followed
with detailed information on each block.
TheR3041extendstherangeofprice/performanceachiev-
Device
Name
Instruction
Cache
Data
Cache
Floating
Point
Bus
Options
R3051
R3052
4kB
8kB
2kB
2kB
Software Emulation
Software Emulation
Mux’ed A/D
Mux’ed A/D
R3071
R3081
16kB
or 8kB
4kB
or 8kB
On-chip Hardware
1/2 frequency bus option
R3041
2kB
512B
Software Emulation
8-, 16-, and 32-bit port width support
Programmable timing support
2905 tbl 01
Table 1. Pin-Compatible RISController Family
CPU Core
The execution engine of the RISController family uses a
five-stage pipeline to achieve close to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions concur-
rently(invariouspipelinestages).Thefivepartsofthepipeline
are the Instruction Fetch, Read register, ALU execution,
Memory, and Write Back stages. Figure 2 shows the
concurrency achieved by the RISController family pipeline.
The CPU core is a full 32-bit RISC integer execution
engine, capableofsustainingclosetoasinglecycleexecution
rate. The CPU core contains a five stage pipeline, and 32
orthogonal 32-bit registers. The RISController family imple-
ments the MIPS-I Instruction Set Architecture (ISA). In fact,
the execution engine of the R3041 is the same as the
execution engine of the R3000A. Thus, the R3041 is binary
compatible with those CPU engines, as well as compatible
with other members of the RISController family.
I#1
IF
RD ALU MEM WB
I#2
IF
RD ALU MEM WB
I#3
IF
RD ALU MEM WB
I#4
IF
RD ALU MEM WB
I#5
IF
RD ALU MEM WB
Current
CPU
Cycle
2905 drw 02
Figure 2. RISController Family 5-Stage Pipeline
2
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
System Control Co-Processor
dress decoding, or in other system specific forms. In systems
which do not wish to implement memory protection, and wish
to have the kernel and user tasks operate out of a single
unified memory space, upper address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.
TheR3041addsadditionalresourcesintotheon-chipCP0.
These resources are detailed in the R3041 User's Manual.
They allow kernel software to directly control activity of the
processor internal resources and bus interface, and include:
• Cache Configuration Register: This register controls the
data cache block size and miss refill algorithm.
• Bus Control Register: This register controls the behavior
of the various bus interface signals.
• Count and Compare Registers: Together, these two
registers implement a programmable 24-bit timer, which
can be used for DRAM refresh or as a general purpose
timer.
The R3041 also integrates on-chip a System Control Co-
processor, CP0. CP0 manages the exception handling capa-
bility of the R3041, the virtual to physical address mapping of
the R3041, and the programmable bus interface capabilities
of the R3041. These topics are discussed in subsequent
sections.
TheR3041doesnotincludetheoptionalTLBfoundinother
membersoftheRISControllerfamily,butinsteadperformsthe
same virtual to physical address mapping of the base version
of the RISController family. These devices still support
distinct kernel and user mode operation, but do not require
page management software or an on-chip TLB, leading to a
simpler software model and a lower-cost processor.
The memory mapping used by these devices is illustrated
in Figure 3. Note that the reserved address spaces shown are
for compatibility with future family members; in the current
family members, references to these addresses are trans-
lated in the same fashion as their respective segments, with
no traps or exceptions taken.
• PortSizeControlRegister: Thisregisterallowsthekernel
to indicate the port width of reads and writes to various sub-
regionsofthephysicaladdressspace. Thus,theR3041can
interface directly with 8-, 16-, and 32-bit memory ports,
including a mix of sizes, for both instruction and data
references, without requiring additional external logic.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by ad-
PHYSICAL
VIRTUAL
0xffffffff
0xffffffff
Kernel Reserved
1MB
Kernel Reserved
0xfff00000
0xffefffff
1MB
0xfff00000
0xffefffff
Kernel Cached
Tasks
Kernel Cached
(kseg2)
1023 MB
0xc0000000
0xbfffffff
0xc0000000
0xbfffffff
User Reserved
1MB
Kernel Uncached
(kseg1)
0xbff00000
0xbfefffff
0xa0000000
0x9fffffff
Kernel Cached
(kseg0)
Kernel/User
Cached
0x80000000
0x7fffffff
0x7ff00000
0x7fefffff
Tasks
User Reserved
1MB
2047 MB
Kernel/User
Cached
0x40000000
0x3fffffff
Inaccessible
512 MB
(kuseg)
0x20000000
0x1fffffff
Kernel Boot
and I/O
0x00000000
0x00000000
512 MB
2905 drw 03
Figure 3. Virtual to Physical Mapping of Base Architecture Versions
3
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Clock Generation Unit
external bus.
TheR3041augmentsthebasicRISControllerbusinterface
capabilitybyaddingtheabilitytodirectlyinterfacewithvarying
memory port widths, for instructions or data. For example, the
R3041 can be used in a system with an 8-bit boot PROM, 16-
bit font/program cartridges, and 32-bit main memory, trans-
parently to software, and without requiring external data
packing, rotation, and unpacking.
The R3041 is driven from a single 2x frequency input clock,
capable of operating in a range of 40%-60% duty cycle. On-
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in R3000A based applications.
In addition, the R3041 incorporates the ability to change
some of the interface timing of the bus. These features can be
used to eliminate external data buffers and take advantage of
lower speed and lower cost interface components.
One of the bus interface options is the Extended Address
Hold mode which adds 1/2 clock of extra address hold time
from ALE falling. This allows easier interfacing to FPGAs and
ASICs.
Instruction Cache
The R3041 integrates 2kB of on-chip Instruction Cache,
organized with a line size of 16 bytes (four 32-bit entries) a nd
is direct mapped. This relatively large cache substantially
contributes to the performance inherent in the R3041, and
allows systems based on the R3041 to achieve high-perfor-
mance even from low-cost memory systems. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses and physical tags (rather than virtual addresses or
tags), and thus does not require flushing on context switch.
The R3041 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO proces-
sor address and data information in store operations, and
present it to the bus interface as write transactions at the rate
the memory system can accommodate. During main memory
writes, the R3041 can break a large datum (e.g. 32-bit word)
into a series of smaller transactions (e.g. bytes), according to
the width of the memory port being written. This operation is
transparent to the software which initiated the store, insuring
thatthesamesoftwarecanrunintrue32-bitmemorysystems.
The RISController family read interface performs both
single word reads and quad word reads. Single word reads
work with a simple handshake, and quad word reads can
either utilize the simple handshake (in lower performance,
simple systems) or utilize a tighter timing mode when the
memory system can burst data at the processor clock rate.
Thus, the system designer can choose to use page or static
column mode DRAMs (and possibly use interleaving, if de-
sired, in high-performance systems), or even to use simpler
SRAM techniques to reduce complexity.
In order to accommodate slower quad word reads, the
RISController family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches.
In addition, the R3041 can perform on-chip data packing
when performing large datum reads (e.g., quad words) from
narrower memory systems (e.g., 16-bits). Once again, this
operation is transparent to the actual software, simplifying
migration of software to higher performance (true 32-bit)
systems, and simplifying field upgrades to wider memory.
Since this capability works for either instruction or data reads,
using 8-, 16-, or 32-bit boot PROMs is easily supported by the
Data Cache
The R3041 incorporates an on-chip data cache of 512B,
organized as a line size of 4 bytes (one word) and is direct
mapped. Thisrelativelylargedatacachecontributessubstan-
tially to the performance inherent in the RISController family.
As with the instruction cache, the data cache is implemented
as a direct mapped physical address cache. The cache is
capableofmappinganywordwithinthe4GBphysicaladdress
space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.
Bus Interface Unit
The RISController family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
The RISController family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE (Address Latch
Enable) output signal to de-multiplex the A/D bus, and simple
handshake signals to process CPU read and write requests.
In addition to the read and write interface, the R3041 incorpo-
rates a DMA arbiter, to allow an external master to control the
4
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
R3041.
boot PROM instead. A 16-bit font/program cartridge interface
is provided for add-in cards. A 16-bit DRAM interface is used
for a low-cost page frame buffer. In this system example, a
field or manufacturing upgrade to a 32-bit page frame buffer
is supported by the boot software and DRAM controller.
Embedded systems may optionally substitute SRAMs for the
DRAMs. Finally various 8/16/32-bit I/O ports such as RS-232/
422, SCSI, and LAN as well as the laser printer engine
interface are supported. Such a system features a very low
entry price, with a range of field upgrade options including the
ability to upgrade to a more powerful member of the
RISController family.
SYSTEM USAGE
The IDT RISController family is specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems use inexpensive EPROMs, DRAMs, and
application specific peripherals.
Figure4showssomeoftheflexibilityinherentintheR3041.
Inthisexamplesystem, whichistypicalofa laserprinter, a32-
bit PROM interface is used due to the size of the PDL
interpreter. An embedded system can optionally use an 8-bit
ClkIn
IDT R3041
RISController
Control
Address/
Data
R3051
Local Bus
EPROM and
I/O Controller
DRAM
Controller
16-bit
16-bit
Add-on
DRAM
32-bit
EPROM
16-bit
DRAM
Font
I/O
Cartridge
2905 drw 04
Figure 4. Typical R3041-Based Application
5
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
edged leader in optimizing compiler technology.
• Cross development tools, available in a variety of develop-
ment environments.
• The high-performance IDT floating point emulation library
software.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT PROM Monitor.
• IDTLaserPrinterSystemboards, whichdirectlydrivealow-
cost print engine, and runs Adobe PostScript™ Page De-
scription Language
DEVELOPMENT SUPPORT
The IDT RISController family is supported by a rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications soft-
ware and utility libraries, logic analysis tools, and sub-system
modules.
Figure5isanoverviewofthesystemdevelopmentprocess
typically used when developing R3041 applications. The
RISController family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for RISController family based
applications, and include tools such as:
• Adobe PostScript Page Description Language running on
the IDT RISController family.
• The IDT/sim™ PROM Monitor, which implements a full
PROM monitor (diagnostics, remote debug support, peek/
• Optimizing compilers from MIPS Technology, the acknowl-
System
Architecture
Evaluation
System
System
Development
Integration
Phase
and Verfification
Software
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript PDL
MicroSoft TrueImage PDL
PeerlessPage BIOS
IDT/kit
Logic Analysis
Diagnostics
IDT/sim PROM Monitor
Remote Debug
Real-Time OS
Cache3041
Benchmarks
Evaluation Board
Laser Printer System
Hardware
Hardware Models
General CAD Tools
RISC Sub-systems
'341 Evaluation Board
Laser Printer System
2905 drw 05
Figure 5. R3041 Development Environment
6
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
poke, etc.).
vices in their application.
• IDT/kit™ (Kernel Integration Toolkit), providing library sup-
port and a frame work for the system run time environment.
PERFORMANCE OVERVIEW
SELECTABLE FEATURES
The RISController family uses two methods to allow the
system designer to configure bus interface operation options.
The first set of options are established via the Reset
Configuration Mode inputs, sampled during the device reset.
After reset, the Reset Mode inputs become regular input or
output signals.
The RISController family achieves a very high-level of
performance. This performance is based on:
• An efficient execution engine: The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the R3041 achieves 20
MIPS performance at 25MHz when operating out of cache.
• Large on-chip caches: The RISController family contains
caches which are substantially larger than those on the
majorityofembeddedmicroprocessors.Theselargecaches
minimize the number of bus transactions required, and
allow the RISController family to achieve actual sustained
performanceveryclosetoitspeakexecutionrate, evenwith
low-cost memory systems.
• Autonomous multiply and divide operations: The
RISController family features an on-chip integer multiplier/
divideunitwhichisseparatefromtheotherALU. Thisallows
theR3041toperformmultiplyordivideoperationsinparallel
with other integer operations, using a single multiply or
divide instruction rather than using “step” operations.
• Integrated write buffer: The R3041 features a four deep
writebuffer,whichcapturesstoretargetaddressesanddata
at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of on-
chip write buffers eliminates the need for the processor to
stall when performing store operations.
The second set of configuration options are contained in
the System Control Co-Processor registers. These Co-pro-
cessor registers configuration options are typically initialized
with the boot PROM and can also be changed dynamically by
the kernel software.
Selectable features include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits inter-
communication between various types of processors and
databases.
• Data Cache Refill of one or four words: The memory
system must be capable of performing 4 word transfers to
satisfy instruction cache misses and 1 word transfers to
satisfy uncached references. The data cache refill size
option allows the system designers to choose between one
and four word refill on data cache misses, depending on the
performance each option brings to their application.
• Bus Turn Around speed: The R3041 allows the kernel to
increase the amount of time between bus transactions
when changes in direction of the A/D bus occur (e.g., at the
end of reads followed by writes). This allows transceivers
and buffers to be eliminated from the system.
• Extended Address Hold Time: The R3041 allows the
system designer to increase the amount of hold time avail-
able for address latching, thus allowing slower speed (low
cost) address latches, FPGAs and ASICs to be used.
• Programmable control signals: The R3041 allows the
system designer to optimally configure various memory
control signals to be active on reads only, writes only, or on
both reads and writes. This allows the simplification of
external logic, thus reducing system cost.
• Burst read support: The R3041 enables the system
designertoutilizepagemode, staticcolumn, ornibblemode
RAMs when performing read operations to minimize the
mainmemoryreadpenaltyandincreasetheeffectivecache
hit rates.
The performance differences among the various
RISController family members depends on the application
software and the design of the memory system. Different
family members feature different cache sizes, and the R3081
features a hardware floating point accelerator. Since all these
devices can be used in a pin and software compatible fashion,
the system designer has maximum freedom in trading be-
tween performance and cost. The memory simulation tools
(e.g. Cache3041) allows the system designers to analyze and
understand the performance differences among these de-
7
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
• Programmable memory Port Widths: The R3041 allows
ThemembersoftheRISControllerfamilyareguaranteedin
the kernel to partition the physical memory space into a case temperature range of 0°C to +85°C. The type of
various sub-regions, and to individually indicate the port package, speed (power) of the device, and airflow conditions,
width of these sub-regions. Thus, the bus interface unit can affect the equivalent ambient conditions which meet this
perform data packing and unpacking when communicating specification.
with narrow memory sub-regions. For example, these fea-
The equivalent allowable ambient temperature, TA, can be
tures, can be used to allow the R3041 to interface with calculated using the thermal resistance from case to ambient
narrow 8-bit boot PROMs, or to implement 16-bit only (ØCA) of the given package. The following equation relates
memory systems.
THERMAL CONSIDERATIONS
ambient and case temperature:
TA = TC - P * ØCA
where P is the maximum power consumption at hot tempera-
ture, calculatedbyusingthemaximumIccspecificationforthe
device.
The RISController family utilizes special packaging tech-
niques to improve the thermal properties of high-speed pro-
cessors. Thus, all versions of the RISController family are
packaged in cavity down packaging.
Typical values for ØCA at various airflows are shown in
Table 2 for the PLCC package.
The lowest cost members of the family use a standard
cavity down, injection molded PLCC package (the “J” pack-
age). This package is used for all speeds of the R3041 family.
Higher speed and higher performance members of the
RISController family utilize more advanced packaging tech-
niques to dissipate power while remaining both low-cost and
pin- and socket- compatible with the PLCC package. Thus,
thesemembersoftheRISControllerfamilyareavailableinthe
MQUAD package (the “MJ” package), which is an all alumi-
num package with the die attached to a normal copper lead-
frame mounted to the aluminum casing. The MQUAD pack-
age ispinandformcompatiblewiththePLCCpackage. Thus,
designerscanchoosetoutilizethispackagewithoutchanging
their PCB.
NOTES ON SYSTEM DESIGN
The R3041 has been designed to simplify the task of high-
speed system design. Thus, set-up and hold-time require-
ments have been kept to a minimum, allowing a wide variety
of system interface strategies.
To minimize these AC parameters, the R3041 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3041 to reference input signals to the
reference clock seen by the external system. The SysClk
output is designed to provide relatively large AC drive to
minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise or fall (10% to 90% signal times) when
driving the test load.
Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net and the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.
Airflow (ft/min)
ØCA
"J" Package
TQFP
0
200
26
400
21
600
18
800
16
1000
Similarly, theR3041employsfeedbackonitsALEoutputto
ensure adequate address hold time to ALE. The system
designer should be careful when designing the ALE net to
minimizetotalloadingandtominimizeskewbetweenALEand
the A/D bus, which will ensure adequate address access latch
time.
29
55
15
40
35
33
31
30
2905 tbl 02
Table 2. Thermal Resistance (ØCA) at Various Airflows
IDT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.
8
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
11 10
12
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75
74
V
SS
V
SS
CC
VCC
13
14
V
73
72
71
70
69
68
67
66
65
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(9)
ClkIn
TriState
BE16(1)
BE16(0)
Addr(1)
Addr(0)
Int(5)
15
16
17
18
19
20
V
CC
SS
21
22
23
VSS
V
VCC
64
63
62
61
60
59
58
57
A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
Int(4)
Int(3)
24
25
SInt(2)
SInt(1)
26
27
28
SInt(0)
SBrCond(3)/ IOStrobe
SBrCond(2)/ ExtDataEn
TC
V
SS
CC
29
30
31
32
V
A/D(2)
A/D(1)
A/D(0)
56
55
54
VSS
VCC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2905 drw 06
84-Pin PLCC/
Top View
(Cavity Down)
9
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
2524232221201918171615 1413 121110 9 8 7 6 5 4 3 2 1
NC
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSS
V
CC
VCC
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(9)
ClkIn
TriState
BE16(1)
BE16(0)
Addr(1)
Addr(0)
Int(5)
VCC
VSS
VSS
IDT R3041/RV3041
A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
VCC
100-Pin
TQFP
(Cavity Up)
Top View
Int(4)
Int(3)
SInt(2)
SInt(1)
SInt(0)
VSS
SBrCond(3)/IOStrobe
SBrCond(2)/ExtDataEn
TC
V
CC
A/D(2)
A/D(1)
A/D(0)
NC
VSS
VCC
NC
NC
NC
515253 54555657585960616263 646566676869707172737475
2905 drw 06
10
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
PIN NAME
I/O
DESCRIPTION
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
inonephase, andwhichisusedtotransmitdatabetweentheCPUandexternalmemoryresourcesduring
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31:4):
The high-order address for the transfer is presented on A/D(31:4).
BE(3:0):
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on A/D(3:0). BE(3) indicates that
A/D(31:24) will be used, and BE(0) corresponds to A/D(7:0). These
strobes are only valid for accesses to 32-bit wide memory ports. Note
that BE(3:0) can be held in-active during reads by setting the appropriate
bitofCP0;thuswhenlatched, thesesignalscanbedirectlyusedasWrite
Enable strobes.
During the second phase, these signals are the data bus for the transaction.
Data(31:0): During write cycles, the bus contains the data to be stored and is driven
from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in
either a single data transaction or in a burst of four words, and places it
into the on-chip read buffer.
The byte lanes used during the transfer are a function of the datum size,
the memory port width, and the system byte-ordering.
Addr(3:0)
O
Low Address (3:0) A 4-bit bus which indicates which word/halfword/byte is currently expected by the
processor. For 32-bit port widths, only Addr(3:2) is valid during the transfer; for 16-bit port widths, only
Addr(3:1) are valid; for 8-bit port widths, all of Addr(3:0) are valid. These address lines always contain
theaddressofthecurrentdatumtobetransferred. Inwritesandsingledatumreads,theaddressesinitially
output the specific target address, and will increment if the size of the datum is wider than the target
memory port. For quad word reads, these outputs function as a counter starting at '0000', and
incrementing according to the width of the memory port.
I(1)
During Reset, the Addr(3:0) pins act as Reset Configuration Mode bit inputs for the BootProm16,
BootProm8, ReservedHigh, and ExtAddrHold options.
The R3041 Addr(1:0) output pins are designated as the unconnected Rsvd(1:0) pins in the R3051 and
R3081.
Diag
O
Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on-
chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:
Cached/Uncached:
DuringthephaseinwhichtheA/Dbuspresentsaddressinformation, this
pin is an active high output which indicates whether or not the current
read is a result of a cache miss. The value of this pin at this time other
than in read cycles is undefined.
I/D:
A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.
The R3041 Diag output pin is designated as the Diag(1) output pin in the R3051 and R3081.
ALE
O
O
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.
DataEn
Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
action is occurring, this signal is negated, thus disabling the external memory drivers.
trans-
2905 tbl 03
NOTE:
1. Reset Configuration Mode bit input when Reset is asserted, normal signal
function when Reset is de-asserted.
11
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued):
PIN NAME
I/O
DESCRIPTION
Burst/
WrNear
O
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles
if the 4-word data block refill option is selected in the CP0 Cache Config Register.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 256 byte page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows nearby writes to be retired quickly.
Rd
O
O
I
Read: An output which indicates that the current bus transaction is a read.
Write: An output which indicates that the current bus transaction is a write.
Wr
Ack
Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction. On write transactions, this signal indicates that the CPU may either
progress to the next data item (for mini-burst writes of wide datums to narrow memories), or terminate
the write cycle. On read transactions, this signal indicates that the memory system has sufficiently
processed the read, and that the processor core may begin processing the data from this read transfer.
RdCEn
SysClk
BusReq
BusGnt
I
Read Buffer Clock Enable: An input which indicates to the device that the memory system has
placed valid data on the A/D bus, and that the processor may move the data into the on-chip Read
Buffer.
O
I
System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "System" clock. This clock is used to control state transitions in the read buffer, write buffer,
memory controller, and bus interface unit.
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus
interfacesignalssothattheymaybedrivenbyanexternalmaster. Thenegationofthisinputrelinquishes
mastership back to the CPU.
O
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.
The R3041 adds an additional DMA protocol, under the control of CP0. If the DMA Protocol is enabled,
the R3041 can request that the external master relinquish bus mastership back to the processor by
negating the BusGnt output early, and waiting for the BusReq input to be negated.
SBrCond(3)/
IOStrobe
I/O
Branch Condition Port/IO Strobe: The use of this signal depends on the setting of various bits of the
CP0 Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(3),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(3)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as IOStrobe, it may be asserted as an output on reads, writes, or both,
as programmed into CP0. This strobe asserts in the second clock cycle of a transfer, and thus can be
used to strobe various control signals on the bus interface.
SBrCond(2)/
ExtDataEn
I/O
Branch Condition Port/Extended Data Enable: The use of this signal depends on the settings in the
CP0 Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(2),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(2)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as Extended Data Enable, it may be asserted as an output on reads,
writes, or both, as programmed into CP0. This strobe can be used as an extended data enable strobe,
in that it is held asserted for one-half clock cycle after the negation of Rd or Wr. This signal may typically
be used as a write enable control line for transceivers, as a write line for I/O, or as an address mux select
for DRAMs.
MemStrobe
O
Memory Strobe: This active low output pulses low for each data read or written, as configured in the
CP0 Bus Control register. Thus, it can be used as a read strobe, write strobe, or both, for SRAM type
memories or for I/O devices.
The R3041 MemStrobe output pin is designated as the BrCond(0) input pin in the R3051 and R3081.
2905 tbl 04
12
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued):
PIN NAME
I/O
DESCRIPTION
BE16(1:0)
O
Byte Enable Strobes for 16-bit Memory Port: These active low outputs are the byte lane strobes for
accessesto16-bitwidememoryports;theyarenotnecessarilyvalidfor8-or32-bitwideports. IfBE16(1)
is asserted, then the most significant byte (either D(31:24) or D(15:8), depending on system endianness)
is going to be used in this transfer. If BE16(0) is asserted, the least significant byte (D(23:16) or D(7:0))
will be used.
BE16(1:0) canbeheldinactive(masked)duringreadtransfers, accordingtotheprogrammingoftheCP0
Bus Control register.
I(1)
O
During Reset, the BE16(1:0) act as Reset Configuration Mode bit inputs for two ReservedHigh options.
The BE16(1:0) output pins are designated as the unconnected Rsvd(3:2) pins in the R3051 and R3081.
Last
TC
Last Datum in Mini-Burst: This active low output indicates that this is the last datum transfer in a given
transaction. It is asserted after the next to last RdCEn (reads) or Ack (writes), and is negated when Rd
or Wr is negated.
The Last output pin is designated in the R3051 and R3081 as the Diag(0) output pin.
O
Terminal Count: This is an active low output from the processor which indicates that the on-chip timer
has reached its terminal count. It will remain low for either 1.5 clock cycles, or until software resets the
timer, depending on the mode selected in the CP0 Bus Control register. Thus, the on-chip timer can
function either as a free running timer for system functions such as DRAM refresh, or can operate as a
software controlled time-slice timer, or real-time clock.
The TC output pin is designated in the R3051 as the BrCond(1) input pin, and in the R3081 as the Run
pin output.
BusError
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
Int(5:3)
SInt(2:0)
I
Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000A. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals on the original R3000A.
I(1)
During Reset, Int(3) and SInt(0) act as Reset Configuration Mode bit inputs for the
AddrDisplayAndForceCacheMiss and BigEndian options.
There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor,
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.
ClkIn
I
I
Master Clock Input: This is a double frequency input used to control the timing of the CPU.
Reset
Master Processor Reset: This signal initializes the CPU. Reset initialization mode selection is
performed during the last cycle of Reset.
TriState
I
Tri-State: This input to the R3041 requests that the R3041 tri-state all of its outputs. In addition to those
outputs tri-stated during DMA, tri-state will cause SysClk, TC, and BusGnt to tri-state. This signal is
intended for use during board testing and emulation during debug and board manufacture.
The TriState input pin is designated as the unconnected Rsvd(4)pin in the R3051 and R3081.
Vcc
Vss
I
I
Power: These inputs must be supplied with the rated supply voltage (VCC). All Vcc inputs must be
connected to insure proper operation.
Ground: These inputs must be connected to ground (GND). All Vss inputs must be connected to insure
proper operation.
2905 tbl 05
NOTE:
1. Reset Configuration Mode bit input when Reset is asserted, normal signal
function when Reset is de-asserted.
13
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1, 3) R3041
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
Grade
Temperature
0°C to +85°C
(Case)
GND
VCC
Commercial
0V
5.0 ±5%
TC
TBIAS
TSTG
VIN
Operating Case Temperature
Temperature Under Bias
Storage Temperature
Input Voltage
0 to +85
°C
°C
2905 tbl 07
–55 to +125
–55 to +125
–0.5 to +7.0
°C
V
OUTPUT LOADING FOR AC TESTING
NOTES:
2905 tbl 06
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
+4mA
2. VIN minimum = –3.0V for pulse width less than 15ns.
VIN should not exceed VCC +0.5 Volts.
3. Notmorethanoneoutputshouldbeshortedatatime. Durationoftheshort
should not exceed 30 seconds.
V
REF
-
+
To Device
Under Test
+1.5V
C
LD
-4mA
AC TEST CONDITIONS R3041
2905 drw 07
Symbol
Parameter
Min.
3.0
—
Max.
—
0
Unit
V
VIH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Signal
Cld
VIL
V
All Signals
25 pF
VIHS
VILS
3.5
—
—
0
V
2905 tbl 09
V
2905 tbl 08
DC ELECTRICAL CHARACTERISTICS R3041 — (TC = 0°C to +85°C, VCC = +5.0V ±5%)
16.67MHz
20MHz
25MHz
33MHz
Symbol
VOH
VOL
Parameter
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(3)
Input LOW Voltage(1)
Input HIGH Voltage(2,3)
Input LOW Voltage(1,2)
Input Capacitance(4)
Output Capacitance(4)
Operating Current
VCC = Min., IOH = –4mA
3.5
—
—
0.4
—
3.5
—
—
0.4
—
3.5
—
—
0.4
—
3.5
—
—
0.4
—
V
V
VCC = Min., IOL = 4mA
VIH
—
2.0
—
2.0
—
2.0
—
2.0
—
V
VIL
—
0.8
—
0.8
—
0.8
—
0.8
—
V
VIHS
VILS
CIN
—
3.0
—
3.0
—
3.0
—
3.0
—
V
—
0.4
10
0.4
10
0.4
10
0.4
10
10
V
—
—
—
—
—
pF
pF
COUT
ICC
—
—
10
—
10
—
10
—
VCC = 5V, TC = 25°C
VIH = VCC
VIL = GND
—
225
100
—
—
250
100
—
—
300
100
—
—
370 mA
IIH
Input HIGH Leakage
Input LOW Leakage
—
—
—
—
100
—
µA
µA
IIL
–100
–100
–100
–100
IOZ
Output Tri-state Leakage VOH = 2.4V, VOL = 0.5V
–100 100 –100 100 –100 100 –100 100
µA
NOTES:
2905 tbl 10
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below –0.5 volts for larger periods.
2. VIHS and VILS apply to CIkIn and Reset.
3. VIH should not be held above VCC + 0.5 volts.
4. Guaranteed by design.
14
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS R3041 (1, 2, 3)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)
16.67MHz
20MHz
25MHz
33MHz
Symbol
Signals
BusReq, Ack, BusError, RdCEn Set-up to SysClk rising
A/D Set-up to SysClk falling
BusReq, Ack, BusError, RdCEn Hold from SysClk rising
Description
Min.
Max.
—
Min.
Max.
—
Min. Max.
Min. Max. Unit
t1
t1a
t2
11
12
4
8
9
3
5.5
7
—
—
—
5.5
7
—
—
ns
ns
ns
—
—
—
—
2.5
2.5
t2a
t3
A/D
Hold from SysClk falling
2
—
2
—
1
—
1
—
ns
ns
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Tri-state from SysClk rising
(after driven condition)
—
13
—
10
—
10
—
10
t4
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Driven from SysClk falling
(after tri-state condition)
—
13
—
10
—
10
—
10
ns
t5
t6
BusGnt
Asserted from SysClk rising
Negated from SysClk falling
Valid from SysClk rising
Valid from SysClk rising
Valid from SysClk rising
Asserted from SysClk rising
Negated from SysClk falling
Hold from ALE negated
Asserted from SysClk
—
—
—
—
—
—
—
2
10
10
8
—
—
—
—
—
—
—
2
8
8
—
—
—
—
—
—
—
2
7
7
—
—
—
—
—
—
—
1.5
—
0
7
7
5
8
8
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BusGnt
t7
Wr, Rd, Burst/WrNear, TC
6
5
t7a
t7b
t8
A/D
12
12
5
9
8
Last
9
8
ALE
4
4
t9
ALE
5
4
4
t10
t11
t12
t14
t15
A/D
—
19
—
—
9
—
15
—
—
7
—
15
—
—
6
DataEn
DataEn
A/D
—
0
—
0
—
0
15
—
—
6
(4)
Asserted from A/D tri-state
(4)
Driven from SysClk rising
0
0
0
0
Wr, Rd, DataEn, Burst/WrNear,
Last, TC
Negated from SysClk falling
—
—
—
—
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
tsys
t32
t33
Addr(3:0), BE 16(1:0)
Diag
Valid from SysClk
—
—
—
—
12
12
30
200
32
8
11
15
13
16
—
—
250
—
—
—
—
—
—
—
—
—
—
—
—
—
10
10
25
200
32
6
8
12
10
13
—
—
250
—
—
—
—
—
—
—
—
—
—
—
—
—
8
7
11
10
12
—
—
250
—
—
—
—
—
—
—
—
—
—
—
—
—
6.5
6.5
15
200
32
5
7
11
10
12
—
—
250
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
µs
sys
ns
ns
ns
ns
ns
ns
ns
ns
Valid from SysClk
A/D
Tri-state from SysClk
SysClk to data out
A/D
ClkIn
Pulse Width High
ClkIn
Pulse Width Low
8
ClkIn
Clock Period
20
200
32
5
Reset
Pulse Width from Vcc valid
Minimum Pulse Width
Set-up to SysClk falling
Mode set-up to Reset rising
Mode hold from Reset rising
Set-up to SysClk falling
Hold from SysClk falling
Set-up to SysClk falling
Hold from SysClk falling
Pulse Width
Reset
Reset
Int
8
6
5
5
Int
2.5
8
2.5
6
2.5
5
2.5
5
SInt, SBrCond
SInt, SBrCond
Int, BrCond
Int, BrCond
SysClk
SysClk
SysClk
4
3
3
3
8
6
5
5
4
3
3
3
2*t22
2*t22 2*t22
2*t22 2*t22
2*t22 2*t22 2*t22
Clock High Time
t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns
Clock Low Time
t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns
2905 tbl 11
15
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS R3041 (CONT.)
16.67MHz
20MHz
Max. Min.
10
25MHz
33MHz
Max. Unit
Symbol
Signals
Description
Min. Max. Min.
Max. Min.
t45
ExtDataEn
Tri-state from SysClk rising
(after driven condition)
—
—
13
13
—
—
—
10
10
—
10
ns
t46
ExtDataEn
Driven from SysClk falling
(after driven condition)
10
—
—
10
ns
t47
IOStrobe
Valid from SysClk falling
—
—
—
—
—
0
10
15
9
—
—
—
—
—
0
8
12
7
—
—
—
—
—
0
7
9
—
—
—
—
—
0
7
9
ns
ns
ns
ns
ns
ns
t48
ExtDataEn, DataEn
ExtDataEn
Asserted from SysClk rising
Negated from SysClk rising
Asserted from SysClk rising
Negated from SysClk falling
Asserted from Addr(3:0) valid
Timing deration for loading
t49
6
6
t50
MemStrobe
MemStrobe
MemStrobe
All outputs
19
19
—
0.5
15
15
—
0.5
15
15
—
0.5
15
15
—
0.5
t51
(4)
t52
tderate
—
—
—
—
ns/
25pF
(4, 5)
over 25pF
NOTES:
2905 tbl 12
1. All timings referenced to 1.5 Volts, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3041 Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
6. Timings t34 - t44 are reserved for other RISController family members.
ABSOLUTE MAXIMUM RATINGS(1, 3) RV3041
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
Grade
Commercial
RV3041
Temperature
0°C to +85°C
(Case)
GND
VCC
0V
3.3 ±5%
TC
TBIAS
TSTG
VIN
Operating Case Temperature
Temperature Under Bias
Storage Temperature
Input Voltage
0 to +85
°C
°C
2905 tbl 07
–55 to +125
–55 to +125
–0.5 to +7.0
°C
V
OUTPUT LOADING FOR AC TESTING
NOTES:
2905 tbl 06
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
+4mA
2. VIN minimum = –3.0V for pulse width less than 15ns.
VIN should not exceed VCC +0.5 Volts.
3. Notmorethanoneoutputshouldbeshortedatatime. Durationoftheshort
should not exceed 30 seconds.
V
REF
-
+
To Device
Under Test
+1.5V
C
LD
-4mA
AC TEST CONDITIONS RV3041
2905 drw 07
Symbol
Parameter
Min.
3.0
—
Max.
—
0
Unit
V
VIH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Signal
Cld
25 pF
VIL
V
All Signals
VIHS
VILS
3.0
—
—
0
V
2905 tbl 09
V
2905 tbl 08
16
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS RV3041 — (TC = 0°C to +85°C, VCC = +3.3V ±5%)
16.67MHz
20MHz
25MHz
33MHz
Symbol
VOH
VOL
VIH
Parameter
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(3)
Input LOW Voltage(1)
Input HIGH Voltage(2,3)
Input LOW Voltage(1,2)
Input Capacitance(4)
Output Capacitance(4)
Operating Current
VCC = Min., IOH = –4mA
2.4
—
—
0.4
—
2.4
—
—
0.4
—
2.4
—
—
0.4
—
2.4
—
—
0.4
—
V
V
VCC = Min., IOL = 4mA
—
2.0
—
2.0
—
2.0
—
2.0
—
V
VIL
—
0.8
—
0.8
—
0.8
—
0.8
—
V
VIHS
VILS
CIN
—
2.5
—
2.5
—
2.5
—
2.5
—
V
—
0.4
10
0.4
10
0.4
10
0.4
10
10
V
—
—
—
—
—
—
pF
pF
COUT
ICC
—
10
—
10
—
10
—
VCC = 3.3V, TC = 25°C
VIH = VCC
—
130
100
—
—
150
100
—
—
180
100
—
—
225 mA
100 mA
IIH
Input HIGH Leakage
Input LOW Leakage
—
—
—
—
IIL
VIL = GND
–100
–100
–100
–100
—
mA
IOZ
Output Tri-state Leakage VOH = 2.4V, VOL = 0.5V
–100 100 –100 100 –100 100 –100 100 mA
NOTES:
2905 tbl 10
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below –0.5 volts for larger periods.
2. VIHS and VILS apply to CIkIn and Reset.
3. VIH should not be held above VCC + 0.5 volts.
4. Guaranteed by design.
AC ELECTRICAL CHARACTERISTICS RV3041 (1, 2, 3)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)
16.67MHz
20MHz
25MHz
33MHz
Symbol
Signals
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t1
BusReq, Ack, BusError,
RdCEn
Set-up to SysClk rising
11
—
8
—
5.5
—
5.5
—
ns
t1a
t2
A/D
Set-up to SysClk falling
Hold from SysClk rising
12
4
—
—
9
3
—
—
7
—
—
7
—
—
ns
ns
BusReq, Ack, BusError,
RdCEn
2.5
2.5
t2a
t3
A/D
Hold from SysClk falling
2
—
2
—
1
—
1
—
ns
ns
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Tri-state from SysClk rising
(after driven condition)
—
13
—
10
—
10
—
10
t4
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Driven from SysClk falling
(after tri-state condition)
—
13
—
10
—
10
—
10
ns
t5
BusGnt
Asserted from SysClk rising
Negated from SysClk falling
Valid from SysClk rising
Valid from SysClk rising
Valid from SysClk rising
Asserted from SysClk rising
Negated from SysClk falling
Hold from ALE negated
—
—
—
—
—
—
—
2
10
10
8
—
—
—
—
—
—
—
2
8
8
—
—
—
—
—
—
—
2
7
7
—
—
—
—
—
—
—
1.5
—
0
7
7
5
8
8
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t6
BusGnt
t7
Wr, Rd, Burst/WrNear, TC
6
5
t7a
t7b
t8
A/D
12
12
5
9
8
Last
9
8
ALE
4
4
t9
ALE
5
4
4
t10
t11
t12
t14
t15
A/D
—
19
—
—
9
—
15
—
—
7
—
15
—
—
6
DataEn
DataEn
A/D
Asserted from SysClk
—
0
—
0
—
0
15
—
—
6
Asserted from A/D tri-state(4)
Driven from SysClk rising(4)
Negated from SysClk falling
0
0
0
0
Wr, Rd, DataEn,
—
—
—
—
Burst/WrNear, Last, TC
t16
t17
Addr(3:0), BE 16(1:0)
Diag
Valid from SysClk
Valid from SysClk
—
—
11
15
—
—
8
—
—
7
—
—
7
ns
ns
12
11
11
2905 tbl 11
17
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS RV3041 (CONT.)
16.67 MHz
20 MHz
25MHz
Max.
33MHz
Symbol
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
tsys
t32
t33
t45
Signals
Description
Tri-state from SysClk
SysClk to data out
Min.
—
Max.
13
Min. Max. Min.
Min. Max. Unit
A/D
A/D
—
—
10
10
25
200
32
6
10
13
—
—
250
—
—
—
—
—
—
—
—
—
—
—
8
10
12
—
—
250
—
—
—
—
—
—
—
—
—
—
—
6.5
6.5
15
200
32
5
10
12
—
—
250
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
µs
sys
ns
ns
ns
ns
ns
ns
ns
—
16
ClkIn
Pulse Width High
12
12
30
200
32
8
—
ClkIn
Pulse Width Low
—
8
ClkIn
Clock Period
250
—
20
200
32
5
Reset
Pulse Width from Vcc valid
Minimum Pulse Width
Set-up to SysClk falling
Mode set-up to Reset rising
Mode hold from Reset rising
Set-up to SysClk falling
Hold from SysClk falling
Set-up to SysClk falling
Hold from SysClk falling
Pulse Width
Reset
—
Reset
—
Int
8
—
6
5
5
Int
2.5
8
—
2.5
6
2.5
5
2.5
5
SInt, SBrCond
SInt, SBrCond
Int, BrCond
Int, BrCond
SysClk
SysClk
SysClk
ExtDataEn
—
4
—
3
3
3
8
—
6
5
5
4
—
3
3
3
2*t22
2*t22
2*t22 2*t22 2*t22 2*t22 2*t22 2*t22 ns
Clock High Time
t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns
t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 ns
Clock Low Time
Tri-state from SysClk rising
(after driven condition)
—
13
—
10
—
10
—
10
ns
t46
ExtDataEn
Driven from SysClk falling
(after driven condition)
—
13
—
10
—
10
—
10
ns
t47
t48
t49
IOStrobe
Valid from SysClk falling
Asserted from SysClk rising
Negated from SysClk rising
—
—
—
10
15
9
—
—
—
8
12
7
—
—
—
7
9
6
—
—
—
7
9
6
ns
ns
ns
ExtDataEn,
ExtDataEn
DataEn
t50
t51
t52
MemStrobe
MemStrobe
MemStrobe
Asserted from SysClk rising
Negated from SysClk falling
Asserted from Addr(3:0) valid(4)
—
—
0
19
19
—
—
—
0
15
15
—
—
—
0
15
15
—
—
—
0
15
15
—
ns
ns
ns
tderate All outputs
Timing deration for loading
over 25pF(4, 5)
—
0.5
—
0.5
—
0.5
—
0.5
ns/
25pF
NOTES:
2905 tbl 12
1. All timings referenced to 1.5 Volts, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3041 Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
6. Timings t34 - t44 are reserved for other RISController family members.
18
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
t
22
t
21
ClkIn
t
20
t
33
SysClk
t32
t
sys
2905 drw 08
Figure 8. RISController Family Clocking
V
CC
ClkIn
t
23
Reset
2905 drw 09
Figure 9. Power-On Reset Sequence
ClkIn
t
24
Reset
2905 drw 10
Figure 10(a). Warm Reset Sequence
ClkIn
t
23
Reset
2905 drw 11
Figure 10(b). Warm Reset Sequence (Internal Pull-Ups Used)
SysClk
Reset
t
25
t
26
Mode Vector Inputs:
SInt(2:0), Int(5:3)
Mode Vector Inputs:
Addr(3:0), BE16(1:0)
External Device Drives Signals
CPU Drives
2905 drw 12
t
27
t
4
Figure 11. Mode Selection and Negation of Reset
19
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Address
Memory
Turn
Bus
Sample
Data?
SysClk
t7
Rd
A/D(31:0)
Addr(3:2)
ALE
t
7a
t
18
t
14
Addr
BE
t
16
t
10
t
9
t
8
t
12
DataEn
Diag
t
11
t
17
t
17
Cached?
I/D
2905 drw 13
Figure 12(a). Start of Read Timing with Non-Extended Address Hold Option
Address
Memory
Extend
Address
Sample
Data?
SysClk
Rd
t7
t
t
7a
16
t
18
t
14
Addr
BE
A/D(31:0)
Addr(3:2)
ALE
t
9
t
8
t
12
DataEn
Diag
t
48
t
17
t
17
Cached?
I/D
2905 drw 14
Figure 12(b). Start of Read Timing with Extended Address Hold Option
20
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Address
Memory
Data
Phase
End
Write?
SysClk
t7
Wr
A/D(31:0)
Addr(3:2)
ALE
t
t
7a
16
t
19
t
14
Addr
BE
Data
Out
t
10
t
9
t
8
t
48
ExtDataEn
WrNear
t
7
2905 drw 15
Figure 12(c). Start of Write Timing with Non-Extended Address Hold Option
Address
Memory
End
Write?
Extended
Address
SysClk
Wr
t
7
t
t
7a
16
t
19
t
14
Addr
BE
Data
Out
A/D(31:0)
Addr(3:2)
ALE
t
9
t
8
t
48
ExtDataEn
WrNear
t
7
2905 drw 16
Figure 12(d). Start of Write Timing with Extended Address Hold Option
21
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Run/
Stall
Stall
Stall
Stall
Stall
Stall
Fixup
PhiClk
SysClk
Rd
t
7
t15
t
7a
t
14
t
18
t
1a
Data Input
2a
t
14
Addr
BE
A/D(31:0)
Addr(3:2)
ALE
t
t
16
t
16
Word Address
t
8
t
9
t
12
t
15
DataEn
ExtDataEn
Burst
t
49
t
48
t
7
t
7b
t
t
t
15
51
15
Last
t
18
t
12
MemStrobe
IOStrobe
RdCEn
Ack
t
50
t
47
t
1
t
2
t
17
t17
t
17
Cached?
I/D
Diag
Start Extended Ack/
Read Address RdCEn
?
Ack/
RdCEn
?
Ack/ Sample
RdCEn Data
End
Read
2905 drw 17
Figure 13. Single Datum Read
22
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Run/
Stall
Stall
Stall
Stall
Stall
Stall
Stall
Fixup
PhiClk
SysClk
Rd
t
7
t15
t
14
t
7a
t
1a
Byte 0
t
1a
Byte 1
t
1a
Byte 2
t
1a
t
14
Addr
18
Byte 3
A/D(31:0)
Addr(3:0)
ALE
t
t
2a
t
2a
t
2a
t
2a
t
16
'nn00'
'nn01'
'nn10'
'nn11'
t
16
t
16
t
16
t16
t
9
t
8
t
12
t
15
DataEn
ExtDataEn
Burst
t
49
t
t
48
t
7
t
15
t
7b
t
t
15
51
t
18
12
Last
t
50
t
50
t
50
t
50
MemStrobe
IOStrobe
RdCEn
Ack
t
51
47
t
51
t51
t
15
t
t
1
t1
t
1
t1
t
2
t2
t
2
t
2
t
17
t17
t
17
Cached?
I/D
Diag
Start Extended RdCEn Sample RdCEn Sample RdCEn Sample Ack/ Sample
New
Read Address
Data
Data
Data RdCEn Data Transaction
2905 drw 18
Figure 14. Mini-burst read of 32-bit datum from 8-bit wide memory port
23
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Fixup
Run/
Stall
Stall
Stall
Stall
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
Rd
t
7
t
15
t
14
t
7a
t
1a
Word 0
2a
t
1a
Word 1
2a
t
1a
Word 2
2a
t
1a
Word 3
t
14
Addr
BE
A/D(31:0)
Addr(3:2)
ALE
t
18
t
t
t
t
2a
t
16
'00'
'01'
'10'
'11'
t
16
t
16
t
16
t
16
t
9
t
8
t
12
t15
DataEn
ExtDataEn
Burst
t
49
t
t
48
t
7
t
7b
t
15
Last
t
18
12
t
50
t
50
t
50
t50
MemStrobe
IOStrobe
RdCEn
Ack
t
t
51
47
t
51
t
51
t
51
15
t
t
1
t
1
t1
t
1
t
2
t2
t
2
t
2
t
17
t17
t
17
Cached
I/D
Diag
Start Extended Ack/
Read Address RdCEn
Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
Data
Data
Data
Data Transaction
2905 drw 19
Figure 15. R3041 Quad Word Read
24
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Run/
Stall
Stall
Stall
Stall
Stall
Stall
Stall
Stall
PhiClk
SysClk
Rd
t7
t15
t14
t7a
t1a
t1a
t1a
t1a
t14
Addr
t18
Halfword 0
t2a
Halfword 1
t2a
Halfword 2
t2a
Halfword 3
t2a
A/D(31:0)
Addr(3:1)
ALE
t16
t8
'000'
t9
'001'
'010'
'011'
'100'
t16
t16
t16
t16
'00'
'00'
'00'
'00'
'00'
BE16(1:0)
DataEn
ExtDataEn
Burst
t16
t16
t16
t16
t16
t12
t48
t7
t18
t12
Last
t51
t51
t51
t51
t50
MemStrobe
IOStrobe
RdCEn
Ack
t50
t47
t50
t50
t50
t1
t1
t1
t1
t1
t2
t2
t2
t2
t2
t17
t17
Cached
I/D
Diag
Start Extended RdCEn Sample RdCEn Sample RdCEn Sample RdCEn Sample RdCEn
Read Address
Data
Data
Data
Data
2905 drw 20
Figure 16(a). Quad Word Read to 16-bit wide Memory Port
25
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Fixup
Stall
Stall
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
t15
Rd
t14
t1a
t1a
t1a
t1a
Halfword 4
t2a
Halfword 5
t2a
Halfword 6
t2a
Halfword 7
t2a
A/D(31:0)
Addr(3:1)
ALE
'100'
'101'
'110'
'111'
t16
t16
t16
t16
'00'
'00'
'00'
'00'
BE16(1:0)
DataEn
ExtDataEn
Burst
t16
t16
t16
t16
t15
t49
t7b
Last
t51
t15
t50
t50
t50
MemStrobe
t51
t51
t51
IOStrobe
RdCEn
t1
t1
t1
t1
t2
t2
t2
t2
Ack
t17
I/D
Diag
Ack/
RdCEn
Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
Data Data Data Data Transaction
2905 drw 21
Figure 16(b). End of Quad Word read from 16-bit Wide Memory Port
26
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
t
7
t
15
Wr
A/D(31:0)
Addr(3:2)
ALE
t
7a
t
14
t
14
t19
Addr
BE
Data Output
t
16
t
16
Word Address
t
8
t
49
ExtDataEn
WrNear
Last
t
11
t
7
t
7b
t
t
15
t
51
MemStrobe
IOStrobe
Ack
t
50
15
t
47
t
1
t
2
Start ExtendedData Out/
Write Address Ack?
Ack?
Ack
Negate
New
Write Transfer
2905 drw 22
Figure 17. Basic Write to 32-bit Memory Port
27
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
t
7
t15
Wr
A/D(31:0)
Addr(3:0)
ALE
t
7a
t
t
14
16
t
14
Addr
19
Byte N
Byte N+1
'nnnn+1'
Byte N+2
'nnnn+2'
t
t
t
19
16
t
t
19
16
t
16
'nnnn'
t
9
t
t
8
t
49
ExtDataEn
WrNear
Last
t
t
48
7
t
15
t
t
7b
t
52
t
52
t
50
50
50
MemStrobe
IOStrobe
Ack
t
t
51
15
t
51
47
t51
t
t
1
t
1
t1
t
2
t
2
t2
Start Extended Ack
Write Address
Ack
Ack
Negate
New
Write Transaction
2905 drw 23
Figure 18. Tri-Byte Mini-burst Write to 8-bit Port
28
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
t
2
BusReq
BusGnt
A/D(31:0)
Addr(3:0)
Diag
t
1
t
5
t
3
Rd
Wr
ALE
Burst/
WrNear
Last,
BE16(1:0),
MemStrobe
IOStrobe
ExtDataEn
TC
t
45
2905 drw 24
Figure 19. Request and Relinquish of R3041 Bus to External Master
29
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
t
2
BusReq
BusGnt
A/D(31:0)
Addr(3:0)
Diag
t
1
t
6
t
4
Rd
Wr
ALE
Burst/
WrNear
Last,
BE16(1:0)
MemStrobe
IOStrobe
t
46
ExtDataEn
TC
2905 drw 25
Figure 20. R3041 Regaining Bus Mastership
30
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
CPU Bus
Request
BusReq
t
1
t2
t
4
A/D(31:0)
t
6
BusGnt
2905 drw 26
Figure 21. R3041 DMA Pulse Protocol
Run Cycle
Exception Vector
Phi
SysClk
SInt(n)
t
28
t29
2905 drw 27
Figure 22. Synchronized Interrupt Input Timing
Run Cycle
Exception Vector
Phi
SysClk
Int(n)
2905 drw 28
t
30
t31
Figure 23. Direct Interrupt Input Timing
Run Cycle
Capture BrCond
BCzT/F Instruction
Phi
SysClk
SBrCond(n)
2905 drw 29
t
28
t29
Figure 24. Synchronized Branch Condition Input Timing
31
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
SysClk
t
7
t
15
TC
2905 drw 30
Figure 25. TC Output
84 LEAD PLCC (SQUARE)
A
D
D1
A1
PIN 1
C
45° x .045
D3/E3
E1
E
D2/E2
b1
B
e
C1
SEATING PLANE
2905 drw 31
84 d2
NOTES:
DWG #
J84-1
84
1. All dimensions are in inches, unless otherwise noted.
2. BSC—Basic lead Spacing between Centers.
3. D & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004”
at the seating plane.
5. ND & NE represent the number of leads in the D & E directions respec-
tively.
6. D1 & E1 should be measured from the bottom of the package.
7. PLCCispin&formcompatiblewithMQUAD;theMQUADpackageisused
in other RISController family members.
# of Leads
Symbol
Min.
165
Max.
.180
A
A1
.095
.026
.013
.020
.008
1.185
1.150
1.090
.115
B
.032
b1
.021
C
.040
C1
.012
D
1.195
1.156
1.130
D1
D2/E2
D3/E3
E
1.000 REF
1.185
1.150
1.195
1.156
E1
e
.050 BSC
21
ND/NE
2905 tbl 13
32
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
100-PIN TQFP
Draft Angle = 12°
100
A1
A3
1
e
A2
0.30 Rad Typ.
100-Pin
TQFP
E1 E
0.20 Rad Typ.
6° ± 4°
Standoff 0.05 Min
A
D1
D
L
B
Max 0.102 Lead
Coplanarity
DWG #
TQFP
100
# of Leads
Symbol
A
Min.
Max.
1.60
—
A1
A2
D
0.5
0.15
1.35
15.75
13.95
15.75
13.95
0.45
1.45
16.25
14.05
16.25
14.05
0.70
D1
E
E1
L
N
100
e
0.50BSC
b
0.17
—
0.27
0.08
0.08
0.20
—
ccc
ddd
R
—
0.08
0.08
0
R1
θ
7.0
θ1
θ2
c
11.0
11.0
0.09
13.0
13.0
0.16
2905 tbl 14
33
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX
—
XX
X
X
IDT
Device Type
Speed Package
Process/
Temp. Range
Blank
Commercial Temperature
Range
'J'
84-Pin PLCC
'PF'
100-Pin TQFP
'16'
'20'
'25'
'33'
16.67MHz
20.00MHz
25.00MHz
33.00MHz
79R3041
5.0V Integrated RISController for
Low-Cost Systems
79RV3041
3.3V Integrated RISController for
Low-Cost Systems
2905 drw 32
VALID COMBINATIONS
IDT 79R3041 - 16
79R3041 - 20
TQFP, PLCC Package
TQFP, PLCC Package
TQFP, PLCC Package
PLCC Package Only
TQFP, PLCC Package
TQFP, PLCC Package
TQFP, PLCC Package
TQFP, PLCC Package
79R3041 - 25
79R3041 - 33
79RV3041 - 16
79RV3041 - 20
79RV3041 - 25
79RV3041 - 33
34
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