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IDT79RV3081E-50J [IDT]

RISController with FPA; RISController与FPA
IDT79RV3081E-50J
型号： IDT79RV3081E-50J
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

RISController with FPA
RISController与FPA
文件： 总38页 (文件大小：297K)
中文：  中文翻译
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IDT 79R3081 , 79R3081E  
IDT79R3081  
RISController  
with FPA  
IDT 79RV3081, 79RV3081E  
Integrated Device Technology, Inc.  
• Large on-chip caches with user configurability  
— 16kB Instruction Cache, 4kB Data Cache  
— Dynamically configurable to 8kB Instruction Cache,  
8kB Data Cache  
— Parity protection over data and tag fields  
• Low cost 84-pin packaging  
• Superset pin- and software-compatible with R3051, R3071  
• Multiplexed bus interface with support for low-cost, low-  
speed memory systems with a high-speed CPU  
• On-chip 4-deep write buffer eliminates memory write stalls  
• On-chip 4-deep read buffer supports burst or simple block  
reads  
FEATURES  
• Instruction set compatible with IDT79R3000A, R3041,  
R3051, and R3071 RISC CPUs  
• High level of integration minimizes system cost  
— R3000A Compatible CPU  
— R3010A Compatible Floating Point Accelerator  
— Optional R3000A compatible MMU  
— Large Instruction Cache  
— Large Data Cache  
— Read/Write Buffers  
• 43VUPS at 50MHz  
— 13MFlops  
• Flexible bus interface allows simple, low cost designs  
• Optional 1x or 2x clock input  
• 20 through 50MHz operation  
• On-chip DMA arbiter  
• Hardware-based Cache Coherency Support  
• Programmable power reduction mode  
• Bus Interface can operate at half-processor frequency  
• "V" version operates at 3.3V  
• 50MHz at 1x clock input and 1/2 bus frequency only  
R3081 BLOCK DIAGRAM  
BrCond(3:2,0)  
Master Pipeline Control  
ClkIn  
Clock Generator  
Unit/Clock Doubler  
System Control  
Coprocessor  
(CP0)  
Floating Point  
Coprocessor  
(CP1)  
Integer  
CPU Core  
Exception/Control  
Registers  
General Registers  
(32 x 32)  
Register Unit  
(16 x 64)  
Memory Management  
Registers  
ALU  
Shifter  
Exponent Unit  
Add Unit  
Divide Unit  
Multiply Unit  
Mult/Div Unit  
Translation  
Lookaside Buffer  
(64 entries)  
Int(5:0)  
Address Adder  
PC Control  
Exception/Control  
Virtual Address  
FP Interrupt  
Data Bus  
Physical Address Bus  
32  
Configurable  
Instruction  
Cache  
Configurable  
Data  
36  
Cache  
(4kB/8kB)  
(16kB/8kB)  
Data Bus  
Parity  
Generator  
R3051 Superset Bus Interface Unit  
4-deep  
Read  
Buffer  
4-deep  
Write  
Buffer  
DMA  
Arbiter  
BIU  
Control  
Coherency  
Logic  
Address/  
Data  
DMA  
Ctrl  
Rd/Wr  
Ctrl  
SysClk Invalidate  
Control  
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The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SEPTEMBER 1995  
1995 Integrated Device Technology, Inc.  
5.5  
DSC-9064/4  
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IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
• The R3051, which incorporates 4kB of instruction cache  
and 2kB of data cache, but omits the TLB, and instead uses  
a simpler virtual to physical address mapping.  
• TheR3081E, whichincorporatesa16kBinstructioncache,  
a 4kB data cache, and full function memory management  
unit (MMU) including 64-entry fully associative Translation  
Lookaside Buffer (TLB). The cache on the R3081E is user  
configurable to an 8kB Instruction Cache and 8kB Data  
Cache.  
• The R3081, which incorporates a 16kB instruction cache,  
a 4kB data cache, but uses the simpler memory mapping  
of the R3051/52, and thus omits the TLB. The cache on the  
R3081isuserconfigurabletoan8kBInstructionCacheand  
8kB Data Cache.  
Figure1showsablocklevelrepresentationofthefunctional  
units within the R3081E. The R3081E could be viewed as the  
embodiment of a discrete solution built around the R3000A  
and R3010A. However, by integrating this functionality on a  
singlechip, dramaticcostandpowerreductionsareachieved.  
INTRODUCTION  
The IDT R3051 family is a series of high-performance 32-  
bit microprocessors featuring a high-level of integration, and  
targeted to high-performance but cost sensitive processing  
applications. The R3051 family is designed to bring the high-  
performance inherent in the MIPS RISC architecture into  
low-cost, simplified, power sensitive applications.  
Thus, functional units have been integrated onto the CPU  
core in order to reduce the total system cost, rather than to  
increase the inherent performance of the integer engine.  
Nevertheless, the R3051 family is able to offer 43VUPS  
performance at 50MHz without requiring external SRAM or  
caches.  
The R3081 extends the capabilities of the R3051 family, by  
integrating additional resources into the same pin-out. The  
R3081 thus extends the range of applications addressed by  
the R3051 family, and allows designers to implement a single,  
base system and software set capable of accepting a wide  
variety of CPUs, according to the price/performance goals of  
the end system.  
In addition to the embedded applications served by the  
R3051family,theR3081allowslow-cost,entrylevelcomputer  
systems to be constructed. These systems will offer many  
times the performance of traditional PC systems, yet cost  
approximately the same. The R3081 is able to run any  
standard R3000A operation system, including ACE UNIX.  
Thus, the R3081 can be used to build a low-cost ARC  
compliant system, further widening the range of performance  
solutions of the ACE Initiative.  
An overview of this device, and quantitative electrical  
parameters and mechanical data, is found in this data sheet;  
consult the "R3081 Family Hardware User's Guide" for a  
complete description of this processor.  
CPU Core  
The CPU core is a full 32-bit RISC integer execution  
engine, capable of sustaining close to single cycle execution.  
TheCPUcorecontainsafivestagepipeline,and32orthogonal  
32-bit registers. The R3081 uses the same basic integer  
execution core as the entire R3051 family, which is the  
R3000AimplementationoftheMIPSinstructionset. Thus, the  
R3081 family is binary compatible with the R3051, R3052,  
R3000A, R3001, and R3500 CPUs. In addition, the R4000  
representsanupwardlysoftwarecompatiblemigrationpathto  
still higher levels of performance.  
The execution engine in the R3081 uses a five-stage  
pipeline to achieve near single-cycle instruction execution  
rates. A new instruction can be initiated in each clock cycle;  
the execution engine actually processes five instructions  
concurrently (in various pipeline stages). Figure 2 shows the  
concurrency achieved in the R3081 execution pipeline.  
DEVICE OVERVIEW  
As part of the R3051 family, the R3081 extends the offering  
of a wide range of functionality in a compatible interface. The  
R3051 family allows the system designer to implement a  
singlebasesystem,andutilizeinterface-compatibleprocessors  
of various complexity to achieve the price-performance goals  
of the particular end system.  
Differences among the various family members pertain to  
theon-chipresourcesoftheprocessor.Currentfamilymembers  
include:  
• TheR3052E, whichincorporatesan8kBinstructioncache,  
a 2kB data cache, and full function memory management  
unit (MMU) including 64-entry fully associative Translation  
Lookaside Buffer (TLB).  
• The R3052, which also incorporates an 8kB instruction  
cache and 2kB data cache, but does not include the TLB,  
and instead uses a simpler virtual to physical address  
mapping.  
System Control Co-Processor  
The R3081 family also integrates on-chip the System  
ControlCo-processor,CP0.CP0managesboththeexception  
handling capability of the R3081, as well as the virtual to  
physical address mapping.  
As with the R3051 and R3052, the R3081 offers two  
versions of memory management and virtual to physical  
address mapping: the extended architecture versions, the  
R3051E, R3052E, and R3081E, incorporate the same MMU  
as the R3000A. These versions contain a fully associative 64-  
entry TLB which maps 4kB virtual pages into the physical  
address space. The virtual to physical mapping thus includes  
kernel segments which are hard-mapped to physical  
addresses, and kernel and user segments which are mapped  
page by page by the TLB into anywhere in the 4GB physical  
address space. In this TLB, 8 pages can be “locked” by the  
kerneltoinsuredeterministicresponseinreal-timeapplications.  
Figure 3 illustrates the virtual to physical mapping found in the  
R3081E.  
• The R3051E, which incorporates 4kB of instruction cache  
and 2kB of data cache, along with the full function MMU/  
TLB of the R3000A.  
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MILITARY AND COMMERCIAL TEMPERATURE RANGES  
The extended architecture versions of the R3051 family  
(theR3051E,R3052E,andR3081E)allowthesystemdesigner  
to implement kernel software which dynamically manages  
user task utilization of system resources, and also allows the  
Kernel to protect certain resources from user tasks. These  
capabilities are important in general computing applications  
such as ARC computers, and are also important in a variety of  
embeddedapplications,fromprocesscontrol(whereprotection  
may be important) to X-Window display systems (where  
virtual memory management can be used). The MMU can  
also be used to simplify system debug.  
I#1  
IF  
RD ALU MEM WB  
I#2  
IF  
RD ALU MEM WB  
I#3  
IF  
RD ALU MEM WB  
I#4  
IF  
RD ALU MEM WB  
I#5  
IF  
RD ALU MEM WB  
R3051familybaseversions(theR3051,R3052,andR3081)  
remove the TLB and institute a fixed address mapping for the  
varioussegmentsofthevirtualaddressspace. Thesedevices  
still support distinct kernel and user mode operation, but do  
not require page management software, leading to a simpler  
software model. The memory mapping used by these devices  
is shown in Figure 4. Note that the reserved spaces are for  
compatiblity with future family members, which may map on-  
chip resources to these addresses. References to these  
addresses in the R3081 will be translated in the same fashion  
as the rest of their respective segments, with no traps or  
exceptions signalled.  
When using the base versions of the architecture, the  
system designer can implement a distinction between the  
user tasks and the kernel tasks, without having to implement  
page management software. This distinction can be  
implemented by decoding the output physical address. In  
systems which do not need memory protection, and wish to  
have the kernel and user tasks operate out of the same  
memory space, high-order address lines can be ignored by  
the address decoder, and thus all references will be seen in  
the lower gigabyte of the physical address space.  
Current  
CPU  
Cycle  
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Figure 2. R3081 5-Stage Pipeline  
VIRTUAL  
PHYSICAL  
0xffffffff  
0xc0000000  
Kernel Mapped  
(kseg2)  
Any  
Kernel Uncached  
(kseg1)  
Physical  
Memory  
3548MB  
0xa0000000  
0x80000000  
Kernel Cached  
(kseg0)  
User Mapped  
Cacheable  
(kuseg)  
Any  
Floating Point Co-Processor  
Memory  
The R3081 also integrates an R3010A compatible floating  
point accelerator on-chip. The FPA is a high-performance co-  
processor (co-processor 1 to the CPU) providing separate  
add, multiply, and divide functional units for single and double  
precisionfloatingpointarithmetic.Thefloatingpointaccelerator  
features low latency operations, and autonomous functional  
units which allow differing types of floating point operations to  
function concurrently with integer operations. The R3010A  
appears to the software programmer as a simple extension of  
the integer execution unit, with 16 dedicated 64-bit floating  
pointregisters(softwarereferencestheseas3232-bitregisters  
when performing loads or stores). Figure 5 illustrates the  
functional block diagram of the on-chip FPA.  
512 MB  
0x00000000  
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Figure 3. Virtual to Physical Mapping of Extended Architecture  
Versions  
VIRTUAL  
PHYSICAL  
0xffffffff  
0xc0000000  
1MB Kernel Rsvd  
Kernel Cacheable  
Tasks  
Kernel Cached  
(kseg2)  
1024 MB  
Kernel Uncached  
(kseg1)  
0xa0000000  
0x80000000  
Kernel/User  
Cacheable  
Tasks  
Kernel Cached  
(kseg0)  
2048 MB  
512 MB  
Clock Generator Unit  
The R3081 is driven from a single input clock which can be  
eitherattheprocessorratedspeed, orattwicethatspeed. On-  
chip, the clock generator unit is responsible for managing the  
interaction of the CPU core, caches, and bus interface. The  
R3081 includes an on-chip clock doubler to provide higher  
frequency signals to the internal execution core; if 1x clock  
mode is selected, the clock doubler will internally convert it to  
1MB User Rsvd  
User  
Cached  
(kuseg)  
Inaccessible  
Kernel Boot  
and I/O  
512 MB  
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0x00000000  
Figure 4. Virtual to Physical Mapping of Base Architecture Versions  
5.5  
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IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
a double frequency clock. The 2x clock mode is provided for theperformanceinherentintheR3081. Aswiththeinstruction  
compatiblitywiththeR3051.Theclockgeneratorunitreplaces cache, the data cache is implemented as a direct mapped  
theexternaldelaylinerequiredinR3000A basedapplications. physicaladdresscache. Thecacheiscapableofmappingany  
word within the 4GB physical address space.  
Instruction Cache  
The data cache is implemented as a write-through cache,  
The R3081 implements a 16kB Instruction Cache. The to insure that main memory is always consistent with the  
system may choose to repartition the on-chip caches, so that internal cache. In order to minimize processor stalls due to  
the instruction cache is reduced to 8kB but the data cache is data write operations, the bus interface unit incorporates a 4-  
increased to 8kB. The instruction cache is organized with a deep write buffer which captures address and data at the  
line size of 16bytes (four entries). This large cache achieves processor execution rate, allowing it to be retired to main  
hitratesinexcessof98%inmostapplications,andsubstantially memory at a much slower rate without impacting system  
contributes to the performance inherent in the R3081. The performance. Further, support has been provided to allow  
cache is implemented as a direct mapped cache, and is hardware based data cache coherency in a multi-master  
capableofcachinginstructionsfromanywherewithinthe4GB environment, such as one utilizing DMA from I/O to memory.  
physical address space. The cache is implemented using  
physical addresses (rather than virtual addresses), and thus fields.Parityisgeneratedbythereadbufferduringcacherefill;  
does not require flushing on context switch. duringcachereferences,theparityischecked,andinthecase  
The data cache is parity protected over the data and tag  
Theinstructioncacheisparityprotectedovertheinstruction of a parity error, a cache miss is processed.  
word and tag fields. Parity is generated by the read buffer  
during cache refill; during cache references, the parity is Bus Interface Unit  
checked, and in the case of a parity error, a cache miss is  
processed.  
The R3081 uses its large internal caches to provide the  
majority of the bandwidth requirements of the execution  
engine, and thus can utilize a simple bus interface connected  
to slower memory devices. Alternately, a high-performance,  
Data Cache  
The R3081 incorporates an on-chip data cache of 4kB, low-cost secondary cache can be implemented, allowing the  
organized as a line size of 4 bytes (one word). The R3081 processor to increase performance in systems where bus  
allows the system to reconfigure the on-chip cache from the bandwidth is a performance limitation.  
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and  
8kB of Data caches.  
AspartoftheR3051family,theR3081businterfaceutilizes  
a 32-bit address and data bus multiplexed onto a single set of  
The relatively large data cache achieves hit rates in excess pins. The bus interface unit also provides an ALE (Address  
of 95% in most applications, and contributes substantially to Latch Enable) output signal to de-multiplex the A/D bus, and  
Cache  
Data Bus  
Data  
(32)  
(32)  
Instructions  
Operands  
Register Unit (16 X 64)  
Exponent Part  
Fraction  
Condition  
Codes  
(11)  
(11)  
(11)  
(53)  
(53)  
(53)  
A
B
Result  
A
B
Result  
Add Unit  
Exponent  
Unit  
Round  
Control Unit  
and Clocks  
(53)  
(53)  
(53)  
(56)  
A
A
B
B
Result  
Divide Unit  
(53)  
(56)  
Result  
Multiply Unit  
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Figure 5. FPA Functional Block Diagram  
5.5  
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IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
simple handshake signals to process CPU read and write to a given application, the system design engineer could  
requests. Inadditiontothereadandwriteinterface, theR3051 include true burst support from the DRAM to provide for high-  
family incorporates a DMA arbiter, to allow an external master performance cache miss processing, or utilize a simpler,  
to control the external bus.  
lowerperformancememorysystemtoreducecostandsimplify  
TheR3081alsosupportshardwarebasedcachecoherency the design. Similarly, the system designer could choose to  
during DMA writes. The R3081 can invalidate a specified line implement techniques such as external secondary cache, or  
of data cache, or in fact can perform burst invalidations during DMA, to further improve system performance.  
burst DMA writes.  
The R3081 incorporates a 4-deep write buffer to decouple  
DEVELOPMENT SUPPORT  
the speed of the execution engine from the speed of the  
memorysystem. ThewritebufferscaptureandFIFOprocessor  
address and data information in store operations, and present  
it to the bus interface as write transactions at the rate the  
memory system can accommodate.  
The R3081 read interface performs both single datum  
reads and quad word reads. Single reads work with a simple  
handshake, and quad word reads can either utilize the simple  
handshake (in lower performance, simple systems) or utilize  
atightertimingmodewhenthememorysystemcanburstdata  
at the processor clock rate. Thus, the system designer can  
choose to utilize page or nibble mode DRAMs (and possibly  
use interleaving, if desired, in high-performance systems), or  
use simpler techniques to reduce complexity.  
In order to accommodate slower quad word reads, the  
R3081 incorporates a 4-deep read buffer FIFO, so that the  
external interface can queue up data within the processor  
before releasing it to perform a burst fill of the internal caches.  
TheR3081isR3051supersetcompatibleinitsbusinterface.  
Specifically, the R3081 has additional support to simplify the  
design of very high frequency systems. This support includes  
the ability to run the bus interface at one-half the processor  
execution rate, as well as the ability to slow the transitions  
between reads and writes to provide extra buffer disable time  
for the memory interface. However, it is still possible to design  
a system which, with no modification to the PC Board or  
software, canaccepteitheranR3041, R3051, R3052, R3071,  
or R3081.  
The IDT R3051 family is supported by a rich set of  
development tools, ranging from system simulation tools  
through PROM monitor and debug support, applications  
software and utility libraries, logic analysis tools, sub-system  
modules, and shrink wrap operating systems. The R3081,  
which is pin and software compatible with the R3051, can  
directly utilize these existing tools to reduce time to market.  
Figure7isanoverviewofthesystemdevelopmentprocess  
typically used when developing R3051 family applications.  
The R3051 family is supported in all phases of project  
development. These tools allow timely, parallel development  
of hardware and software for R3051 family applications, and  
include tools such as:  
• OptimizingcompilersfromMIPS,theacknowledgedleader  
in optimizing compiler technology.  
• Cross development tools, available in a variety of  
development environments.  
• The IDT Evaluation Board, which includes RAM, EPROM,  
I/O, and the IDT PROM Monitor.  
• IDT/sim , which implements a full prom monitor  
(diagnostics, remote debug support, peek/poke, etc.).  
• IDT/kit , which implements a run-time support package for  
R3051 family systems.  
PERFORMANCE OVERVIEW  
TheR3081achievesaveryhigh-levelofperformance. This  
performance is based on:  
• An efficient execution engine. The CPU performs ALU  
operations and store operations in a single cycle, and has  
an effective load time of 1.3 cycles, and branch execution  
rate of 1.5 cycles (based on the ability of the compilers to  
avoid software interlocks). Thus, the execution engine  
achieves over 35 VUPS performance when operating out  
of cache.  
• Afullfeaturedfloatingpointaccelerator/co-processor.  
The R3081 incorporates an R3010A compatible floating  
pointacceleratoron-chip,withindependentALUsforfloating  
point add, multiply, and divide. The floating point unit is fully  
hardware interlocked, and features overlapped operation  
and precise exceptions. The FPA allows floating point  
adds, multiplies, and divides to occur concurrently with  
each other, as well as concurrently with integer operations.  
• Largeon-chipcaches.TheR3051familycontainscaches  
which are substantially larger than those on the majority of  
today’smicroprocessors. Theselargecachesminimizethe  
number of bus transactions required, and allow the R3051  
family to achieve actual sustained performance very close  
to its peak execution rate. The R3081 doubles the cache  
available on the R3052, making it a suitable engine for  
SYSTEM USAGE  
The IDT R3051 family has been specifically designed to  
allow a wide variety of memory systems. Low-cost systems  
can use slow speed memories and simple controllers, while  
otherdesignersmaychoosetoincorporatehigherfrequencies,  
faster memories, and techniques such as DMA to achieve  
maximum performance. The R3081 includes specific support  
for high perfromance systems, including signals necessary to  
implement external secondary caches, and the ability to  
perform hardware based cache coherency in multi-master  
systems.  
Figure 6 shows a typical system implementation.  
Transparent latches are used to de-multiplex the R3081  
address and data busses from the A/D bus. The data paths  
between the memory system elements and the A/D bus is  
managed by simple octal devices. A small set of simple PALs  
is used to control the various data path elements, and to  
control the handshake between the memory devices and the  
CPU.  
Dependingonthecostvs.performancetradeoffsappropriate  
5.5  
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IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
ClkIn  
IDT R3081  
RISController  
Address/Data  
Control  
R3051  
Local Bus  
DRAM  
Controller  
I/O Controller  
PROM  
I/O  
I/O  
DRAM  
DRAM  
IDT73720  
Bus Exchanger  
2889 drw 06  
Figure 6. R3081 RISChipset Based System  
System  
Architecture  
Evaluation  
System  
Development  
Phase  
System  
Integration  
and Verfification  
Software  
DBG Debugger  
PIXIE Profiler  
MIPS Compiler Suite  
Stand-Alone Libraries  
Floating Point Library  
Cross Development Tools  
Adobe PostScript PDL  
MicroSoft TrueImage PDL  
PeerlessPage Printer OS  
X-Server  
Logic Analysis  
Diagnostics  
IDT/sim  
Cache-3051  
SPP  
Benchmarks  
IDT/kit  
Evaluation Board  
Laser Printer System  
X-Terminal System  
In-Circuit Emulation  
Remote Debug  
Real-Time OS  
Hardware  
Hardware Models  
General CAD Tools  
Evaluation Board  
Laser Printer System  
Support Chips  
2889 drw 07  
Figure 7. R3051 Family Development Toolchain  
5.5  
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IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
many general purpose computing applications, such as  
ARC compliant systems.  
isallowedfortransitionsbetweenmemoryandtheprocessor  
on the multiplexed address/data bus.  
• Autonomousmultiplyanddivideoperations.TheR3051 • Configurable cache. The R3081 allows the system  
family features an on-chip integer multiplier/divide unit  
which is separate from the other ALU. This allows the CPU  
toperformmultiplyordivideoperationsinparallelwithother  
designer to use software to select either a 16kB Instruction  
Cache/4kBDataCacheorganization,oran8kBInstruction/  
8kB Data Cache organization.  
integer operations, using a single multiply or divide • Cache Coherent Interface. The R3081 has an optional  
instruction rather than “step” operations.  
• Integrated write buffer. The R3081 features a four deep  
write buffer, which captures store target addresses and  
hardware based cache coherency interface intended to  
support multi-master systems such as those utilizing DMA  
between memory and I/O.  
data at the processor execution rate and retires it to main • Optional 1x or 2x clock input. The R3081 can be driven  
memoryattheslowermainmemoryaccessrate. Useofon-  
chip write buffers eliminates the need for the processor to  
stall when performing store operations.  
with an R3051 compatible 2x clock input, or a lower  
frequency 1x clock input.  
• Burstreadsupport.TheR3051familyenablesthesystem  
designer to utilize page mode or nibble mode RAMs when  
performing read operations to minimize the main memory  
read penalty and increase the effective cache hit rates.  
Thesetechniquescombinetoallowtheprocessortoachieve  
over 43 VUPS integer performance, 13MFlops of Linpack  
performance,and70,000dhrystoneswithouttheuseofexternal  
caches or zero wait-state memory devices.  
The performance differences between the various family  
members depends on the application software and the design  
of the memory system. The impact of the various cache sizes,  
and the hardware floating point, can be accurately modeled  
using Cache-3051. Since the R3041, R3051, R3052, R3071,  
and R3081 are all pin and software compatible, the system  
designer has maximum freedom in trading between  
performance and cost. A system can be designed, and later  
theappropriateCPUinsertedintotheboard,dependingonthe  
desired system performance.  
THERMAL CONSIDERATIONS  
TheR3081utilizesspecialpackagingtechniquestoimprove  
the thermal properties of high-speed processors. Thus, the  
R3081 is packaged using cavity down packaging, with an  
embedded thermal slug to improve thermal transfer to the  
suurrounding air.  
The R3081 utilizes the 84-pin MQUAD package (the "MJ"  
package), which is an all aluminum package with the die  
attached to a normal copper lead-frame mounted to the  
aluminumcasing.TheMQUADpackageallowsforan efficient  
thermal transfer between the die and the case due to the heat  
spreading effect of the aluminum. The aluminum offers less  
internal resistance from one end of the package to the other,  
reducing the temperature gradient across the package and  
therefore presenting a greater area for convection and  
conduction to the PCB for a given temperature. Even nominal  
amounts of airflow will dramatically reduce the junction  
temperature of the die, resulting in cooler operation. The  
MQUADpackageisavailableatallfrequencies, andispinand  
form compatible with the PLCC used for the R3051. Thus,  
SELECTABLE FEATURES  
The R3081 allows the system designer to configure certain designerscaninter-changeR3081sandR3051sinaparticular  
aspects of operation. Some of these options are established design, without changing their PC Board.  
when the device is reset, while others are enabled via the  
Config registers:  
The R3081 is guaranteed in a case temperature range of  
0°C to +85°C. The type of package, speed (power) of the  
• BigEndian vs. LittleEndian Byte Ordering. The part can device, and airflow conditions, affect the equivalent ambient  
be configured to operate with either byte ordering. ACE/ temperature conditions which will meet this specification.  
ARC systems typically use Little Endian byte ordering.  
The equivalent allowable ambient temperature, TA, can be  
However,variousembeddedapplications,writtenoriginally calculated using the thermal resistance from case to ambient  
for a Big Endian processor such as the MC680x0, are (ØCA) of the given package. The following equation relates  
easier to port to a Big Endian system.  
ambient and case temperatures:  
• Data Cache Refill of one or four words. The memory  
system must be capable of performing four word refills of  
instruction cache misses. The R3081 allows the system  
designer to enable D-Cache refill of one or four words  
dynamically. Thus, specialized algorithms can choose one  
refill size, while the rest of the system can operate with the  
other.  
• Half-frequency bus mode. The processor can be  
configured such that the external bus interface is at one-  
half the frequency of the processor core. This simplifies  
system design; however, the large on-chip caches mitigate  
theperformanceimpactofusingaslowersystembusclock.  
• Slow bus turn-around. The R3081 allows the system  
designer to space processor operations, so that more time  
TA = TC - P * ØCA  
where P is the maximum power consumption at hot  
temperature,calculatedbyusingthemaximumIccspecification  
for the device.  
Typical values for ØCA at various airflows are shown in  
Table 1.  
Note that the R3081 allows the operational frequency to be  
turneddownduringidleperiodstoreducepowerconsumption.  
This operation is described in the R3081 Hardware User's  
Guide. Reducingtheoperationfrequencydramaticallyreduces  
power consumption.  
5.5  
7
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
minimize skew due to slow rise or fall times. A typical part will  
have less than 2ns rise or fall (10% to 90% signal times) when  
driving the test load.  
Therefore, the system designer should use care when  
designing for direct SysClk use. Total loading (due to devices  
connected on the signal net and the routing of the net itself)  
should be minimized to ensure the SysClk output has a  
smooth and rapid transition. Long rise and/or fall times may  
cause a degradation in the speed capability of an individual  
device.  
Similarly, theR3081employsfeedbackonitsALEoutputto  
ensure adequate address hold time to ALE. The system  
designer should be careful when designing the ALE net to  
minimizetotalloadingandtominimizeskewbetweenALEand  
the A/D bus, which will ensure adequate address access latch  
time.  
IDT's field and factory applications groups can provide the  
system designer with assistance for these and other design  
issues.  
ØCA  
400  
12  
Airflow (ft/min)  
"MJ" Package*  
PLCC Package  
0
200  
14  
600  
11  
800  
9
1000  
22  
29  
8
26  
21  
18  
16  
15  
2889 tbl 01  
Table 1. Thermal Resistance (ØCA) at Various Airflows  
(*estimated: final values tbd)  
NOTES ON SYSTEM DESIGN  
The R3081 has been designed to simplify the task of high-  
speedsystemdesign.Thus,set-upandhold-timerequirements  
have been kept to a minimum, allowing a wide variety of  
system interface strategies.  
To minimize these AC parameters, the R3081 employs  
feedback from its SysClk output to the internal bus interface  
unit. This allows the R3081 to reference input signals to the  
reference clock seen by the external system. The SysClk  
output is designed to provide relatively large AC drive to  
5.5  
8
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN DESCRIPTION  
PIN NAME  
I/O  
DESCRIPTION  
A/D(31:0)  
I/O  
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction  
in one phase, and which is used to transmit data between the CPU and external memory resources during  
the rest of the transfer.  
Bus transactions on this bus are logically separated into two phases: during the first phase, information  
about the transfer is presented to the memory system to be captured using the ALE output. This  
information consists of:  
Address(31:4):  
(3:0):  
The high-order address for the transfer is presented on A/D(31:4).  
These strobes indicate which bytes of the 32-bit bus will be involved in  
the transfer, and are presented on A/D(3:0).  
BE  
During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.  
On read cycles, the bus receives the data from the external resource, in either a single data transaction  
or in a burst of four words, and places it into the on-chip read buffer.  
During cache coherency operations, the R3081 monitors the A/D bus at the start of a DMA write to capture  
the write target address for potential data cache invalidates.  
Addr(3:2)  
Diag(1)  
O
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.  
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes  
or single datum reads) or functions as a two bit counter starting at ‘00’ for burst read operations.  
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA write to  
capture the write target address for potential data cache invalidates.  
Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-chip  
cache miss, and also presents part of the miss address. The value output on this pin is time multiplexed:  
Cached:  
DuringthephaseinwhichtheA/Dbuspresentsaddressinformation, this  
pin is an active HIGH output which indicates whether the current read is  
a result of a cache miss.  
Miss Address (3):  
During the remainder of the read operation, this output presents address  
bit(3)oftheaddresstheprocessorwasattemptingtoreferencewhenthe  
cache miss occurred. Regardless of whether a cache miss is being  
processed, this pin reports the transfer address during this time.  
On write cycles, this output signals whether the data being written as retained in the on-chip data cache.  
The value of this pin is time multiplexed during writes:  
Cached:  
During the address phase of write transactions, this signal is an active  
highoutputwhichindicatesthatthestoredatawasretainedintheon-chip  
data cache.  
Reserved:  
The value of this pin during the data phase of writes is reserved.  
Diag(0)  
O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those  
due to data references, and presents the remaining bit of the miss address. The value output on this  
pin is also time multiplexed:  
I/ :  
D
If the “Cached” Pin indicates a cache miss, then a high on this pin at this  
time indicates an instruction reference, and a low indicates a data  
reference. If the read is not due to a cache miss but rather an uncached  
reference, then this pin is undefined during this phase.  
Miss Address (2):  
During the remainder of the read operation, this output presents  
address bit (2) of the address the processor was attempting to  
reference when the cache miss occurred. Regardless of whether a  
cache miss is being processed, this pin reports the transfer address  
during this time.  
During write cycles, the value of this pin during both the address and data phases is reserved.  
2889 tbl 02  
5.5  
9
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN DESCRIPTION (Continued):  
PIN NAME  
ALE  
I/O  
DESCRIPTION  
I/O  
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus  
transaction. This signal is used by external logic to capture the address for the transfer, typically using  
transparent latches.  
During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to capture the write  
target address for potential data cache invalidates.  
Rd  
Wr  
O
Read: An output which indicates that the current bus transaction is a read.  
I/O  
Write: An output which indicates that the current bus transaction is a write. During coherent DMA, this input  
indicates that the current transfer is a write.  
DataEn  
O
O
External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor during  
read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus  
without having a bus conflict occur. During write cycles, or when no bus transaction is occurring, this signal is  
negated, thus disabling the external memory drivers  
Burst/  
WrNear  
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read is  
requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to  
cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles if quad word refill  
is currently selected.  
On write transactions, the WrNear output tells the external memory system that the bus interface unit is  
performing back-to-back write transactions to an address within the same 512 word page as the prior write  
transaction. This signal is useful in memory systems which employ page mode or static column DRAMs, and  
allows near writes to be retired quickly.  
Ack  
I
Acknowledge: An input which indicates to the device that the memory system has sufficiently processed the  
bus transaction, and that the CPU may either terminate the write cycle or process the read data from this read  
transfer.  
During Coherent DMA, this input indicates that the current write transfer is completed, and that the internal  
invalidation address counter should be incremented.  
RdCEn  
SysClk  
I
Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed valid  
data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer.  
O
System Reference Clock: An output from the CPU which reflects the timing of the internal processor "Sys"  
clock. This clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus  
interface unit. This clock will either be at the same frequency as the CPU execution rate clock, or at one-half  
that frequency, as selected during reset.  
BusReq  
BusGnt  
IvdReq  
CohReq  
I
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals  
so that they may be driven by an external master.  
O
I
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that aBusReq has been detected, and  
that the bus is relinquished to the external master.  
Invalidate Request. An input provided by an external DMA controller to request that the CPU invalidate the  
Data Cache line corresponding to the current DMA write target address. This signal is the same pin as Diag(0)  
I
Coherent DMA Request. An input used by the external DMA controller to indicate that the requested DMA  
operations could involve hardware cache coherency. This signal is the Rsvd(0) of the R3051.  
SBrCond(3:2)  
BrCond(0)  
I
Branch Condition Port: These external signals are internally connected to the CPU signals CpCond(3:0).  
These signals can be used by the branch on co-processor condition instructions as input ports. There are two  
types of Branch Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs, and  
thus may be driven by asynchronous agents. The direct Branch Condition inputs must be driven synchronously.  
Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.  
BusError  
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal  
is only sampled during read and write operations. If the bus transaction is a read operation, then the CPU will  
take a bus error exception.  
2889 tbl 03  
5.5  
10  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN DESCRIPTION (Continued):  
PIN NAME  
I/O  
DESCRIPTION  
Int(5:3)  
I
Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0) SInt(2:0)  
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but in a  
different (simpler) fashion than the interrupt signals of the R3000.  
There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor, and may  
be driven by an asynchronous external agent. The direct interrupt inputs are not internally synchronized, and  
thus must be externally synchronized to the CPU. The direct interrupt inputs have one cycle lower latency than  
the synchronized interrupts. Note that the interrupt used by the on-chip FPA will not be monitored externally.  
ClkIn  
I
I
Master Clock Input: This input clock can be provided at the execution frequency of the CPU (1x clock mode)  
or at twice that frequency (2x clock mode), as selected at reset.  
Reset  
Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last cycle  
of Reset.  
Rsvd(4:1)  
I/O  
Reserved: These four signal pins are reserved for testing and for future revisions of this device. Users must not  
connect these pins. Note that Rsvd(0) of the R3051 is now used for the CohReq input pin.  
2889 tbl 04  
ABSOLUTE MAXIMUM RATINGS(1, 3)  
AC TEST CONDITIONS—R3081  
Symbol  
Rating  
Commercial  
Military  
Unit  
Symbol  
Parameter  
Min.  
3.0  
—
Max.  
—
0
Unit  
V
VTERM  
Terminal Voltage  
with Respect  
to GND  
–0.5 to +7.0 –0.5 to +7.0  
V
VIH  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
VIL  
V
TC  
Operating Case  
Temperature  
0 to +85  
–55 to +125 °C  
VIHS  
VILS  
3.5  
—
—
0
V
TBIAS  
TSTG  
Case Temperature –55 to +125 –65 to +135 °C  
Under Bias  
V
2889 tbl 06  
Storage  
–55 to +125 –65 to +155 °C  
AC TEST CONDITIONS—RV3081  
Temperature  
Symbol  
Parameter  
Min.  
3.0  
—
Max.  
—
0
Unit  
V
VIN  
Input Voltage  
–0.5 to +7.0 –0.5 to +7.0  
V
VIH  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
2889 tbl 05  
NOTES:  
VIL  
V
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS  
may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions  
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot  
implied. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
VIHS  
VILS  
3.0  
—
—
0
V
V
2889 tbl 06  
2. VIN minimum = –3.0V for pulse width less than 15ns.  
VIN should not exceed VCC +0.5V.  
3. Notmorethanoneoutputshouldbeshortedatatime. Durationoftheshort  
should not exceed 30 seconds.  
OUTPUT LOADING FOR AC TESTING  
+4mA  
VREF  
–
To Device  
Under Test  
RECOMMENDED OPERATING  
TEMPERATURE AND SUPPLY VOLTAGE  
+
+1.5V  
CLD  
Grade  
Temperature(Case)  
GND  
VCC  
Military  
–55°C to +125°C  
0V  
5.0 ±10%  
–4mA  
2889 drw 08  
Commercial  
Commercial  
0°C to +85°C  
0°C to +85°C  
0V  
0V  
5.0 ±5%  
3.3 ±5%  
Signal  
SysClk  
CLD  
50 pf  
25 pf  
2889 tbl 07  
All Others  
2889 tbl 08  
5.5  
11  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
DC ELECTRICAL CHARACTERISTICS RV3081  
COMMERCIAL TEMPERATURE RANGE(1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
20MHz  
Max.  
25MHz  
Symbol  
VOH  
VOL  
VIH  
Parameter  
Test Conditions  
Min.  
2.4  
—
Min.  
2.4  
—
Max.  
—
Units  
V
Output HIGH Voltage  
Output LOW Voltage  
VCC = Min., IOH = –4mA  
—
0.4  
—
VCC = Min., IOL = 4mA  
0.4  
—
V
(3)  
Input HIGH Voltage  
—
2.0  
—
2.0  
—
V
(1)  
VIL  
Input LOW Voltage  
—
0.8  
—
0.8  
—
V
(2,3)  
VIHS  
VILS  
CIN  
Input HIGH Voltage  
—
2.8  
—
2.8  
—
V
(1,2)  
Input LOW Voltage  
—
0.4  
10  
0.4  
10  
V
(4,5)  
Input Capacitance  
—
—
—
—
pF  
pF  
mA  
µA  
µA  
µA  
(4,5)  
COUT  
ICC  
Output Capacitance  
—
10  
—
10  
Operating Current  
Input HIGH Leakage  
Input LOW Leakage  
Output Tri-state Leakage  
VCC = 3.3V, TA = 25°C  
VIH = VCC  
—
375  
100  
—
—
425  
100  
—
IIH  
—
—
IIL  
VIL = GND  
–100  
–100  
–100  
–100  
IOZ  
VOH = 2.4V, VOL = 0.5V  
100  
100  
NOTES:  
2889 tbl 09  
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.  
2. VIHS and VILS apply to CIkIn and Reset.  
3. VIH should not be held above VCC + 0.5V.  
4. Guaranteed by design.  
5. ALE is 12pF for SysClk values CIN and COUT for all speeds.  
AC ELECTRICAL CHARACTERISTICS RV3081  
COMMERCIAL TEMPERATURE RANGE (1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
20MHz  
25MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
RdCEn, CohReq  
Set-up to SysClk rising  
6
—
5
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
Hold from SysClk rising  
7
4
—
—
6
4
—
—
ns  
ns  
BusReq, Ack, BusError,  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
2
—
2
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Tri-state from SysClk rising  
—
10  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Driven from SysClk falling  
—
10  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
2
8
8
—
—
—
—
—
2
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
5
5
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated(3)  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
4
4
t9  
ALE  
4
4
t10  
t11  
t12  
t14  
t15  
t16  
t17  
A/D  
—
15  
—
—
7
—
15  
—
—
6
DataEn  
DataEn  
A/D  
—
0
—
0
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
—
—
—
—
Addr(3:2)  
Diag  
Valid from SysClk  
Valid from SysClk  
6
6
12  
11  
5.5  
12  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS RV3081 (cont.)  
COMMERCIAL TEMPERATURE RANGE(1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
20MHz  
25MHz  
Symbol Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
tsys  
t32  
A/D  
Tri-state from SysClk falling  
—
10  
13  
—
10  
ns  
A/D  
SysClk falling to data valid  
Pulse Width HIGH  
—
10  
10  
25  
200  
32  
6
—
8
12  
—
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
—
Pulse Width LOW  
—
8
—
Clock Period  
250  
—
20  
200  
32  
5
250  
—
Pulse Width from Vcc valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
Pulse Width(5)  
Reset  
—
—
Reset  
—
—
Int  
10  
0
—
9
—
Int  
—
0
—
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
6
—
5
—
3
—
3
—
6
—
5
—
Int, BrCond  
3
—
3
—
SysClk (full frequency mode)  
SysClk (full frequency mode)  
2*t22  
t22-2  
2*t22  
t22+2  
2*t22  
t22-2  
2*t22  
t22+2  
Clock High Time(5)  
t33  
tsys/2  
t34  
SysClk (full frequency mode)  
Clock LOW Time(5)  
t22-2  
t22+2  
4*t22  
2*t22+2  
2*t22+2  
—
t22-2  
t22+2  
4*t22  
2*t22+2  
2*t22+2  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SysClk (half frequency mode) Pulse Width(5)4*t22  
SysClk (half frequency mode) Clock HIGH Time(5)  
SysClk (half frequency mode) Clock LOW Time(5)  
ALESet-up to SysClk falling  
4*t22  
4*t22  
2*t22-2  
2*t22-2  
t35  
2*t22-2  
2*t22-2  
t36  
9
2
8
2
t37  
ALEHold from SysClk falling  
—
—
t38  
A/DSet-up to ALE falling  
10  
2
—
9
—
t39  
A/DHold from ALE falling  
—
2
—
t40  
WrSet-up to SysClk rising  
10  
3
—
9
—
t41  
WrHold from SysClk rising  
—
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
Pulse Width HIGH(6)  
Pulse Width LOW(6)  
Clock Period(6)  
20  
20  
50  
—
—
16  
16  
40  
—
—
t43  
—
—
t44  
50  
50  
tderate  
Timing deration for loading  
1
1
ns/  
25pF  
(3, 4)  
over CLD  
NOTES:  
2889 tbl 11  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.  
5.5  
13  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
DC ELECTRICAL CHARACTERISTICS RV3081  
COMMERCIAL TEMPERATURE RANGE(1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
33MHz  
Max.  
40MHz  
Symbol  
VOH  
VOL  
VIH  
Parameter  
Test Conditions  
Min.  
2.4  
—
Min.  
2.4  
—
Max.  
—
Units  
V
Output HIGH Voltage  
Output LOW Voltage  
VCC = Min., IOH = –4mA  
—
0.4  
—
VCC = Min., IOL = 4mA  
0.4  
—
V
(3)  
Input HIGH Voltage  
—
2.0  
—
2.0  
—
V
(1)  
VIL  
Input LOW Voltage  
—
0.8  
—
0.8  
—
V
(2,3)  
VIHS  
VILS  
CIN  
Input HIGH Voltage  
—
2.8  
—
2.8  
—
V
(1,2)  
Input LOW Voltage  
—
0.4  
10  
0.4  
10  
V
(4,5)  
Input Capacitance  
—
—
—
—
pF  
pF  
mA  
µA  
µA  
µA  
(4,5)  
COUT  
ICC  
Output Capacitance  
—
10  
—
10  
Operating Current  
Input HIGH Leakage  
Input LOW Leakage  
Output Tri-state Leakage  
VCC = 3.3V, TA = 25°C  
VIH = VCC  
—
525  
100  
—
—
600  
100  
—
IIH  
—
—
IIL  
VIL = GND  
–100  
–100  
–100  
–100  
IOZ  
VOH = 2.4V, VOL = 0.5V  
100  
100  
NOTES:  
2889 tbl 09  
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.  
2. VIHS and VILS apply to CIkIn and Reset.  
3. VIH should not be held above VCC + 0.5V.  
4. Guaranteed by design.  
5. ALE is 12pF for SysClk values CIN and COUT for all speeds.  
AC ELECTRICAL CHARACTERISTICS RV3081  
COMMERCIAL TEMPERATURE RANGE (1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
33MHz  
40MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
RdCEn, CohReq3  
Set-up to SysClk rising  
4
—
3
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
Hold from SysClk rising  
5
3
—
—
4.5  
3
—
—
ns  
ns  
BusReq, Ack, BusError,  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
1
—
1
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Tri-state from SysClk rising  
—
10  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Driven from SysClk falling  
—
10  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
1.5  
—
0
6
6
—
—
—
—
—
1.5  
—
0
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
4
3.5  
3
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated(3)  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
3
t9  
ALE  
3
3
t10  
t11  
t12  
t14  
t15  
t16  
t17  
A/D  
—
13  
—
—
5
—
12  
—
—
4
DataEn  
DataEn  
A/D  
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
—
—
—
—
Addr(3:2)  
Diag  
Valid from SysClk  
Valid from SysClk  
5
4.5  
9
10  
5.5  
14  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS RV3081 (cont.)  
COMMERCIAL TEMPERATURE RANGE(1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)  
33MHz  
40MHz  
Symbol Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
tsys  
t32  
A/D  
Tri-state from SysClk falling  
—
9
11  
—
8
ns  
A/D  
SysClk falling to data valid  
Pulse Width HIGH  
—
6.5  
6.5  
15  
200  
32  
4
—
5.6  
5.6  
12.5  
200  
32  
3
10  
—
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
—
Pulse Width LOW  
—
—
Clock Period  
250  
—
250  
—
Pulse Width from Vcc valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
Pulse Width(5)  
Reset  
—
—
Reset  
—
—
Int  
8
—
7
—
Int  
0
—
0
—
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
4
—
3
—
2
—
2
—
4
—
3
—
Int, BrCond  
2
—
2
—
SysClk (full frequency mode)  
SysClk (full frequency mode)  
2*t22  
t22-1  
2*t22  
t22+1  
2*t22  
t22-1  
2*t22  
t22+1  
Clock High Time(5)  
t33  
tsys/2  
t34  
SysClk (full frequency mode)  
Clock LOW Time(5)  
t22-1  
t22+1  
4*t22  
2*t22+1  
2*t22+1  
—
t22-1  
t22+1  
4*t22  
2*t22+1  
2*t22+1  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SysClk (half frequency mode) Pulse Width(5)4*t22  
SysClk (half frequency mode) Clock HIGH Time(5)  
SysClk (half frequency mode) Clock LOW Time(5)  
ALESet-up to SysClk falling  
4*t22  
4*t22  
2*t22-1  
2*t22-1  
t35  
2*t22-1  
2*t22-1  
t36  
7
1
6
1
t37  
ALEHold from SysClk falling  
—
—
t38  
A/DSet-up to ALE falling  
8
—
8
—
t39  
A/DHold from ALE falling  
1
—
1
—
t40  
WrSet-up to SysClk rising  
8
—
7
—
t41  
WrHold from SysClk rising  
3
—
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
Pulse Width HIGH(6)  
Pulse Width LOW(6)  
Clock Period(6)  
13  
13  
30  
—
—
11(6)  
11(6)  
25  
—
—
t43  
—
—
t44  
50  
50  
tderate  
Timing deration for loading  
1
1
ns/  
25pF  
(3, 4)  
over CLD  
NOTES:  
2889 tbl 11  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns  
.
5.5  
15  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
DC ELECTRICAL CHARACTERISTICS R3081  
COMMERCIAL TEMPERATURE RANGE — (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
20MHz  
25MHz  
33.33MHz  
40MHz  
50MHZ  
Symbol  
VOH  
VOL  
Parameter  
Test Conditions  
VCC = Min., IOH = –4mA 3.5  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
Output HIGH Voltage  
Output LOW Voltage  
—
0.4  
—
3.5  
—
—
0.4  
—
3.5  
—
—
0.4  
—
3.5  
—
—
0.4  
—
3.5  
—
—
0.4  
—
V
V
VCC = Min., IOL = 4mA  
—
2.0  
—
(3)  
VIH  
Input HIGH Voltage  
—
2.0  
—
2.0  
—
2.0  
—
2.0  
—
V
(1)  
VIL  
Input LOW Voltage  
—
0.8  
—
0.8  
—
0.8  
—
0.8  
—
0.8  
—
V
(2,3)  
VIHS  
VILS  
CIN  
Input HIGH Voltage  
—
3.0  
—
3.0  
—
3.0  
—
3.0  
—
3.0  
—
V
(1,2)  
Input LOW Voltage  
—
0.4  
10  
0.4  
10  
0.4  
10  
0.4  
10  
0.4  
10  
10  
V
(4)  
Input Capacitance  
—
—
—
—
—
—
—
pF  
pF  
(4)  
COUT Output Capacitance  
—
10  
—
10  
—
10  
—
10  
—
ICC  
IIH  
Operating Current  
VCC = 5V, TA = 25°C  
VIH = VCC  
—
475  
100  
—
—
525  
100  
—
—
625  
100  
—
—
700  
100  
—
—
825 mA  
Input HIGH Leakage  
Input LOW Leakage  
—
—
—
—
—
100  
—
µA  
µA  
IIL  
VIL = GND  
–100  
–100  
–100  
–100  
–100  
IOZ  
Output Tri-state Leakage VOH = 2.4V, VOL = 0.5V –100 100 –100 100 –100 100 –100 100 –100 100  
µA  
2889 tbl 09  
NOTES:  
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.  
2. VIHS and VILS apply to CIkIn and Reset.  
3. VIH should not be held above VCC + 0.5V.  
4. Guaranteed by design.  
5.5  
16  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081  
COMMERCIAL TEMPERATURE RANGE (1, 2) (20, 25MHz)—(TC = 0°C to +85°C, VCC = +5.0V ±5%)  
20MHz  
25MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
Set-up to SysClk rising  
RdCEn, CohReq  
6
—
5
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
7
4
—
—
6
4
—
—
ns  
ns  
BusReq, Ack, BusError,  
Hold from SysClk rising  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
2
—
2
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Tri-state from SysClk rising  
Burst/WrNear, Rd, DataEn  
—
10  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Driven from SysClk falling  
Burst/WrNear, Rd, DataEn  
—
10  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
2
8
8
—
—
—
—
—
2
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
5
5
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated  
4
4
t9  
ALE  
4
4
t10  
t11  
t12  
t14  
t15  
t16  
t17  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
tsys  
t32  
A/D  
—
15  
—
—
7
—
15  
—
—
6
DataEn  
DataEn  
A/D  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
—
0
—
0
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
—
—
—
10  
10  
25  
200  
32  
6
—
—
—
—
—
8
Addr(3:2)  
Valid from SysClk  
6
6
Diag  
Valid from SysClk  
12  
10  
13  
—
—
250  
—
—
—
—
—
—
—
—
—
2*t22  
t22+2  
11  
10  
12  
—
—
250  
—
—
—
—
—
—
—
—
—
2*t22  
t22+2  
A/D  
Tri-state from SysClk falling  
SysClk falling to data valid  
Pulse Width HIGH  
A/D  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
Pulse Width LOW  
8
Clock Period  
20  
200  
32  
5
Pulse Width from VCC valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
Pulse Width(5)  
Reset  
Reset  
Int  
10  
0
9
Int  
0
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
6
5
3
3
6
5
Int, BrCond  
3
3
SysClk (full frequency mode)  
SysClk (full frequency mode)  
2*t22  
t22-2  
2*t22  
t22-2  
Clock HIGH Time(5)  
2889 tbl 10  
NOTES:  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.  
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.  
5.5  
17  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081 (cont.)  
COMMERCIAL TEMPERATURE RANGE(1, 2) (20, 25MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
20MHz  
25MHz  
Symbol  
t33  
Signals  
Description  
Min.  
t22-2  
4*t22  
2*t22-2  
2*t22-2  
9
Max.  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SysClk (full frequency mode) Clock LOW Time(5)  
t22+2  
4*t22  
2*t22+2  
2*t22+2  
—
t22-2  
t22+2  
4*t22  
2*t22+2  
2*t22+2  
—
(5)  
tsys/2  
t34  
SysClk (half frequency mode) Pulse Width  
4*t22  
SysClk (half frequency mode) Clock HIGH Time(5)  
SysClk (half frequency mode) Clock LOW Time(5)  
2*t22-2  
t35  
2*t22-2  
t36  
ALE  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to ALE falling  
Hold from ALE falling  
Set-up to SysClk rising  
Hold from SysClk rising  
Pulse Width HIGH(6)  
Pulse Width LOW(6)  
Clock Period(6)  
8
2
t37  
ALE  
2
—
—
t38  
A/D  
10  
—
9
—
t39  
A/D  
2
—
2
—
t40  
Wr  
10  
—
9
—
t41  
Wr  
3
—
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
20  
—
16  
16  
40  
—
—
t43  
20  
—
—
t44  
50  
50  
50  
tderate  
Timing deration for loading  
—
1
1
ns/  
25pF  
(3, 4)  
over CLD  
NOTES:  
2889 tbl 11  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.  
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.  
AC ELECTRICAL CHARACTERISTICS R3081  
COMMERCIAL TEMPERATURE RANGE (1, 2) (33, 40MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
33MHz  
40MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
RdCEn, CohReq  
Set-up to SysClk rising  
4
—
3
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
Hold from SysClk rising  
5
3
—
—
4.5  
3
—
—
ns  
ns  
BusReq, Ack, BusError,  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
1
—
1
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Tri-state from SysClk rising  
—
10  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Driven from SysClk falling  
—
10  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
1.5  
—
0
6
6
—
—
—
—
—
1.5  
—
0
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
4
3.5  
3
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated  
3
t9  
ALE  
3
3
t10  
t11  
t12  
t14  
t15  
A/D  
—
13  
—
—
5
—
12  
—
—
4
DataEn  
DataEn  
A/D  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
2889 tbl 11  
5.5  
18  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081 (cont.)  
COMERCIAL TEMPERATURE RANGE (1, 2) (33, 40MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
33MHz  
Min.  
40MHz  
Min.  
Symbol  
t16  
Signals  
Addr(3:2)  
Description  
Valid from SysClk  
Max.  
5
Max.  
4.5  
9
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
—
—
—
—
t17  
Diag  
Valid from SysClk  
10  
t18  
A/D  
Tri-state from SysClk falling  
SysClk falling to data valid  
Pulse Width HIGH  
—
9
—
8
t19  
A/D  
—
11  
—
10  
—
t20  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
6.5  
6.5  
15  
200  
32  
4
—
5.6  
5.6  
12.5  
200  
32  
t21  
Pulse Width LOW  
—
—
t22  
Clock Period  
250  
—
250  
—
t23  
Pulse Width from VCC valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
t24  
Reset  
—
—
t25  
Reset  
—
3
t26  
Int  
8
—
7
—
—
t27  
Int  
0
—
0
t28  
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
Int, BrCond  
SysClk (full frequency mode) Pulse Width(5)  
SysClk (full frequency mode) Clock HIGH Time(5)  
SysClk (full frequency mode) Clock LOW Time(5)  
SysClk (half frequency mode) Pulse Width(5)  
SysClk (half frequency mode) Clock HIGH Time(5)  
SysClk (half frequency mode) Clock LOW Time(5)  
4
—
3
—
t29  
2
—
2
—
t30  
4
—
3
—
t31  
2
—
2
—
tsys  
t32  
2*t22  
t22-1  
t22-1  
4*t22  
2*t22-1  
2*t22-1  
7
2*t22  
t22+1  
t22+1  
4*t22  
2*t22+1  
2*t22+1  
—
2*t22  
t22-1  
t22-1  
4*t22  
2*t22-1  
2*t22-1  
6
2*t22  
t22+1  
t22+1  
4*t22  
2*t22+1  
2*t22+1  
—
t33  
tsys/2  
t34  
t35  
t36  
ALE  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to ALE falling  
t37  
ALE  
1
—
1
—
t38  
A/D  
8
—
8
—
t39  
A/D  
Hold from ALE falling  
Set-up to SysClk rising  
Hold from SysClk rising  
Pulse Width HIGH(6)  
1
—
1
—
t40  
Wr  
8
—
7
—
t41  
Wr  
3
—
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
13  
13  
30  
—
—
11(6)  
11(6)  
25  
—
t43  
Pulse Width LOW(6)  
Clock Period(6)  
—
—
t44  
50  
50  
(3, 4)  
tderate  
Timing deration for loading over CLD  
1
—
1
ns/  
25pF  
NOTES:  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2889 tbl 11  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40 and 50MHz.  
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.  
5.5  
19  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081  
COMMERCIAL TEMPERATURE RANGE (1, 2) (50MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
50MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
Set-up to SysClk rising  
RdCEn, CohReq  
5
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
6
4
—
—
ns  
ns  
BusReq, Ack, BusError,  
Hold from SysClk rising  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
2
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Tri-state from SysClk rising  
Burst/WrNear, Rd, DataEn  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Driven from SysClk falling  
Burst/WrNear, Rd, DataEn  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
1.5  
—
0
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
5
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated  
4
t9  
ALE  
4
t10  
t11  
t12  
t14  
t15  
t16  
t17  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
tsys  
t32  
A/D  
—
15  
—
—
6
DataEn  
DataEn  
A/D  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
—
—
—
Addr(3:2)  
Valid from SysClk  
6
Diag  
Valid from SysClk  
11  
10  
12  
A/D  
Tri-state from SysClk falling  
SysClk falling to data valid  
Pulse Width HIGH  
A/D  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
N/A (8)  
N/A (8)  
Pulse Width LOW  
Clock Period  
N/A (7, 8)  
Pulse Width from VCC valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
200  
—
—
Reset  
32  
Reset  
5
Int  
9
—
—
Int  
0
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
Int, BrCond  
SysClk (full frequency mode) Pulse Width(5)  
SysClk (full frequency mode) Clock HIGH Time(5)  
SysClk (full frequency mode) Clock LOW Time(5)  
5
3
—
—
5
—
3
—
N/A (8)  
N/A (8)  
N/A (8)  
N/A (8)  
N/A (8)  
N/A (8)  
t33  
2889 tbl 11  
NOTES:  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.  
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.  
8. For the 50MHz version, 1x Clock Mode and half-frequency bus mode only.  
5.5  
20  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081 (cont.)  
COMERCIAL TEMPERATURE RANGE (1, 2) (50MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)  
50MHz  
Symbol  
tsys/2  
t34  
Signals  
Description  
Min.  
2*t44  
t44-1  
t44-1  
8
Max.  
2*t44  
t44+1  
t44+1  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SysClk (half frequency mode) Pulse Width(5)  
SysClk (half frequency mode) Clock HIGH Time(5)  
SysClk (half frequency mode) Clock LOW Time(5)  
t35  
t36  
ALE  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to ALE falling  
t37  
ALE  
2
—
t38  
A/D  
9
—
t39  
A/D  
Hold from ALE falling  
Set-up to SysClk rising  
Hold from SysClk rising  
Pulse Width HIGH(6)  
2
—
t40  
Wr  
9
—
t41  
Wr  
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
16(6)  
16(6)  
40  
—
t43  
Pulse Width LOW(6)  
—
t44  
Clock Period(6)  
50  
(3, 4)  
tderate  
Timing deration for loading over CLD  
—
1
ns/  
25pF  
NOTES:  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.  
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.  
8. For the 50MHz version, 1x Clock Mode and half-frequencybus mode only.  
5.5  
21  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
DC ELECTRICAL CHARACTERISTICS R3081  
MILITARY TEMPERATURE RANGE— (TC(5) = -55°C to +125°C, VCC = +5.0V ±10%)  
20MHz  
25MHz  
Symbol  
VOH  
VOL  
VIH  
Parameter  
Test Conditions  
Min.  
2.4  
—
Max.  
—
Min.  
2.4  
—
Max.  
—
Units  
V
Output HIGH Voltage  
Output LOW Voltage  
VCC = Min., IOH = –4mA  
VCC = Min., IOL = 4mA  
0.4  
—
0.4  
—
V
(3)  
Input HIGH Voltage  
—
2.0  
—
2.0  
—
V
(1)  
VIL  
Input LOW Voltage  
—
0.8  
—
0.8  
—
V
(2,3)  
VIHS  
VILS  
CIN  
Input HIGH Voltage  
—
2.8  
—
2.8  
—
V
(1,2)  
Input LOW Voltage  
—
0.4  
12  
0.4  
12  
V
(4)  
Input Capacitance  
—
—
—
—
pF  
pF  
mA  
µA  
µA  
µA  
(4)  
COUT  
ICC  
Output Capacitance  
—
12  
—
12  
Operating Current  
Input HIGH Leakage  
Input LOW Leakage  
Output Tri-state Leakage  
VCC = 5.0V, TA = 25°C  
VIH = VCC  
—
550  
100  
—
—
650  
100  
—
IIH  
—
—
IIL  
VIL = GND  
–100  
–100  
–100  
–100  
IOZ  
VOH = 2.4V, VOL = 0.5V  
100  
100  
NOTES:  
2889 tbl 09  
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.  
2. VIHS and VILS apply to CIkIn and Reset.  
3. VIH should not be held above VCC + 0.5V.  
4. Guaranteed by design.  
5. Case Temperatures are "instant on."  
AC ELECTRICAL CHARACTERISTICS R3081  
MILITARY TEMPERATURE RANGE (1, 2)— (TC(7) = -55°C to +125°C, VCC = +5.0V ±10%)  
20MHz  
25MHz  
Symbol  
Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t1  
BusReq, Ack, BusError,  
RdCEn, CohReq  
Set-up to SysClk rising  
6
—
5
—
ns  
t1a  
t2  
A/D  
Set-up to SysClk falling  
Hold from SysClk rising  
7
4
—
—
6
4
—
—
ns  
ns  
BusReq, Ack, BusError,  
RdCEn, CohReq  
t2a  
t3  
A/D  
Hold from SysClk falling  
2
—
2
—
ns  
ns  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Tri-state from SysClk rising  
—
10  
—
10  
t4  
A/D, Addr, Diag, ALE, Wr  
Burst/WrNear, Rd, DataEn  
Driven from SysClk falling  
—
10  
—
10  
ns  
t5  
t6  
BusGnt  
Asserted from SysClk rising  
Negated from SysClk falling  
Valid from SysClk rising  
—
—
—
—
—
1.5  
—
0
8
8
—
—
—
—
—
1.5  
—
0
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BusGnt  
t7  
Wr, Rd, Burst/WrNear, A/D  
5
5
t8  
ALE  
Asserted from SysClk rising  
Negated from SysClk falling  
Hold from ALE negated(3)  
Asserted from SysClk falling  
Asserted from A/D tri-state(3)  
Driven from SysClk rising(3)  
4.5  
4
4.5  
4
t9  
ALE  
t10  
t11  
t12  
t14  
t15  
t16  
t17  
A/D  
—
15  
—
—
7
—
15  
—
—
6
DataEn  
DataEn  
A/D  
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling  
—
—
—
—
—
—
Addr(3:2)  
Diag  
Valid from SysClk  
Valid from SysClk  
6
6
12  
11  
5.5  
22  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AC ELECTRICAL CHARACTERISTICS R3081 (cont.)  
MILITARY TEMPERATURE RANGE(1, 2)— (TC(7) = -55°C to +125°C, VCC = +5.0V ±10%)  
20MHz  
25MHz  
Symbol Signals  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
tsys  
t32  
A/D  
Tri-state from SysClk falling  
—
10  
—
10  
ns  
A/D  
SysClk falling to data valid  
Pulse Width HIGH  
—
10  
13  
—
—
8
12  
—
ns  
ns  
ns  
ns  
µs  
tsys  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
ClkIn (2x clock mode)  
Reset  
Pulse Width LOW  
10  
—
8
—
Clock Period  
25  
250  
—
20  
200  
32  
5
250  
—
Pulse Width from Vcc valid  
Minimum Pulse Width  
Set-up to SysClk falling  
Mode set-up to Reset rising  
Mode hold from Reset rising  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to SysClk falling  
Hold from SysClk falling  
Pulse Width(5)  
200  
32  
Reset  
—
—
Reset  
6
—
—
Int  
10  
—
9
—
Int  
0
—
0
—
SInt, SBrCond  
SInt, SBrCond  
Int, BrCond  
6
—
5
—
3.5  
6
—
3
—
—
5
—
Int, BrCond  
3.5  
2*t22  
t22-2  
—
3
—
SysClk (full frequency mode)  
SysClk (full frequency mode)  
2*t22  
t22+2  
2*t22  
t22-2  
2*t22  
t22+2  
Clock High Time(5)  
t33  
tsys/2  
t34  
SysClk (full frequency mode)  
Clock LOW Time(5)  
Pulse Width(5)  
t22-2  
t22+2  
4*t22  
t22-2  
t22+2  
4*t22  
2*t22+2  
2*t22+2  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SysClk (half frequency mode)  
4*t22  
4*t22  
SysClk (half frequency mode)  
Clock HIGH Time(5)  
Clock LOW Time(5)  
Set-up to SysClk falling  
Hold from SysClk falling  
Set-up to ALE falling  
Hold from ALE falling  
Set-up to SysClk rising  
Hold from SysClk rising  
Pulse Width HIGH(6)  
Pulse Width LOW(6)  
Clock Period(6)  
2*t22-2  
2*t22+2  
2*t22-2  
t35  
SysClk (half frequency mode)  
2*t22-2  
2*t22+2  
—
2*t22-2  
t36  
ALE  
9
2
8
2
t37  
ALE  
—
—
t38  
A/D  
10  
2
—
9
—
t39  
A/D  
—
2
—
t40  
Wr  
10  
3
—
9
—
t41  
Wr  
—
3
—
t42  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
ClkIn (1x clock mode)  
All outputs  
20  
20  
50  
—
—
16  
16  
40  
—
—
t43  
—
—
t44  
50  
1
50  
tderate  
Timing deration for loading  
1
ns/  
25pF  
(3, 4)  
over CLD  
NOTES:  
2889 tbl 11  
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.  
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.  
3. Guaranteed by design.  
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified  
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.  
5. In 1x clock mode, t22 is replaced by t44/2.  
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.  
7. Case Temperatures are "instant on."  
5.5  
23  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN CONFIGURATIONS  
1
84  
75  
Vss  
Vcc  
12  
Vss  
Vcc  
ClkIn  
A/D(14)  
A/D(13)  
A/D(12)  
A/D(11)  
A/D(10)  
A/D(9)  
Vcc  
Rsvd(4)  
Rsvd(3)  
Rsvd(2)  
Rsvd(1)  
CohReq  
Int(5)  
84-Pin MQUAD/PLCC  
Top View  
Vss  
Vss  
Vcc  
A/D(8)  
A/D(7)  
A/D(6)  
A/D(5)  
A/D(4)  
A/D(3)  
Vss  
Int(4)  
Int(3)  
SInt(2)  
SInt(1)  
SInt(0)  
SBrCond(3)  
SBrCond(2)  
NC  
Vcc  
A/D(2)  
A/D(1)  
Vss  
Vcc  
54  
A/D(0)  
33  
2889 drw 08  
NOTE:  
Reserved Pins must not be connected.  
5.5  
24  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN CONFIGURATIONS  
1
84  
21  
22  
Vss  
Vss  
Vcc  
ClkIn  
Vcc  
A/D(14)  
A/D(13)  
A/D(12)  
A/D(11)  
A/D(10)  
A/D(9)  
Vcc  
Rsvd(4)  
Rsvd(3)  
Rsvd(2)  
Rsvd(1)  
CohReq  
Int(5)  
84-Pin FD  
Top View  
Vss  
Vss  
Vcc  
A/D(8)  
A/D(7)  
A/D(6)  
A/D(5)  
A/D(4)  
A/D(3)  
Vss  
Int(4)  
Int(3)  
SInt(2)  
SInt(1)  
SInt(0)  
SBrCond(3)  
SBrCond(2)  
NC  
Vcc  
A/D(2)  
A/D(1)  
A/D(0)  
Vss  
64  
63  
42  
43  
Vcc  
NOTE:  
Reserved Pins must not be connected.  
5.5  
25  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
25242322212019181716151413121110 9 8 7 6 5 4 3 2 1  
NC  
NC  
VSS  
NC  
NC  
VSS  
VCC  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
VCC  
A/D(14)  
A/D(13)  
A/D(12)  
A/D(11)  
A/D(10)  
A/D(9)  
VCC  
ClkIn  
RSVD(4)  
RSVD(3)  
RSVD(2)  
RSVD(1)  
CohReQ  
Int(5)  
VSS  
VCC  
VSS  
RV3081 Y  
A/D(8)  
A/D(7)  
A/D(6)  
A/D(5)  
A/D(4)  
A/D(3)  
VSS  
100-Pin  
TQFP  
(Cavity Up)  
Top View  
Int(4)  
Int(3)  
SInt(2)  
SInt(1)  
SInt(0)  
SBrCond(3)  
SBrCond(2)  
NC  
VSS  
VCC  
VSS  
VCC  
VCC  
A/D(2)  
A/D(1)  
A/D(0)  
NC  
NC  
51 5253 54555657585960616263646566676869707172737475  
2905 drw 06  
5.5  
26  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
t44  
t43  
ClkIn  
t42  
t33  
SysClk  
t32  
tsys  
2889 drw 12  
Figure 8 (a). R3081 Clocking (1x clock input mode, full frequency bus)  
t44  
t43  
ClkIn  
t42  
t35  
SysClk  
t34  
2889 drw 13  
tsys/2  
Figure 8 (b). R3081Clocking (1x clock input mode, half-frequency bus)  
t22  
t21  
ClkIn  
t20  
t34  
t35  
SysClk  
tsys/2  
2889 drw 14  
Figure 8 (c). R3081 Clocking (2x clock input mode, half-frequency bus)  
t22  
t21  
ClkIn  
t20  
t33  
t32  
SysClk  
2889 drw 15  
tSYS  
Figure 8 (d). R3081 Clocking (2x clock input mode, full-frequency bus)  
5.5  
27  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
Vcc  
ClkIn  
Reset  
t23  
2889 drw 16  
Figure 9. Power-On Reset Sequence  
ClkIn  
t24  
Reset  
2889 drw 17  
Figure 10. Warm Reset Sequence  
SysClk  
Reset  
t25  
t26  
Int(n)  
t27  
2889 drw 18  
Figure 11. Mode Selection and Negation of Reset  
5.5  
28  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
t7  
t15  
Rd  
t14  
t14  
t18  
t1a  
Addr  
BE  
Data Input  
t2a  
A/D(31:0)  
Addr(3:2)  
ALE  
t16  
t8  
t10  
Word Address  
t9  
t12  
t15  
DataEn  
Burst  
t11  
t7  
t1  
RdCEn  
Ack  
t2  
t17  
t17  
Cached?  
Miss Address(3)  
Miss Address(2)  
Ack?  
Diag(1)  
Diag(0)  
I/D  
Start  
Read  
Turn  
Bus  
Ack/  
RdCen  
Sample  
Data  
End  
Read  
Ack?  
2889 drw 19  
Figure 12. Single Datum Read in R3081  
5.5  
29  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
t7  
t15  
Rd  
t14  
t14  
t18  
t1a  
Word 0  
t1a  
Word 1  
t1a  
Word 2  
t1a  
Word 3  
Addr  
BE  
A/D(31:0)  
Addr(3:2)  
ALE  
t2a  
t2a  
t2a  
t2a  
t16  
t8  
t10  
'00'  
t9  
'01'  
'10'  
'11'  
t16  
t16  
t16  
t12  
t15  
DataEn  
Burst  
t11  
t7  
t1  
t1  
t1  
t1  
RdCEn  
Ack  
t2  
t2  
t2  
t2  
t17  
t17  
Cached?  
Miss Address(3)  
Miss Address(2)  
Diag(1)  
Diag(0)  
I/D  
Start  
Read  
Turn  
Bus  
Ack/  
RdCen  
Sample RdCEn Sample RdCEn Sample RdCEn Sample  
New  
Data Data Data Data Transaction  
2889 drw 20  
Figure 13. R3081 Burst Read  
5.5  
30  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
Rd  
t1a  
t1a  
A/D(31:0)  
Addr(3:2)  
ALE  
Word 0  
Word 1  
t2a  
t2a  
'00'  
'01'  
'10'  
t16  
t16  
DataEn  
Burst  
t1  
t1  
t1  
RdCEn  
Ack  
t2  
t2  
t2  
RdCEn  
Sample  
Data  
RdCEn  
Sample  
Data  
RdCEn  
Sample  
Data  
2889 drw 21  
Figure 14 (a). Start of Throttled Quad Read  
SysClk  
Rd  
t15  
t14  
t1a  
t1a  
Word 2  
Word 3  
A/D(31:0)  
Addr(3:2)  
ALE  
t
2a  
t2a  
'01'  
'11'  
t
16  
t15  
DataEn  
Burst  
t1  
t1  
t
1
RdCEn  
t
2
t2  
t2  
t1  
Ack  
t2  
Ack  
RdCEn  
Sample  
Data  
RdCEn  
Sample  
Data  
New  
Transaction  
2889 drw 22  
Figure 14 (b). End of Throttled Quad Read  
5.5  
31  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
t7  
t15  
Wr  
t14  
t14  
t19  
Addr  
BE  
Data  
Out  
A/D(31:0)  
Addr(3:2)  
ALE  
t10  
t16  
t8  
Word Address  
t9  
t17  
Cached  
Reserved  
Reserved  
Diag(1)  
Diag(0)  
WrNear  
Ack  
t17  
t7  
Reserved  
t15  
t2  
t1  
Start  
Write  
Data  
Out  
Ack  
Negate  
Wr  
New  
Transfer  
Ack?  
Ack?  
2889 drw 23  
Figure 15. R3081 Write Cycle  
SysClk  
t2  
BusReq  
t1  
t
5
BusGnt  
t3  
A/D(31:0)  
Addr(3:2)  
Diag(1:0)  
Rd  
Wr  
ALE  
Burst/  
WrNear  
2889 drw 24  
Figure 16. Request and Relinquish of R3081 Bus to External Master  
5.5  
32  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
BusReq  
BusGnt  
A/D(31:0)  
Addr(3:2)  
Diag(1:0)  
Rd  
t2  
t1  
t6  
t4  
Wr  
ALE  
Burst/  
WrNear  
2889 drw 25  
Figure 17. R3081 Regaining Bus Mastership  
SysClk  
SInt(n)  
t29  
t28  
2889 drw 26  
Figure 18. Synchronized Interrupt Input Timing  
SysClk  
Int(n)  
t30  
t31  
2889 drw 27  
Figure 19. Direct Interrupt Input Timing  
5.5  
33  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
SBrCond(n)  
t28  
t29  
2889 drw 28  
Figure 20. Synchronized Branch Condition Input Timing  
SysClk  
BrCond(n)  
t30  
t31  
2889 drw 29  
Figure 21. Direct Branch Condition Input Timing  
SysClk  
∫∫  
t2  
BusReq  
t1  
CohReq  
t5  
BusGnt  
A/D(31:0)  
Addr(3:2)  
Diag(1:0)  
Rd  
t3  
Wr  
ALE  
Burst/  
WrNear  
2889 drw 30  
Figure 22. Coherent DMA Request  
5.5  
34  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
Wr  
T41  
T40  
T37  
T36  
T38  
ALE  
A/D  
T39  
Addr  
Internal  
Invalidate  
Address  
2889 drw 31  
Figure 23. Beginning of Coherent DMA Write  
SysClk  
T1  
T2  
Ack  
IvdReq  
Internal  
Ivd  
Internal  
Invalidate  
Address  
2988 drw 32  
Figure 24. Cache Word Invalidation  
SysClk  
Ack  
T40  
Wr  
T
41  
2889 drw 33  
Figure 25. End of Coherent Write  
5.5  
35  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SysClk  
t2  
BusReq  
t1  
CohReq  
BusGnt  
t6  
t4  
A/D(31:0)  
Addr(3:2)  
Diag(1:0)  
Rd  
Wr  
ALE  
Burst/  
WrNear  
2889 drw 34  
Figure 26. End of Coherent DMA Request  
5.5  
36  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
84 LEAD PLCC/MQUAD(7) (SQUARE)  
A
D
D1  
A1  
PIN 1  
C
45° x .045  
D3/E3  
E1  
E
D2/E2  
b1  
B
e
C1  
SEATING PLANE  
2874 drw 27  
NOTES:  
1. All dimensions are in inches, unless otherwise noted.  
2. BSC—Basic lead Spacing between Centers.  
3. D & E do not include mold flash or protutions.  
4. Formed leads shall be planar with respect to one another and within .004 inches at the seating plane.  
5. ND & NE represent the number of leads in the D & E directions respectively.  
6. D1 & E1 should be measured from the bottom of the package.  
7. MQUAD is pin & form compatible with PLCC.  
DWG #  
J84-1  
84  
MJ84-1  
84  
# of Leads  
Symbol  
Min.  
165  
Max.  
.180  
Min.  
165  
Max.  
A
A1  
.180  
.114  
.095  
.026  
.013  
.020  
.008  
1.185  
1.150  
1.090  
.115  
.094  
.026  
.013  
.020  
.008  
1.185  
1.140  
1.090  
B
.032  
.032  
b1  
.021  
.021  
C
.040  
.040  
C1  
.012  
.012  
D
1.195  
1.156  
1.130  
1.195  
1.150  
1.130  
D1  
D2/E2  
D3/E3  
E
1.000 REF  
1.000 REF  
1.185  
1.150  
1.195  
1.156  
1.185  
1.140  
1.195  
1.150  
E1  
e
.050 BSC  
21  
.050 BSC  
21  
ND/NE  
5.5  
37  
IDT79R3081 RISController  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
ORDERING INFORMATION  
XXXXX  
–
XX  
X
X
IDT  
Device Type  
Speed Package Process/  
Temp. Range  
Blank  
B
M
Commercial Temperature Range  
Compliant to MIL-STD-883, Class B  
Military Temperature Range Only  
MJ  
FD  
84-Pin MQUAD  
84-lead Cavity-down Flatpack with  
Integral Thermal Slug  
84-lead PLCC  
J
PF  
100-lead TQFP  
20  
25  
33  
40  
50  
20.0MHz  
25.0MHz  
33.33MHz  
40.0MHz  
(5V Only)  
50.0MHz  
79R3081  
No TLB; VCC = 5V  
With TLB; VCC = 5V  
No TLB; VCC = 3.3V  
With TLB; VCC = 3.3V  
79R3081E  
79RV3081  
79RV3081E  
2889 drw 37  
VALID COMBINATIONS  
IDT 79R3081 (E) – 20, 25, 33, 40, 50  
79RV3081 (E) – 20, 25, 33  
MJ Package  
PF Package  
MJ Package  
79RV3081(E) – 20, 25, 33, 40  
79R3081E – 20, 25 (FDB/FDM)  
FD Package Only  
5.5  
38  

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