IDT79RV4640-180DU8 [IDT]
RISC Microprocessor, 64-Bit, 180MHz, PQFP128, PLASTIC, QFP-128;
| 型号： | IDT79RV4640-180DU8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISC Microprocessor, 64-Bit, 180MHz, PQFP128, PLASTIC, QFP-128 |
| 文件： | 总23页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79RC4640™
Low-Cost Embedded
64-bit RISController
w/ DSP Capability
◆
Low-power operation
ꢌꢍꢈꢎꢏꢊꢍꢐ
◆
–
–
Active power management powers-down inactive units
Standby mode
High-performance embedded 64-bit microprocessor
–
–
–
–
64-bit integer operations
64-bit registers
Based on the MIPS RISC Architecture
100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz
operating frequencies
◆
Large, efficient on-chip caches
–
Separate 8KB Instruction and 8KB Data caches
Over 3200MB/sec bandwidth from internal caches
2-set associative
Write-back and write-through support
Cache locking, to facilitate deterministic response
High performance write protocols, for graphics and data
communications
–
–
–
–
–
–
32-bit bus interface brings 64-bit power to 32-bit system cost
◆
◆
High-performance DSP capability
–
133.5 Million Integer Mul-Accumulate
operations/sec @267MHz
89 MFlops floating-point operations @267MHz
◆
Bus compatible with RC4000 family
–
–
System interfaces to 125MHz, provides bandwidth up to 500
MB/sec
High-performance microprocessor
–
–
–
133.5 M Mul-Add/second @267MHz
89 MFlops @267MHz
>640,000 dhrystone (2.1)/sec capability @267MHz (352
–
–
Direct interface to 32-bit wide systems
Synchronized to external reference clock for multi- master
operation
dhrystone MIPS)
High level of integration
–
Socket compatible with IDT RC 64474 and RC64574
◆
◆
Improved real-time support
–
–
–
64-bit, 267 MHz integer CPU
8KB instruction cache; 8KB data cache
Integer multiply unit with 133.5M Mul-Add/sec
–
–
Fast interrupt decode
Optional cache locking
◆
◆
Note: “R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”
refers to both
Upwardly software compatible with IDT RISController
Family
Easily upgradable to 64-bit system
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢈꢋꢅ
System Control Coprocessor
267 MHz 64-bit CPU
89 MFlops Single-Precision FPA
FP Register File
Address Translation/
Cache Attribute Control
64-bit Register File
64-bit Adder
Load Aligner
Store Aligner
Logic Unit
Pack/Unpack
Exception Management
Functions
FP Add/Sub/Cvt/
Div/Sqrt
High-Performance
Integer Multiply
FP Multiply
Control Bus
Data Bus
Instruction Bus
Instruction Cache
Set A
(Lockable)
Data Cache
Set A
(Lockable)
32-bit
Synchronized
System Interface
Instruction Cache
Set B
Data Cache
Set B
The IDT logo is a registered trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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DSC 3486/2
1999 Integrated Device Technology, Inc.
IDT79RC4640™
The extensions result in better code density, greater multi-
processing support, improved performance for commonly used code
sequences in operating system kernels, and faster execution of floating-
point intensive applications. All resource dependencies are made trans-
parent to the programmer, insuring transportability among implementa-
tions of the MIPS instruction set architecture. In addition, MIPS-III
specifies new instructions defined to take advantage of the 64-bit archi-
tecture of the processor.
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The IDT79RC4640 is a low-cost member of the Integrated Device
Technology, Inc. RC4000 family, targeted to a variety of performance-
hungry embedded applications. The RC4640 continues the RC4000
tradition of high-performance through high-speed pipelines, high-band-
width caches and bus interface, 64-bit architecture, and careful attention
to efficient control. The cost of this performance is reduced by removing
functional units frequently not required for many embedded applications.
Finally, the RC4640 also implements additional instructions, which
are considered extensions to the MIPS-III architecture. These instruc-
tions improve the multiply and multiply-add throughput of the CPU,
making it well suited to a wide variety of imaging and DSP applications.
These extensions, which use opcodes allocated by MIPS Technologies
for this purpose, are supported by a wide variety of development tools.
The RC4640 supports a wide variety of embedded processor-based
applications, such as internetworking equipment (routers, switches),
office automation equipment (printers, scanners), and consumer multi-
media game systems. Also, being upwardly software-compatible with
the RC32300 family as well as bus- and upwardly software-compatible
with the IDT RC4000 family, the RC4640 will serve in many of the same
applications. And, the RC4640 supports applications that require integer
digital signal processing (DSP) functions.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and autonomous
multiply/divide unit. The 64-bit register resources include: 32 general-
purpose orthogonal integer registers, the HI/LO result registers for the
integer multiply/divide unit, and the program counter. In addition, the on-
chip floating-point co-processor adds 32 floating-point registers, and a
floating-point control/status register.
The RC64475 and RC64575 processors offer a direct migration path
for designs based on IDT’s RC4650 processors, through full pin and
socket compatibility.
The RC4640 brings 64-bit performance levels to lower cost systems.
High performance is preserved by retaining large on-chip two-way set-
associative caches, a streamlined high-speed pipeline, high bandwidth,
64-bit execution, and facilities such as early restart for data cache
misses.
The RC4640 has 32 general-purpose 64-bit registers. These regis-
ters are used for scalar integer operations and address calculation. The
register file consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
These techniques allow the system designer over 3.2 GB/sec aggre-
gate internal bandwidth, 500 MB/sec bus bandwidth, almost 352 Dhrys-
tone MIPS, 89MFlops, and 133.5 M Mul-Add/sec. An array of tools
facilitates rapid development of RC4640-based systems, allowing a
wide variety of customers access to the processor’s high-performance
capabilities while maintaining short time-to-market goals.
The RC4640 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations;
the logic unit performs all of the logic and shift operations. Each unit is
highly optimized and can perform an operation in a single pipeline cycle.
ꢓꢈꢊꢔꢕꢈꢊꢍꢅꢖꢗꢍꢊꢗꢇꢍꢕ
Some key elements of the RC4640 are briefly described below. More
detailed information is available in the IDT79RC4640/IDT79RC4650
RISC Processor Hardware User’s Manual.
The RC4640 uses a dedicated integer multiply/divide unit, optimized
for high-speed multiply and multiply-accumulate operation. Table 1
shows the performance, expressed in terms of pipeline clocks, achieved
by the RC4640 integer multiply unit.
The RC4640 uses a 5-stage pipeline that is similar to the
IDT79RC3000 and the IDT79RC4700 processors. The simplicity of this
pipeline allows the RC4640 to cost less than super-scalar processors
and require less power than super-pipelined processors. So, unlike
superscalar processors, applications that have large data dependen-
cies, or require frequent load/stores, can still achieve peak performance.
MULT/U, MAD/U
MUL
16 bit
32 bit
16 bit
32 bit
any
3
2
0
0
1
2
0
0
0
4
3
3
2
4
3
The RC4640 implements the MIPS-III Instruction Set Architecture
and is fully upward compatible with applications that run on earlier
generation parts. The RC4640 is software-compatible with the RC4650,
and includes the instruction set found in the RC4700 microprocessor,
targeted at higher performance while maintaining binary compatibility
with RC32300 processors.
DMULT, DMULTU
DIV, DIVU
6
5
any
36
68
36
68
DDIV, DDIVU
any
Table 1 RC4640 Integer Multiply Operation
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IDT79RC4640™
As in the IDT79RC4700, the RC4640 maintains fully precise floating-
point exceptions while allowing both overlapped and pipelined opera-
tions. Precise exceptions are extremely important in mission-critical
environments, such as ADA, and highly desirable for debugging in any
environment.
The MIPS-III architecture defines that the results of a multiply or
divide operation are placed in the HI and LO registers. The values can
then be transferred to the general purpose register file using the MFHI/
MFLO instructions.
The RC4640 adds a new multiply instruction, “MUL”, which can
specify that the multiply results bypass the “Lo” register and are placed
immediately in the primary register file. By avoiding the explicit “Move-
from-Lo” instruction required when using “Lo”, throughput of multiply-
intensive operations is increased.
The floating-point unit’s operation set includes floating-point add,
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats, and
floating-point compare. These operations comply with IEEE Standard
754. Double precision operations are not directly supported; attempts to
execute double-precision floating point operations, or refer directly to
double-precision registers, result in the RC4640 signalling a “trap” to the
CPU, enabling emulation of the requested function. Table 2 gives the
latencies of some of the floating-point instructions in internal processor
cycles.
An additional enhancement offered by the RC4640 is an atomic
“multiply-add” operation, MAD, used to perform multiply-accumulate
operations. This instruction multiplies two numbers and adds the product
to the current contents of the HI and LO registers. This operation is used
in numerous DSP algorithms, and allows the RC4640 to cost reduce
systems requiring a mix of DSP and control functions.
Finally, aggressive implementation techniques feature low latency for
these operations along with pipelining to allow new operations to be
issued before a previous one has fully completed. Table 1 also shows
the repeat rate (peak issue rate), latency, and number of processor stalls
required for the various operations. The RC4640 performs automatic
operand size detection to determine the size of the operand, and imple-
ments hardware interlocks to prevent overrun, allowing this high-perfor-
mance to be achieved with simple programming.
ADD
SUB
4
4
MUL
DIV
8
32
31
3
SQRT
CMP
FIX
The RC4640 incorporates an entire single-precision floating-point
coprocessor on chip, including a floating-point register file and execution
units. The floating-point coprocessor forms a “seamless” interface with
the integer unit, decoding and executing instructions in parallel with the
integer unit.
4
FLOAT
ABS
6
1
The floating-point unit of the RC4640 directly implements single-
precision floating-point operations, which enables the RC4640 to
perform functions such as graphics rendering without requiring exten-
sive die area or power consumption. The single-precision unit of the
RC4640 is directly compatible with the single-precision operation of the
RC4700, and features the same latencies and repeat rates.
MOV
NEG
LWC1
SWC1
1
1
2
1
Table 2 Floating-Point Operation
The RC4640 does not directly implement the double-precision opera-
tions found in the RC4700. However, to maintain software compatibility,
the RC4640 will signal a trap when a double-precision operation is initi-
ated, allowing the requested function to be emulated in software. Alter-
natively, the system architect could use a software library emulation of
double-precision functions, selected at compile time, to eliminate the
overhead associated with trap and emulation.
The floating-point register file is made up of thirty-two 32-bit regis-
ters. These registers are used as source or target registers for the
single-precision operations.
References to these registers as 64-bit registers (as supported in the
RC4700) will cause a trap to be signalled to the integer unit.
The floating-point control register space contains two registers; one
for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
The RC4640’s floating-point execution units perform single precision
arithmetic, as specified in IEEE Standard 754. The execution unit is
broken into a separate multiply unit and a combined add/convert/divide/
square root unit. Overlap of multiply and add/subtract is supported. The
multiplier is partially pipelined, allowing a new multiplication instruction
to begin every 6 cycles.
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IDT79RC4640™
The system control coprocessor in the MIPS architecture is respon-
sible for the virtual to physical address translation and cache protocols,
the exception control system, and the diagnostics capability of the
processor. In the MIPS architecture, the system control coprocessor
(and thus the kernel software) is implementation dependent.
The RC4640 supports two modes of operation: user mode and
kernel mode. Kernel mode operation is typically used for exception
handling and operating system kernel functions, including CP0 manage-
ment and access to IO devices. In kernel mode, software has access to
the entire address space and all of the co-processor 0 registers, and
can select whether to enable co-processor 1 accesses. The processor
enters kernel mode at reset, and whenever an exception is recognized.
In the RC4640, significant changes in CP0 relative to the RC4600
have been implemented. These changes are designed to simplify
memory management, facilitate debug, and speed real-time processing.
User mode is typically used for applications programs. User mode
accesses are limited to a subset of the virtual address space, and can
be inhibited from accessing CP0 functions.
The RC4640 incorporates all system control co-processor (CP0)
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RC4640
includes registers to implement a real-time cycle counting facility, which
aids in cache diagnostic testing, assists in data error detection, and facil-
itates software debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic interrupt.
0xFFFFFFFF
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB
0xC0000000
0xBFFFFFFF
Uncached kernel physical address space
(kseg1)
Table 3 shows the CP0 registers of the RC4640.
Unmapped, 0.5GB
0xA0000000
0
1
2
3
IBase
Instruction address space base
Instruction address space bound
Data address space base
Data address space bound
Not used
0x9FFFFFFF
Cached kernel physical address space
(kseg0)
IBound
DBase
DBound
Unmapped, 0.5GB
0x80000000
4-7, 10, 20-25, -
29, 31
0x7FFFFFF
8
BadVAddr
Virtual address on address exceptions
Counts every other cycle
User virtual address space
(useg)
Mapped, 2.0GB
9
Count
Compare
Status
Cause
EPC
11
12
13
14
15
16
17
Generate interrupt when Count = Compare
Miscellaneous control/status
Exception/Interrupt information
Exception PC
0x00000000
Figure 1 Mode Virtual Addressing (32-bit mode)
PRId
Processor ID
Config
CAlg
Cache and system attributes
The 4GB virtual address space of the RC4640 is shown in Figure 1.
The 4 GB address space is divided into addresses accessible in either
kernel or user mode (kuseg), and addresses only accessible in kernel
mode (kseg2:0).
Cache attributes for the 8 512MB regions of the
virtual address space
18
19
26
27
28
30
IWatch
DWatch
ECC
Instruction breakpoint virtual address
Data breakpoint virtual address
Used in cache diagnostics
The RC4640 supports the use of multiple user tasks sharing
common virtual addresses, but mapped to separate physical addresses.
This facility is implemented via the “base-bounds” registers contained in
CP0.
CacheErr
TagLo
Cache diagnostic information
Cache index information
When a user virtual address is asserted (load, store, or instruction
fetch), the RC4640 compares the virtual address with the contents of
the appropriate “bounds” register (instruction or data). If the virtual
ErrorEPC
CacheError exception PC
Table 3 RC4640 CPO Registers
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IDT79RC4640™
In addition, the contents of one set of the instruction cache (set “A”)
can be “locked” by setting a bit in a CP0 register. Locking the set
prevents its contents from being overwritten by a subsequent cache
miss; refill occurs then only into “set B”.
address is “in bounds”, the value of the corresponding “base” register is
added to the virtual address to form the physical address for that refer-
ence. If the address is not within bounds, an exception is signalled.
This facility enables multiple user processes in a single physical
memory without the use of a TLB. This type of operation is further
supported by a number of development tools for the RC4640, including
real-time operating systems and “position independent code”.
This operation effectively “locks” time critical code into one 4kB set,
while allowing the other set to service other instruction streams in a
normal fashion. Thus, the benefits of cached performance are achieved,
while deterministic real-time response is preserved.
Kernel mode addresses do not use the base-bounds registers, but
rather undergo a fixed virtual-to-physical address translation.
For fast, single cycle data access, the RC4640 includes an 8KB on-
chip data cache that is two-way set associative with a fixed 32-byte
(eight words) line size. Table 4 lists the RC4640 cache attributes.
To facilitate software debug, the RC4640 adds a pair of “watch” regis-
ters to CP0. When enabled, these registers will cause the CPU to take
an exception when a “watched” address is appropriately accessed.
Size
8KB
8KB
The RC4640 also adds the capability to speed interrupt exception
decoding. Unlike the RC4700, which utilizes a single common exception
vector for all exception types (including interrupts), the RC4640 allows
kernel software to enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing by allowing
software to avoid decoding interrupts from general purpose exceptions.
Organization
Line size
Index
2-way set associative 2-way set associative
32B
32B
vAddr11..0
pAddr31..12
n.a.
vAddr11..0
Tag
pAddr31..12
writeback /writethru
Write policy
Line transfer order
read sub-block order read sub-block order
To keep the RC4640’s high-performance pipeline full and operating
efficiently, the RC4640 incorporates on-chip instruction and data caches
that can each be accessed in a single processor cycle. Each cache has
its own 64-bit data path and can be accessed in parallel. The cache
subsystem provides the integer and floating-point units with an aggre-
gate bandwidth of over 3200 MB per second at a pipeline clock
frequency of 267MHz. The cache subsystem is similar in construction to
that found in the RC4700, although some changes have been imple-
mented. Table 4 is an overview of the caches found on the RC4640.
write sequential
Miss restart after transfer of entire line
write sequential
first word
per-byte
Parity
per-word
set A
Cache locking
set A
Table 4 RC4640 Cache Attributes
The data cache is protected with byte parity and its tag is protected
with a single parity bit. It is virtually indexed and physically tagged to
allow simultaneous address translation and data cache access
The RC4640 incorporates a two-way set associative on-chip instruc-
tion cache. This virtually indexed, physically tagged cache is 8KB in size
and is parity protected.
The normal write policy is writeback, which means that a store to a
cache line does not immediately cause memory to be updated. This
increases system performance by reducing bus traffic and eliminating
the bottleneck of waiting for each store operation to finish before issuing
a subsequent memory operation. Software can however select write-
through for certain address ranges, using the CAlg register in CP0.
Cache protocols supported for the data cache are:
Because the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache access, thus further
increasing performance by allowing these two operations to occur simul-
taneously. The tag holds a 20-bit physical address and valid bit, and is
parity protected.
◆
Uncached.
Addresses in a memory area indicated as uncached will not be
read from the cache. Stores to such addresses will be written
directly to main memory, without changing cache contents.
The instruction cache is 64-bits wide, and can be refilled or accessed
in a single processor cycle. Instruction fetches require only 32 bits per
cycle, for a peak instruction bandwidth of 1068MB/sec at 267MHz.
Sequential accesses take advantage of the 64-bit fetch to reduce power
dissipation, and cache miss refill, can write 64 bits-per-cycle to minimize
the cache miss penalty. The line size is eight instructions (32 bytes) to
maximize performance.
◆
Writeback.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
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IDT79RC4640™
tents will be updated, and the cache line marked for later write-
An on-chip phase-locked-loop generates the pipeline clock from the
system interface clock by multiplying it up an amount selected at system
reset. Supported multipliers are values 2 through 8 inclusive, allowing
systems to implement pipeline clocks at significantly higher frequency
than the system interface clock.
back. If the cache lookup misses, the target line is first brought
into the cache before the cache is updated.
◆
Write-through with write allocate.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
tents will be updated and main memory will also be written; the
state of the “writeback” bit of the cache line will be unchanged. If
the cache lookup misses, the target line is first brought into the
cache before the cache is updated.
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the RC4640 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC. When initialized for
32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with
4 parity check bits.
◆
Write-through without write-allocate.
The system interface is configurable to allow easier interfacing to
memory and I/O systems of varying frequencies. The bus frequency and
reference timing of the RC4640 are taken from the input clock. The rate
at which the CPU transmits data to the system interface is program-
mable via boot time mode control bits. The rate at which the processor
receives data is fully controlled by the external device. Therefore, either
a low cost interface requiring no read or write buffering or a faster, high
performance interface can be designed to communicate with the
RC4640. Again, the system designer has the flexibility to make these
price/performance trade-offs.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
tents will be updated, and the cache line marked for later write-
back. If the cache lookup misses, then only main memory is
written.
Associated with the Data Cache is the store buffer. When the
RC4640 executes a Store instruction, this single-entry buffer gets written
with the store data while the tag comparison is performed. If the tag
matches, then the data is written into the Data Cache in the next cycle
that the Data Cache is not accessed (the next non-load cycle). The store
buffer allows the RC4640 to execute a store every processor cycle and
to perform back-to-back stores without penalty.
The RC4640 interface has a 9-bit System Command (SysCmd) bus.
The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also
indicates what type of transaction is to take place (for example, a read
or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word trans-
mitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4640. Processor requests are initiated by
the RC4640 and responded to by an external device. External requests
are issued by an external device and require the RC4640 to respond.
Writes to external memory, whether cache miss writebacks or stores
to uncached or write-through addresses, use the on-chip write buffer.
The write buffer holds up to four address and data pairs. The entire
buffer is used for a data cache writeback and allows the processor to
proceed in parallel with memory update.
The RC4640 supports single datum (one to eight byte) and 8-word
block transfers on the SysAD bus. In the case of a single-datum
transfer, the low-order 3 address bits gives the byte address of the
transfer, and the SysCmd bus indicates the number of bytes being
transferred.
The RC4640 supports a 32-bit system interface that is syntactically
compatible with the RC4700 system interface.
The interface consists of a 32-bit Address/Data bus with eight check
bits and a 9-bit command bus protected with parity. In addition, there are
eight handshake signals and six interrupt inputs. The interface has a
simple timing specification and is capable of transferring data between
the processor and memory at a peak rate of 500MB/sec at 125MHz on
the bus.
There are six handshake signals on the system interface. Two of
these, RdRdy* and WrRdy* are used by an external device to indicate to
the RC4640 whether it can accept a new read or write transaction. The
RC4640 samples these signals before deasserting the address on read
and write requests.
Figure 2 on page 7 shows a typical system using the RC4640. In this
example two banks of DRAMs are used to supply and accept data with a
DDxxDD data pattern.
The following is a list of the supported external requests:
The RC4640 clocking interface allows the CPU to be easily mated
with external reference clocks. The CPU input clock is the bus reference
clock, and can be between 50 and 125MHz (somewhat dependent on
maximum pipeline speed for the CPU).
◆
Read Response
◆
Null
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IDT79RC4640™
information to be kept in a low-cost EPROM; alternatively the twenty-or-
so bits could be generated by the system interface ASIC or a simple
PAL.
ExtRqst* and Release* are used to transfer control of the SysAD and
SysCmd buses between the processor and an external device. When an
external device needs to control the interface, it asserts ExtRqst*. The
RC4640 responds by asserting Release* to release the system interface
to slave state.
Immediately after the VCCOK Signal is asserted, the processor
reads a serial bit stream of 256 bits to initialize all fundamental opera-
tional modes. After initialization is complete, the processor continues to
drive the serial clock output, but no further initialization bits are read.
ValidOut* and ValidIn* are used by the RC4640 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4640 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
The boot-time serial mode stream is defined in Table 6. Bit 0 is the bit
presented to the processor when VCCOK is asserted; bit 255 is the last.
CP0 is also used to control the power management for the RC4640.
This is the standby mode and it can be used to reduce the power
consumption of the internal core of the CPU. The standby mode is
entered by executing the WAIT instruction with the SysAD bus idle and
is exited by any interrupt.
The RC4640 requires a non-overlapping system interface, compat-
ible with the RC4700. This means that only one processor request may
be outstanding at a time and that the request must be serviced by an
external device before the RC4640 issues another request. The RC4640
can issue read and write requests to an external device, and an external
device can issue read and write requests to the RC4640.
ꢘꢎꢈꢒꢔꢙꢚꢅꢛꢂꢔꢍꢅꢖꢑꢍꢊꢈꢎꢇꢂꢒ
The RC4640 asserts ValidOut* and simultaneously drives the
address and read command on the SysAD and SysCmd buses. If the
system interface has RdRdy* or Read transactions asserted, then the
processor tristates its drivers and releases the system interface to slave
state by asserting Release*. The external device can then begin sending
the data to the RC4640.
The RC4640 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode”.
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, and some of the input pins
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run.
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
Address
Control
DRAM
(80ns)
Boot
ROM
SCSI
ENET
Memory I/O
Controller
32
RV4640
9
2
11
Figure 2 Typical RC4640 System Architecture
7 of 23
March 28, 2000
IDT79RC4640™
temperature parts. The type of package, speed (power) of the device,
and air flow conditions affect the equivalent ambient temperature condi-
tions that will meet this specification.
If the conditions are not correct when the WAIT instruction finishes the
W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a
NOP.
The equivalent allowable ambient temperature, TA, can be calculated
using the thermal resistance from case to ambient ( CA) of the given
package. The following equation relates ambient and case tempera-
tures:
Once the CPU is in Standby Mode, any interrupt, including the inter-
nally generated timer interrupt, will cause the CPU to exit Standby
Mode.
ꢜꢝꢍꢊꢋꢈꢁꢅꢞꢂꢒꢐꢇꢔꢍꢊꢈꢎꢇꢂꢒꢐ
TA = TC - P *
CA
The RC4640 utilizes special packaging techniques to improve the
thermal properties of high-speed processors. The RV4640 is packaged
using cavity-up packaging in a 128-pin thermally enhanced PQFP
package (“DU”) with a drop-in heat spreader, for devices with low peak
power. The R4640 utilizes the MQUAD package for higher power
consumption devices (the “MU” package), which is an all-aluminum
package with the die attached to a normal copper lead frame mounted to
the aluminum casing.
where P is the maximum power consumption at hot temperature,
calculated by using the maximum ICC specification for the device.
Typical values for CA at various air flows are shown in Table 5.
128 QFP (DU)
17
9
7
5
8
4
7
3
Due to the heat-spreading effect of the aluminum, the MQUAD
package allows for an efficient thermal transfer between the die and the
case. The aluminum offers less internal resistance from one end of the
package to the other, reducing the temperature gradient across the
package and therefore presenting a greater area for convection and
conduction to the PCB for a given temperature. Even nominal amounts
of air flow will dramatically reduce the junction temperature of the die,
resulting in cooler operation. The MQUAD package is pin and socket
compatible with the 128-pin QFP package.
128 MQUAD (MU)
20 12
9.5
6.5
Table 5 Thermal Resistance ( CA) at Various Airflows
Note that the RC4640 implements advanced power management to
substantially reduce the average power dissipation of the device. This
operation is described in the IDT79RC4640/ IDT79RC4650 RISC
Processor Hardware User’s Manual.
and the RV4640
The R4640
are guaranteed in a case temperature
range of 0°C to +85°C for commercial temperature parts and the
RV4640 in a case temperature range of -40°C to +85°C for industrial
MasterClock
SysAD
Addr
Read
Data0
CData
Data1
CData
Data7
CEOD
Data6
CData
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Figure 3 RC4640 Block Read Request
8 of 23
March 28, 2000
IDT79RC4640™
ꢆꢈꢎꢈꢅꢘꢝꢍꢍꢎꢅ ꢍꢗꢇꢐꢇꢂꢒꢅꢓꢇꢐꢎꢂꢊꢚ
Features:
–
Added 200MHz operating frequency
Features:
–
–
Added 32-bit bus interface info
Deleted items from low-power operation descriptions.
Features:
–
Added 400MB/sec bandwidth reference
Hardware Overview:
–
–
Added detailed descriptions of features.
Changed Boot Time Mode Stream table values for mode bit
12.
Power Consumption (RV4640):
–
Upgraded System Condition Icc active parameters
DC Electrical Characteristics:
The CIN and COUT values have been changed.
–
Corrected several incorrect references to tables and figures.
–
AC Electrical Characteristics:
–
In System Interface Parameters tables (RC4640 and
RV4640), Data Setup and Data Hold minimums changed.
–
–
Replaced existing figure in Mode Configuration Interface
Reset Sequence section with 3 reset figures.
Revised values in System Interface Parameters table.
Valid Combinations:
–
List of valid combinations has been corrected.
Features:
–
Added preliminary 150 MHz operation frequency
Thermal Considerations:
–
Added thermally enhanced packaging (“DU”) and drop-in heat
spreader information.
–
Upgraded 80 to 133MHz speed grade specs to “final.”
Features:
–
–
Added 180 MHz spreader information
Eliminated 80 MHz
MasterClock
Addr
Write
Data6
CData
SysAD
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Data0
CData
Data1
CData
Data7
CEOD
Figure 4 RC4640 Block Write Request
9 of 23
March 28, 2000
IDT79RC4640™
0
Reserved (must be zero)
4s:1
Writeback data rate:
32-bit
0 → Ω
1 → WWx
2 → WWxx
3 → WxWx
4 → WWxxx
5 → WWxxxx
6 → WxxWxx
7 → WWxxxxxx
8 → WxxxWxxx
9-15 reserved
7:5
Clock multiplier:
0 → 2
1 → 3
2 → 4
3 → 5
4 → 6
5 → 7
6 → 8
7 reserved
8
0 → Little endian
1 → Big endian
10:9
00 → R4000 compatible
01 → reserved
10 → pipelined writes
11 → write re-issue
11
Disable the timer interrupt on Int[5]
12
Must be 1
14:13
Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slowest)
255:15
Must be zero
Table 6 Boot-time mode stream
10 of 23
March 28, 2000
IDT79RC4640™
!ꢇꢒꢅꢆꢍꢐꢃꢊꢇꢑꢎꢇꢂꢒ
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4640. Pin names ending with an asterisk (*) identify pins
that are active when low.
System Bus Interface
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
Input
Output
Input
Input
Input
External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
SysAD(31:0) Input/Output System address/data bus
A 32-bit address and data bus for communication between the processor and an external agent.
SysADC(3:0) Input/Output System address/data check bus
A 4-bit bus containing parity check bits for the SysAD bus during data bus cycles.
SysCmd(8:0) Input/Output System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
SysCmdP
Input/Output Reserved system command/data identifier bus parity
For the RC4640 this signal is unused on input and zero on output.
Clock/Control interface
MasterClock Input
Master clock
Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipelineoperation
frequency is derived by multiplying this clock up by the factor selected during boot initialization.
VCCP
VSSP
Input
Input
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
Quiet VSS for PLL
Quiet VSS for the internal phase locked loop.
Interrupt interface
Int*(5:0)
Input
Interrupt
Six general processor interrupts, bit-wise OR’ d with bits 5:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, OR’d with bit 6 of the interrupt register.
Initialization interface
Input
VCCOk
VCC is OK
When asserted, this signal indicates to the RC4640 that the power supply has been above Vcc minimum for more than 100 millisec-
onds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream.
11 of 23
March 28, 2000
IDT79RC4640™
ColdReset*
Reset*
Input
Input
Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock.
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or syn-
chronously to initiate a warm reset. Reset must be de-asserted synchronously with MasterClock.
ModeClock
ModeIn
Int*(5:0)
NMI*
Output
Input
Input
Input
Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by 256.
Boot mode data in
Serial boot-mode data input.
Interrupt
Six general processor interrupts, bit-wise OR’ d with bits 5:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, OR’d with bit 6 of the interrupt register.
"ꢙꢐꢂꢁꢏꢎꢍꢅꢛꢈ#ꢇꢋꢏꢋꢅ ꢈꢎꢇꢒꢉꢐ
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
±
±
±
V
Terminal Voltage with respect to GND
Operating Temperature(case)
Case Temperature Under Bias
Storage Temperature
–0.51 to +7.0
0 to +85
–55 to +125
–55 to +125
202
–0.51 to +4.6
0 to +85
–55 to +125
–55 to +125
202
–0.51 to +4.6
-40 to +85
–55 to +125
–55 to +125
202
V
TERM
TC
°C
°C
°C
mA
mA
TBIAS
TSTG
I
DC Input Current
IN
IOUT
DC Output Current
503
503
503
1.
NVIN minimum = –2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.
When VIN < 0V or VIN > VCC
2.
3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
ꢍꢃꢂꢋꢋꢍꢒꢔꢍꢔꢅꢖꢑꢍꢊꢈꢎꢇꢂꢒꢅꢜꢍꢋꢑꢍꢊꢈꢎꢏꢊꢍꢅꢈꢒꢔꢅꢘꢏꢑꢑꢁꢚꢅ$ꢂꢁꢎꢈꢉꢍ
Commercial
Industrial
0°C to +85°C (Case)
-40°C + 85°C (Case)
0V
0V
5.0V±5%
3.3V±5%
3.3V±5%
N/A
12 of 23
March 28, 2000
IDT79RC4640™
ꢆꢞꢅ%ꢁꢍꢃꢎꢊꢇꢃꢈꢁꢅꢞꢝꢈꢊꢈꢃꢎꢍꢊꢇꢐꢎꢇꢃꢐꢅ&ꢅꢞꢂꢋꢋꢍꢊꢃꢇꢈꢁꢅꢜꢍꢋꢑꢍꢊꢈꢎꢏꢊꢍꢅ ꢈꢒꢉꢍ& '(')
= 5.0 5
± %, TCASE = 0°C to +85°C)
(V
CC
V
—
0.1V
—
—
0.1V
—
|IOUT| = 20uA
|IOUT| = 4mA
OL
V
VCC - 0.1V
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
OL
V
2.4V
–0.5V
2.0V
—
2.4V
–0.5V
2.0V
—
OH
V
0.2V
0.2V
CC
—
—
IL
CC
V
VCC + 0.5V
VCC + 0.5V
IH
I
±10uA
10pF
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
CIN
—
—
—
—
COUT
I/O
—
10pF
—
10pF
—
20uA
—
20uA
Input/Output Leakage
LEAK
!ꢂꢕꢍꢊꢅꢞꢂꢒꢐꢏꢋꢑꢎꢇꢂꢒ& '(')ꢅ
System Condition:
100/50MHz
133/67MHz
—
2
2
ICC
standby
—
—
75 mA
—
—
100 mA
CL = 0pF3
CL = 50pF
2
2
150 mA
200 mA
2
2
2
2
active,
64-bit bus
option
700 mA
900 mA
900 mA
950 mA
CL = 0pF
No SysAd activity3
2
2
2
2
800 mA
1000 mA
1000 mA
1100 mA
CL = 50pF
R4x00 compatible writes,
TC = 25oC
2
4
2
4
800 mA
1200 mA
1000 mA
1350 mA
CL = 50pF
Pipelined writes or write re-issue,
TC = 25oC
1.
Typical integer instruction mix and cache miss rates, Vcc = 3.3V, TA = 25×C.
2.
3.
4.
These are not tested. They are the results of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
13 of 23
March 28, 2000
IDT79RC4640™
"ꢞꢅ%ꢁꢍꢃꢎꢊꢇꢃꢈꢁꢅꢞꢝꢈꢊꢈꢃꢎꢍꢊꢇꢐꢎꢇꢃꢐꢅ&ꢅꢞꢂꢋꢋꢍꢊꢃꢇꢈꢁꢅꢜꢍꢋꢑꢍꢊꢈꢎꢏꢊꢍꢅ ꢈꢒꢉꢍ& '(')
(V =5.0V ± 5%; TCASE = -0°C to +85°C)
CC
Pipeline clock frequency
MasterClock HIGH
PClk
tMCHIGH
tMCLOW
—
50
4
100
—
—
50
40
±250
5
50
3
133
—
—
67
40
±250
4
MHz
ns
Transition ≤ tMCRise/Fall
MasterClock LOW
Transition ≤ tMCRise/Fall
4
3
ns
MasterClock Frequency1
—
—
—
—
—
—
25
20
—
—
—
—
25
15
—
—
—
—
MHz
ns
—
MasterClock Period
tMCP
2
Clock Jitter for MasterClock tJitterIn
ps
2
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tMCRise
ns
2
tMCFall
5
4
ns
2
tModeCKP
256*
tMCP
256*
tMCP
ns
1.
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
Guaranteed by design.
2.
ꢘꢚꢐꢎꢍꢋꢅ*ꢒꢎꢍꢊ+ꢈꢃꢍꢅ!ꢈꢊꢈꢋꢍꢎꢍꢊꢐ& '(')
(V =5.0V ± 5%; TCASE = 0°C to +85°C)
CC
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
Data Output1
Data Output Hold
Data Setup
tDO = Max
mode14..13 = 10 (Fastest)
mode14..13 = 11 (85%)
mode14..13 = 00 (66%)
1.02
9
1.02
9
ns
mode
= 01 (slowest)
2.02
1.0
12
—
2.0
1.0
12
—
ns
ns
14..13
3
tDOH
mode14..13 = 10
mode14..13 = 11
mode14..13 = 00
mode14..13 = 01
tDS
t
t
= 5ns
= 5ns
5.5
2
—
—
4.5
1.5
—
—
ns
ns
rise
fall
Data Hold
tDH
1.
Capacitive load for all output timings is 50pF.
Guaranteed by design.
2.
3.
50pf loading on external output signals, fastest settings
14 of 23
March 28, 2000
IDT79RC4640™
ꢀꢂꢂꢎ,ꢎꢇꢋꢍꢅ*ꢒꢎꢍꢊ+ꢈꢃꢍꢅ!ꢈꢊꢈꢋꢍꢎꢍꢊꢐ& '(')
(V =5.0V ± 5%; TCASE = 0°C to +85°C)
CC
Mode Data Setup
Mode Data Hold
tDS
—
—
3
0
—
—
3
0
—
—
Master Clock Cycle
Master Clock Cycle
tDH
Load Derate
CLD
—
—
2
—
2
ns/25pF
= 3.3 5
± %, Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
(V
CC
V
—
0.1V
—
—
0.1V
—
|IOUT| = 20uA
|IOUT| = 4mA
OL
V
VCC - 0.1V
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
OL
V
2.4V
–0.5V
2.4V
–0.5V
OH
V
0.2V
0.2V
CC
—
—
IL
CC
V
0.7V
VCC + 0.5V
0.7V
CC
VCC + 0.5V
IH
CC
I
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
C
—
—
IN
COUT
I/O
10pF
10pF
20uA
20uA
Input/Output Leakage
LEAK
V
—
0.1V
—
—
0.1V
—
0.1V
—
|IOUT| = 20uA
OL
V
VCC - 0.1V
VCC - 0.1V
—
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
—
0.4V
—
|IOUT| = 4mA
OL
V
2.4V
–0.5V
2.4V
–0.5V
2.4V
–0.5V
OH
V
0.2VCC
0.2V
0.2V
CC
—
—
IL
CC
V
0.7V
VCC + 0.5V
0.7V
VCC + 0.5V
0.7V
CC
VCC + 0.5V
IH
CC
CC
I
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
C
—
—
IN
COUT
I/O
10pF
10pF
10pF
20uA
20uA
20uA
Input/Output Leakage
LEAK
1.
Industrial temperature range is not available at 267MHz
15 of 23
March 28, 2000
IDT79RC4640™
!ꢂꢕꢍꢊꢅꢞꢂꢒꢐꢏꢋꢑꢎꢇꢂꢒ& $'(')
System Condition
133/67MHz
150/75MHz
—
2
2
ICC
standby
—
—
60 mA
—
—
60mA
CL = 0pF3
2
2
110 mA
110mA
CL = 50pF
2
2
2
2
active,
400 mA
450 mA
450 mA
500mA
CL = 0pF, No SysAd activity3
64-bit bus
option
2
2
2
2
450 mA
500 mA
500mA
550mA
CL = 50pF R4x00 |compatible writes
TC = 25oC
2
4
2
4
500 mA
575 mA
550mA
625mA
CL = 50pF Pipelined writes or Write
re-issue, TC = 25oC3
1.
Typical integer instruction mix and cache miss rates, Vcc = 3.3V, TA = 25×C.
2.
3.
4.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
System Condition
180/60MHz
200/67MHz
267/89MHz
—
2
2
2
ICC
standby
—
—
60mA
—
—
60mA
—
—
60mA
CL = 0pF3
2
2
2
110mA
110mA
110mA
CL = 50pF
2
2
2
2
2
2
active,
610 mA
680mA
685mA
760mA
650mA
800mA
CL = 0pF, No SysAd activity3
64-bit bus
option
2
2
2
2
2
2
680mA
750mA
760mA
835mA
750mA
900mA
CL = 50pF R4x00 compatible writes
TC = 25oC
2
4
2
4
2
4
750mA
850mA
835mA
950mA
900mA
1200mA
CL = 50pF Pipelined writes or Write
re-issue, TC = 25oC
1.
Typical integer instruction mix and cache miss rates, Vcc = 3.3V, TA = 25×C.
2.
3.
4.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
16 of 23
March 28, 2000
IDT79RC4640™
ꢅ"ꢞꢅ%ꢁꢍꢃꢎꢊꢇꢃꢈꢁꢅꢞꢝꢈꢊꢈꢃꢎꢍꢊꢇꢐꢎꢇꢃꢐꢅ&ꢅꢞꢂꢋꢋꢍꢊꢃꢇꢈꢁ-*ꢒꢔꢏꢐꢎꢊꢇꢈꢁꢅꢜꢍꢋꢑꢍꢊꢈꢎꢏꢊꢍꢅ ꢈꢒꢉꢍ&
$'(')
(V =3.3V ± 5%; Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
CC
Note: Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
Pipeline clock Frequency
MasterClock HIGH
PClk
50
3
133
—
—
67
40
±250
4
MHz
ns
tMCHIGH
tMCLOW
Transition ≤ tMCRise/Fall
MasterClock LOW
Transition ≤ tMCRise/Fall
3
ns
MasterClock Frequency
MasterClock Period
—
—
—
—
—
—
25
15
—
—
—
—
MHz
ns
—
tMCP
1
Clock Jitter for MasterClock
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tJitterIn
ps
1
tMCRise
ns
1
tMCFall
4
ns
1
tModeCKP
256*
tMCP
ns
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Pipeline clock Frequency
MasterClockHIGH
50
3
150
—
—
75
40
±250
3
50
3
180
—
50
3
200
—
—
100
40
100
3
267
—
—
125
20
MHz
ns
MasterClockLOW
3
3
—
3
3
ns
MasterClock Frequency1
MasterClock Period
25
13.3
—
—
—
—
25
11.1
—
—
—
—
90
25
10
—
—
—
—
50
8
MHz
ns
40
Clock Jitter for MasterClock
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
±250
2.5
2.5
±250
2
—
—
—
—
±250
2
ps
ns
3
2
2
ns
256*
tMCP
256*
tMCP
256*
tMCP
256*
tMCP
ns
1.
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
17 of 23
March 28, 2000
IDT79RC4640™
ꢘꢚꢐꢎꢍꢋꢅ*ꢒꢎꢍꢊ+ꢈꢃꢍꢅ!ꢈꢊꢈꢋꢍꢎꢍꢊꢐ& $'(')
(V =3.3V ± 5%; Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
CC
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
Data Output1
tDM= Min
DO = Max
mode
mode
mode
= 10 (fastest)
= 01 (slowest)
= 10 (fastest)
1.0
2.0
1.0
4.5
1.5
9
1.0
2.0
1.0
4.5
1.5
9
ns
ns
ns
ns
ns
14..13
14..13
14..13
t
12
—
—
—
12
—
—
—
2
Data Output Hold
Input Data Setup
tDOH
tDS
t
= 5ns
= 5ns
rise
t
fall
Input Data Hold
tDH
1.
Capacitive load for all output timings is 50pF.
2.
50pf loading on external output signals, fastest settings
Data Output
t
DM= Min
mode14..13 = 10 (fastest)
mode14..13 = 01 (slowest)
mode = 10 (fastest)
1.0
2.0
1.0
4.5
1.5
9
1.0
2.0
1.0
4.5
1.5
4.5
5.0
—
—
—
1.0
—
4.5
ns
tDO = Max
10
—
—
—
5.0
—
—
—
ns
ns
ns
ns
1
Data Output Hold
Data Input
tDOH
1.0
2.5
1.0
14..13
tDS
trise = 3ns
tfall = 3ns
tDH
1.
50pf loading on external output signals, fastest settings
ꢀꢂꢂꢎꢅꢜꢇꢋꢍꢅ*ꢒꢎꢍꢊ+ꢈꢃꢍꢅ!ꢈꢊꢈꢋꢍꢎꢍꢊꢐ& $'(')ꢅ
Min Max
Min
Max
Min Max
Min Max
Min
Max
Mode Data
Setup
tDS
—
—
3
—
3
—
3
—
3
—
3
—
ns
ns
Master Clock
Cycle
Mode Data
Hold
tDH
0
—
0
—
0
—
0
—
0
—
Master Clock
Cycle
Load Derate
CLD
—
—
2
—
2
—
2
—
2
—
1
ns/25pF
18 of 23
March 28, 2000
IDT79RC4640™
ꢜꢇꢋꢇꢒꢉꢅꢞꢝꢈꢊꢈꢃꢎꢍꢊꢇꢐꢎꢇꢃꢐ& $'(')
1
2
3
4
Cycle
MasterClock
t
MCkHigh
t
MCkLow
t
MCkP
SysAD,SysCmd Driven
SysADC
D
D
D
t
t
DOH
t
DM
DZ
t
DO
SysAD,SysCmd Received
SysADC
D
D
D
D
t
DS
t
DH
Control Signal CPU driven
ValidOut*
Release*
t
DO
t
DOH
Control Signal CPU received
RdRdy*
WrRdy*
ExtRqst*
ValidIn*
NMI*
t
t
DS
DH
Int*(5:0)
* = active low signal
Figure 5 System Clocks Data Setup, Output, and Hold timing
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March 28, 2000
IDT79RC4640™
2.3V
2.3V
Vcc
MasterClock
(MClk)
TDS
> 100ms
256
MClk
VCCOK
ModeClock
ModeIn
256 MClk cycles
cycles
TMDS
TMDH
Bit
255
Bit 1
Bit 0
TDS
TDS
TDS
> 64K MClk cycles
ColdReset*
Reset*
> 64 MClk cycles
TDS
Figure 6 Power-on Reset
Vcc
Master
Clock
(MClk)
TDS
TDS
> 100ms
256
MClk
VCCOK
256 MClk cycles
cycles
ModeClock
ModeIn
TMDS
TMDH
Bit
1
Bit
255
Bit
0
TDS
TDS
> 64K MClk cycles
ColdReset*
Reset*
> 64 MClk cycles
TDS
TDS
Figure 7 Cold Reset
Vcc
Master
Clock
(MClk)
VCCOK
256 MClk cycles
ModeClock
ModeIn
ColdReset*
Reset*
TDS
TDS
> 64 MClk cycles
Figure 8 Warm Reset
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March 28, 2000
IDT79RC4640™
!ꢝꢚꢐꢇꢃꢈꢁꢅꢘꢑꢍꢃꢇ+ꢇꢃꢈꢎꢇꢂꢒꢐꢅ,ꢅ./0,!ꢇꢒꢅꢛ12"ꢆ-1ꢌ!
70
J X 45 0
3X
L
D
D1
PIN 1 ID
h X 450
e
C
A1
E1
E
A2
A
NOTES:
SYMBOLS
MIN
3.50
.25
MAX
3.86
.51
1. ALL DIMENSIONS ARE IN MILLIMETERS.
A
A1
A2
b
3.17
.30
3.43
.45
C
.13
.23
D/E
D1/E1
e
31.00
27.59
31.40
27.79
.80 BSC
J
.20 REF
.89 REF
h
L
.68
-
21 of 23
March 28, 2000
IDT79RC4640™
ꢞ'(')ꢅ!ꢈꢃꢄꢈꢉꢍꢅ!ꢇꢒ,ꢖꢏꢎ
N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active
when low.
1
N.C.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Vcc
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Vcc
97
Vcc
2
SysCmd2
Vcc
Vss
SysAD28
ColdReset*
SysAD27
Vss
98
Vss
3
SysAD13
SysAD14
Vss
99
SysAD19
ValidIn*
Vcc
4
Vss
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
5
SysAD5
WrRdy*
ModeClock
SysAD6
Vcc
6
Vcc
Vcc
Vss
7
SysAD15
Vss
N.C.
SysAD18
Int0*
8
SysAD26
N.C.
9
Vcc
SysAD17
Vcc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Vss
SysADC1
Vss
Vss
SysCmd3
SysAD7
SysCmd4
Vcc
Vcc
Vss
Vcc
SysAD25
Vss
Int1*
MasterClock
VssP
VccP
Vss
SysAD16
Int2*
Vcc
Vss
SysAD24
SysADC2
Vss
Vcc
SysADC0
SysCmd5
SysAD8
Vcc
Vss
Vss
Int3*
Vss
Vcc
SysAD0
Int4*
Vss
NMI*
Vss
Vss
SysAD23
Release*
Vss
Vcc
SysCmd6
SysAD9
Vcc
Vss
Vss
SysADC3
VccOK
Vss
SysAD1
Int5*
Vcc
Vss
SysAD22
Modein
RdRdy*
SysAD21
Vss
SysAD2
Vcc
SysCmd7
SysAD10
SysCmd8
Vcc
Vcc
SysAD31
Vss
Vss
SysCmd0
SysAD3
Vcc
Vcc
Vss
SysAD30
SysAD29
Reset*
Vss
Vcc
SysAD11
SysCmdP
SysAD12
ExtRqst*
SysAD20
ValidOut*
Vss
SysCmd1
SysAD4
22 of 23
March 28, 2000
IDT79RC4640™
ꢖꢊꢔꢍꢊꢇꢒꢉꢅ*ꢒ+ꢂꢊꢋꢈꢎꢇꢂꢒ
IDT79
YY
XXXX
A
999
A
Temp range/
Process
Package
Speed
Device
Type
Operating
Voltage
Commercial
Blank
I
°
°
(0 C to +85 C Case)
Industrial
°
°
(-40 C to +85 C Case)
DU
MU
128-pin PQFP
128-pin MQUAD
100
133
150
180
200
100 MHz PClk
MHz PClk
133
150 MHz PClk
180 MHz PClk
200 MHz PClk
267 MHz PCLK
267
64-bit processor
w/ DSP Capability
4640
5.0+/-5%
3.3+/-5%
R
RV
$ꢈꢁꢇꢔꢅꢞꢂꢋꢙꢇꢒꢈꢎꢇꢂꢒꢐ
IDT79R4640 - 100, 133MHz - MU
MQUAD package, Commercial Temperature
QFP package, Commercial Temperature
QFP package, Industrial Temperature
IDT79RV4640 - 133, 150, 180, 200, 267MHz - DU
IDT79RV4640 - 133, 150, 180, 200MHz - DUI
CORPORATE HEADQUARTERS
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