IDT79RV5000-180BS [IDT]
64-BIT, 180MHz, RISC PROCESSOR, PBGA272, SBGA-272;
| 型号： | IDT79RV5000-180BS |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 64-BIT, 180MHz, RISC PROCESSOR, PBGA272, SBGA-272 |
| 文件： | 总16页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MULTI-ISSUE
64-BIT MICROPROCESSOR
79RC5000
◆
Large, efficient on-chip caches
32KB Instruction Cache, 32KB Data Cache
2-set associative in each cach
Virtually indexed and physically tagged to minimize cache
flushes
Write-back and write-through selectable on a per page
basis
Critical word first cache miss processing
Supports back-to-back loads and stores in any combination
at full pipeline rate
Features
-
-
-
◆
Dual issue super-scalar execution core
-
-
300 MHz frequency
Dual issue floating-point ALU operations with other
instruction classes
Traditional 5-stage pipeline, minimizes load and branch
latencies
-
-
-
-
◆
Single-cycle repeat rate for most floating point ALU oper-
ations
◆
◆
High level of performance for a variety of applications
High-performance 64-bit integer unit achieves 400 dhry-
stone MIPS (dhrystone 2.1)
Ultra high-performance floating-point accelerator,
directly implementing single- and double-precision oper-
ations achieves 600mflops
Extremely large on-chip primary cache
On-chip secondary cache controller
MIPS-IV 64-bit ISA for improved computation
Compound floating-point operations for 3D graphics and
floating-point DSP
High-performance memory system
-
-
-
-
-
-
Large primary caches integrated on-chip
Secondary cache control interface on-chip
High-frequency 64-bit bus interface runs up to 125MHz
Aggregate bandwidth of on-chip caches, system interface
of 5.6GB/s
High-performance write protocols for graphics and data
communications
Compatible with a variety of operating systems
Windows™ CE
Numerous MIPS-compatible real-time operating systems
-
-
-
◆
◆
-
-
-
-
Conditional move operations
◆
Uses input system clock, with processor pipeline clock multi-
plied by a factor of 2-8
◆
◆
Large on-chip TLB
Active power management, including use of WAIT operation
Block diagram
Phase Lock Loop
Data Tag A
Instruction Set A
Instruction Select
Data Set A
Store Buffer
DTLB Physical
SysAD
Integer Instruction Register
FP Instruction Register
Address Buffer
Instruction Tag A
ITLB Physical
Write Buffer
Read Buffer
Data Set B
DBus
Instruction Set B
IntIBus
Instruction Tag B
FPIBus
Control
AuxTag
Joint TLB
Tag
Load Aligner
Floating Point Register File
Unpacker/Packer
Integer Register File
Integer/Address Adder
Coprocessor 0
Data TLB Virtual
DVA
System/Memory
Control
Floating Point
MAdd,Add,Sub, Cvt
Div, SqRt
Shifter/Store Aligner
IVA
PC Incrementer
Branch Adder
Logic Unit
ABus
Instruction TLB Virtual
Program Counter
Integer Multiply, Divide
The IDT logo is a registered trademark and RC4600, RC4640, RC4650, RC4700, RC5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc.
MIPS is a registered trademark of MIPS Computer Systems, Inc.
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June 21, 1999
79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
Integer pipeline
The RC5000 is a limited dual-issue machine that utilizes a tradi-
tional 5-stage integer pipeline. This basic integer pipeline of the
RC5000 is illustrated in Figure 1. The integer instruction execution
speed is tabulated (in number of pipeline clocks) as follows:
DESCRIPTION
The RC5000 serves many performance critical embedded
applications, such as high-end internetworking systems, color
printers, and graphics terminals.
The RC5000 is optimized for high-performance applications,
with special emphasis on system bandwidth and floating point
operations, through integration of high-performance computational
units and a high-performance memory hierarchy. For this class of
application, the result is a relatively low-cost CPU capable of
approximately 400 Dhrystone MIPS.
Operation
Latency
Repeat
Load
2
1
Store
2
1
IDT’s objectives in offering the RC5000 include:
MULT/MULTU
DMULT/DMULTU
DIV/DIVU
DDIV/DDIVU
Other Integer ALU
Branch
8
8
◆
Offering a high performance upgrade path to existing
12
36
68
1
12
36
68
1
embedded customers in the internetworking, office auto-
mation and visualization markets.
◆
Providing a significant improvement in the floating- point
performance currently available in a moderately priced
MIPS CPU.
2
2
◆
Providing improvements in the memory hierarchy of desk-
Jump
2
2
top systems by using large primary caches and integrat-
ing a secondary cache controller.
Table 1: Integer Instruction Execution Speed
◆
Enabling improvements in performance through the use of
The RC5000’s short pipeline keeps the load and branch latencies
very low. The caches contain special logic that allows any combina-
tion of loads and stores to execute in back-to-back cycles without
requiring pipeline slips or stalls. (This assumes that the operation
does not miss in the cache.)
the MIPS-IV ISA.
Instruction issue mechanism
The RC5000 recognizes two general classes of instructions for
multi-issue:
◆
Floating-point ALU
◆
All others
These instruction classes are pre-decoded by the RC5000, as
they are brought on-chip. The pre-decoded information is stored in
the instruction cache.
Assuming that there are no pending resource conflicts, the
RC5000 can issue one instruction per class per pipeline clock
cycle. Note that this broad separation of classes insures that there
are no data dependencies to restrict multi-issue.
However, long-latency resources in either the floating-point ALU
(e.g. DIV or SQRT instructions) or instructions in the integer unit
(such as multiply) can restrict the issue of instructions. Note that
the R5000 does not perform out-of-order or speculative execution;
instead, the pipeline slips until the required resource becomes
available.
There are no alignment restrictions on dual-issue instruction
pairs. The RC5000 fetches two instructions from the cache per
cycle. Thus, for optimal performance, compilers should attempt to
align branch targets to allow dual-issue on the first target cycle,
since the instruction cache only performs aligned fetches.
Instruction set architecture
The RC5000 implements the MIPS-IV 64-bit ISA, including CP1
and CP1X functional units (and their instruction set).
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
I0
I1
I2
1I
2I
1R
1I
2R
2I
1A
1R
1I
2A
2R
2I
1D
1A
1R
2D
2A
2R
1W
1D
1A
2W
2D
2A
1W
1D
2W
2D
1
W
I3
I4
1I
2I
1R
1I
2R
2I
1A
1R
2A
2R
1D
1A
one cycle
Figure 1 R5000 Integer Pipeline Stages
Key to Figure
1I-1R
2I
Instruction cache access
Instruction virtual to physical address translation
Data cache access and load align
2A-
2D
1D
1D-
2D
Data virtual to physical address translation
Virtual to physical address translation
2R
2R
2R
2R
1A
Register file read
Bypass calculation
Instruction decode
Branch address calculation
Issue or slip decision
Integer add, logical, shift
1A-
2A
1A
2A
1A
2W
Data virtual address calculation
Store align
Branch decision
Register file write
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
The following equation relates ambient and case temperatures:
RC5000 Computational Units
The RC5000 contains the following computational units:
Integer ALU. The RC5000 implements a full, single-cycle 64-bit
ALU for all integer ALU functions other than multiply and divide.
Bypassing is used to support back-to-back ALU operations at the
full pipeline rate, without requiring stalls for data dependencies.
Integer Multiply/Divide Unit. This unit is separated from the
primary ALU, to allow these longer latency operations to run in
parallel with other operations. The pipeline stalls only if an attempt
to access the HI or LO registers is made before the operation
completes.
Floating-point ALU. This unit is responsible for all CP1/CP1X
ALU operations other than DIV/SQRT. The unit is pipelined to allow
a single-cycle repeat rate for single-precision operations
Floating-point DIV/SQRT unit. This unit is separated from the
other floating-point ALU, so that these long latency operations do
not prevent the issue of other floating point operations.
In addition, the RC5000 implements separate logical units to
implement loads, stores, and branches.
TA = TC - P * ÆCA
where P is the maximum power consumption at hot temperature,
calculated by using the maximum ICC specification for the device.
Typical values for ÆCA at various airflows are shown in Table 1.
ÆCA
Airflow (ft/min)
PGA
0
200
7
400
5
600
3
800
2.5
1000
2
16
BGA
14
6
4
3
2.5
2
Table 2: Thermal Resistance (ÆCA) at Various Airflows
Note: The RC5000 implements advanced power management to
substantially reduce the average power dissipation of the device. This
operation is described in the IDT79RV5000 RISC Microprocessor
Reference Manual.
Operating frequency
Note:
The input clock operates in a frequency range of 33MHz to
100MHz. The pipeline frequency for the RC5000 is 2 to 8 times the
input clock (up to the maximum for the speed grade of CPU).
Per the RC5000 Documentation errata, Revicion 1.0, dated
February 1999 and per the RC5000 Device errata, dated February
1999, mode bits 20, 33 and 37 must be set to 1.
Thermal considerations
Revision history
The RC5000 utilizes special packaging techniques, to improve
the thermal properties of high-speed processors. The RC5000 is
packaged using cavity down packaging in a 223-pin PGA package
with integral thermal slug, and a 272-pin BGA package. These
packages effectively dissipate the power of the CPU, increasing
device reliability.
Changes to version dated January 1996:
Pin Description section:
-
Corrected pin list for Clock/Control, Initialization, and
Secondary Cache interfaces.
Advance Pin-Out section:
-
Changed pins AA19 and AA21 from Vcc to Vss.
The RC5000 utilizes an all-aluminum package with the die
attached to a normal copper lead frame mounted to the aluminum
casing. Due to the heat-spreading effect of the aluminum, the
package allows for an efficient thermal transfer between the die
and the case. The aluminum offers less internal resistance from
one end of the package to the other, reducing the temperature
gradient across the package and therefore presenting a greater
area for convection and conduction to the PCB for a given temper-
ature. Even nominal amounts of airflow will dramatically reduce the
junction temperature of the die, resulting in cooler operation.
The RC5000 is guaranteed in a case temperature range of 0° to
+85° C. The type of package, speed (power) of the device, and
airflow conditions affect the equivalent ambient temperature condi-
tions that will meet this specification.
Changes to version dated March 1997:
-
Upgraded data sheet status from “Preliminary” to Final.
Added section on thermal considerations
Added section on absolute maximum ratings
-
-
Changes to version dated June 1997:
-
Revised Power Consumption and System Interface Param-
eters
Changes to version dated September 1997:
-
Added user notation on Boot Mode Bits 20 and 33 for 200
MHz frequency
Changes to version dated June 1998:
-
Added 250 MHz
Changed naming conventions
-
Changes to version dated June 1999:
-
Added 267 MHz and 300 MHz
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ÆCA) of the given package.
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
Logic diagram
64
8
2
SysAD(63:0)
ScWord (1:0)
ScTCE*
SysADC(7:0)
SysCmd(8:0)
SysCmdP
ValidIn*
9
ScTDE*
ScTOE*
ScCLR*
ValidOut*
ExtRqst*
ScDCE*
ScDOE*
Release*
RdRdy*
ScCWE*
ScLine (15:0)
16
WrRdy*
ScMATCH
ScVALID
RC5000
Logic
Symbol
6
SysClock
VccP
Int (5:0)*
NMI*
VssP
34
34
Vcc
Vss
BigEndian
ModeClock
ModeIN
VccOk
ColdReset*
Reset*
JTDI
JTDO
JTMS
JTCK
Table 3: RC5000 Logic Symbol Diagram
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
Pin description
The RC5000 implements a bus similar to that of the RC4700. Table 2 lists and describes the RC5000 signals.
Pin Name
Type
Description
System interface
ExtRqst*
Input
External Request.
Signals that the system interface needs to submit an external request.
Release*
RdRdy*
WrRdy*
ValidIn*
Output
Input
Input
Input
Release Interface.
Signals that the processor is releasing the system interface to slave state
Read Ready.
Signals that an external agent can now accept a processor read.
Write Ready.
Signals that an external agent can now accept a processor write request.
Valid Input.
Signals that an external agent is now driving a valid address or data on the SysAD bus and a
valid com mand or data identifier on the SysCmd bus.
ValidOut*
Output
Valid Output.
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
com mand or data identifier on the SysCmd bus.
SysAD(63:0)
Input/Output System Address/Data bus.
A 64-bit address and data bus for communication between the processor and an external
agent.
SysADC(7:0)
SysCmd(8:0)
Input/Output System Address/Data check bus.
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
Input/Output System Command/data identifier bus.
A 9-bit bus for command and data identifier transmission between the processor and an exter-
nal agent.
SysCmdP
Input/Output Reserved System Command/data identifier bus parity.
For the RC5000, unused on input and zero on output.
Clock/control interface
SysClock
Input
Master Clock.
Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock
up.
VCCP
VSSP
Input
Input
Quiet VCC for PLL.
Quiet VCC for the internal phase locked loop.
Quiet VSS for PLL.
Quiet VSS for the internal phase locked loop.
Interrupt interface
Int(5:0)*
Input
Input
Interrupt.
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register.
NMI*
Table 4: RC5000 Signal Names and Descriptions (Page 1 of 3)
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79RC5000
JTAG interface:
MULTI-ISSUE 64-BIT MICROPROCESSOR
JTDI
Input
Input
Output
Input
JTAG Data In.
Connected directly to JTDO. No JTAG implemented; should be pulled High.
JTAG Clock Input.
JTCK
JTDO
JTMS
Unused input; should be pulled High.
JTAG Data Out.
Connected directly to JTDI. If no external scan used, this is a no connect.
JTAG Command.
Unused input. Should be pulled High.
Initialization interface:
VCCOk
Input
VCC is OK.
When asserted, this signal indicates to the RC5000 that the power supply has been aboveVcc
mini mum for more than 100 milliseconds and will remain stable. The assertion of VCCOk ini-
tiates the read ing of the boot-time mode control serial stream.
ColdReset*
Reset*
Input
Input
Cold Reset.
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-
asserted syn chronously with SysClock.
Reset.
This signal must be asserted for any reset sequence. It may be asserted synchronously or
asynchro nously for a cold reset, or synchronously to initiate a warm reset. Reset must be syn-
chronously de-asserted with SysClock.
ModeClock
Output
Boot Mode Clock.
Serial boot-mode data clock output at the system clock frequency divided by two hundred and
fifty six.
ModeIn
Input
Input
Boot Mode Data In.
Serial boot-mode data input.
Endian mode select.
BigEndian
Allows the system to change the processor addressing mode without rewriting the mode ROM.
If endi anness is to be specified by using the BigEndian pin, program mode ROM bit 8 to 0; if
endianness is to be specified by the mode ROM, ground the BigEndian pin.
Secondary cache interface:
ScCLR*
Output
Output
Output
Input
Secondary Cache Block Clear.
Clears all valid bits in those Tag RAM’s which support this function.
Secondary Cache Write Enable.
ScCWE*(1:0)
ScDCE*(1:0)
ScDOE*
Asserted during writes to the secondary cache
Data RAM Chip Enable.
Chip Enable for Secondary Cache Data RAM
Data RAM Output Enable.
Asserted by the external agent to enable data onto the SysAD bus
Data RAM Output Enable.
ScLine (15:0)
Output
Cache line index for secondary cache
Table 4: RC5000 Signal Names and Descriptions (Page 2 of 3)
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
ScMATCH
Input
Secondary cache Tag Match.
Asserted by Tag RAM on Secondary cache tag match
Secondary cache Tag RAM Chip Enable.
ScTCE*
Output
Output
Output
Chip enable for secondary cache tag RAM.
Secondary cache Tag RAM Data Enable.
ScTDE*
Data Enable for Secondary Cache Tag RAM.
Secondary cache Tag RAM Output Enable.
Tag RAM Output enable for Secondary Cache Tag RAM’s
ScTOE*
ScWord (1:0)
ScValid
Input/Output Secondary cache Word Index.
Determines correct double-word of Secondary cache Index
Input/Output Secondary cache Valid.
Always driven by the CPU except during a cache probe operation, when it is driven by the tag
RAM.
Table 4: RC5000 Signal Names and Descriptions (Page 3 of 3)
Absolute maximum ratings
Symbol
VTERM
TC
Rating
Commercial (3.3V±5%)
–0.5(2) to +4.6
0 to +85
Unit
V
Terminal Voltage with respect to GND
Operating Temperature (case)
Case Temperature Under Bias
Storage Temperature
DC Input Current
°C
°C
°C
mA
mA
TBIAS
TSTG
IIN
–55 to +125
–55 to +125
20(3)
IOUT
DC Output Current
50(4)
NOTES:
1Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.V
IN minimum = –2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.
3.When VIN < 0V or VIN > VCC.
4.Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
Recommended operation temperature and supply voltage
RV5000
Grade
Temperature
GND
VCC
Commercial
0°C to +85°C (Case)
0V
3.3V±5%
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
AC electrical characteristics
(VCC= 3.3V± 5%; Tcase = 0°C to +85°C )
Clock Parameters—RC50001
180MHz
200MHz
250MHz
267 MHz
300 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Parameter
Symbol
Units
Pipeline Clock
Frequency
PCLk
100
180
100
200
100
250
100
267
100
300
SysClock HIGH
tSCHIGH
tSCLOW
—
3
—
3
—
—
100
30
2
3
—
—
125
30
2
3
—
—
125
20
2
3
—
—
125
20
2
ns
SysClock LOW
3
—
3
3
3
3
ns
SysClock Frequency
SysClock Period
SysClock Rise Time
SysClock Fall Time
ModeClock Period
33
11.1
—
—
—
90
30
2.5
2.5
33
10
—
—
—
33
8
33
8
50
8
MHz
ns
tSCP
tSCRise
tSCFall
—
—
—
—
—
—
—
—
—
ns
2
2
2
2
ns
tMo-
256
256
256
256
256
ns
tSCP
tSCP
tSCP
tSCP
tSCP
deCKP
Capacitive load deration—RC5000
180MHz
Symbol Test Conditions Min Max
200MHz
250MHz
267MHz
300MHz
Parameter
Load Derate CLD
Min
Max
Min
Max
Min
Max
Min
Max
Units
—
—
2
—
2
—
2
—
2
—
2
ns/25pF
1. Boot Mode Bits 20, 33 and 37 must be set to “1” for all frequencies
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
System interface parameters—RC5000
180 MHz
pipeline / 90
MHz Bus
200 MHz
pipeline /
100MHz Bus
Frequency
250MHz
pipeline /
125 MHz Bus
Frequency
267Mhz
Pipeline /
89MHz Bus
Frequency
300Mhz
pipeline /
100MHz Bus
Frequency
Parameter
Symbol
Test Conditions
Frequency
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max Units
Data Output
tDM= Min
tDO = Max (fastest)
mode14..13 = 10
1.5*
7
1.5
5
1.5*
4.7
1.0
4.7
1.0
4.7
ns
ns
ns
mode14..13 = 01
(slowest)
1.5*
1.0
11
—
1.5
1.0
11
—
1.5
1.0
7
—
7
—
7
Data Output
Hold
tDOH*
mode14..13 = 10
(fastest)
—
1.0
—
1.0
—
tDS
tDH
trise = 3ns
tfall = 3ns
1.5
0.5
—
—
1.5
0.5
—
—
1.5
0.5
—
—
1.5
0.5
—
—
1.5
0.5
—
—
ns
ns
Data Input
*Guaranteed by design
50 pf loading on external output signals
Boot time interface parameters—RC5000
180MHz / 90 200MHz / 100 250MHz / 125 267 MHz / 300 MHz / 100
Units
Sym Test
bol Conditions
MHz
MHz
MHz
89MHz
MHz
Parameter
Conditions
Min Max Min Max Min Max Min Max Min Max
Mode Data Setup tDS
Mode Data Hold tDH
—
—
4
0
—
—
4
0
—
—
4
0
—
—
4
0
—
—
4
0
—
—
ns
ns
Master Clock Cycle
Master Clock Cycle
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
DC electrical characteristics
(Vcc = 3.3V± 5%; Tcase = 0°C to +85°C)
180MHz
Min Max
200MHz
Min Max
250MHZ
Min Max
267MHz
Min
300MHz
Min
Max
0.1V
Max
0.1V
VCC - 0.1V —
Parameter
VOL
Conditions
—
0.1V
—
—
0.1V
—
—
0.1V
—
—
—
|IOUT|= 20uA
VOH
VCC
- 0.1V
—
VCC
- 0.1V
—
VCC
- 0.1V
—
VCC - 0.1V
—
VOL
VOH
VIL
0.4V
—
0.4V
—
0.4V
—
—
0.4V
—
—
0.4V
|IOUT|= 4mA
2.4V
–0.5V
2.4V
2.4V
2.4V
2.4V
—
0.2VCC –0.5V
0.2VCC –0.5V
0.2VCC –0.5V
0.2VCC
–0.5V
0.7VCC
0.2VCC
—
—
VIH
0.7VCC VCC +
0.5V
0.7VCC VCC + 0.7VCC VCC +
0.7VCC
VCC +
0.5V
VCC +
0.5V
0.5V
0.5V
IIN
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
0 £ VIN £ VCC
CIN
—
—
CIO
Cclk
I/OLEAK
Input/Output
Leakage
Power consumption—RC5000
180MHz
200MHz
250MHz
Max
267MHz
Max
300MHz
Parameter
Max
Max
Max
300/100MHz
130mA
3500
Conditions
System Condition
180/45MHz
120mA
200/50MHz
120mA
250/62.5MHz 267/89MHz
—
Icc
Standby
Active
120mA
130mA
3000
CL = 50 pF
CL = 50pF
1100mA
1300mA
1800mA
Pipelined writes or write re-
issue
Tc = 25oC
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79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
Physical specifications
The RC5000 is available in two packages, the 223-pin CPGA and the 272-ball SBGA. The 223-pin CPGA package is shown in Figure 2
and Table 3; information on the SBGA package is shown in Figure 3 and Table 4.
V
U
T
R
P
N
M
L
K
223-Pin CPGA
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Figure 2 RC5000 223-pin CPGA Pin Orientation (Bottom View)
12 of 16
79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
223-Pin CPGA Pinout
Pin # Function Pin
Function Pin Function
Pin
Function Pin Function Pin
Function
A2
Vcc
C5
SysADC[6]
SysAD[16]
SysAD[50]
SysAD[22]
SysAD[24]
SysAD[28]
SysAD[62]
SysAD[44]
SysAD[10]
SysAD[38]
SysAD[4]
SysAD[34]
SysAD[2]
Vss
E18
F1
Vcc
K17
VssP
R6
SysAD[51]
SysAD[55]
SysAD[27]
SysAD[31]
SysAD[43]
SysAD[39]
SysAD[35]
SysAD[1]
ScWord[1]
ScLine[0]
ScLine[3]
ScLine[6]
Vss
U9
SysAD[63]
SysAD[13]
SysAD[11]
SysAD[9]
SysAD[37]
SysAD[3]
ScWord[0]
Vcc
A3
Vss
C6
Vcc
K18
L1
Vss
R7
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
A4
Vcc
C7
F2
Reserved
ScValid
INT[1]*
ScDCE[0]*
ScCWE[0]*
ScTDE*
Vss
Vss
R8
A5
Vss
C8
F3
L2
SysCmd[8]
SysCmd[7]
SysCmd[5]
ScLine[12]
ScLine[14]
ScLine[15]
Vcc
R9
A6
Vss
C9
F4
L3
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
A7
Vcc
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
F15
F16
F17
F18
G1
L4
A8
Vss
L15
L16
L17
L18
M1
M2
M3
M4
M15
M16
M17
M18
N1
A9
Vcc
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
Vss
Vss
Vcc
Vss
Vss
Vss
G2
Reserved
Reserved
Reserved
ScCLR*
ScTCE*
ModeIn
Vcc
Vcc
Vss
Vcc
G3
SysCmd[6]
SysCmd[4]
SysCmd[1]
ScLine[8]
ScLine[10]
ScLine[13]
Vss
V2
Vss
Vss
G4
V3
Vcc
Vss
G15
G16
G17
G18
H1
Vss
V4
Vss
Vcc
Vss
T2
SysAD[15]
SysAD[47]
SysAD[17]
SysAD[19]
SysAD[23]
SysAD[57]
SysAD[29]
Vcc
V5
Vss
Vss
D2I
D3
INT3*
T3
V6
Vcc
Vss
INT5*
T4
V7
Vss
Vss
D4
Release*
Vcc
Vcc
T5
V8
Vcc
B2
Vss
D5
H2
Reserved
Reserved
Reserved
VccOK
ModeClock
SysClock
Vss
Vss
T6
V9
Vss
B3
Vcc
D6
SysADC[2]
SysAD[48]
SysAD[52]
SysAD[56]
SysAD[60]
SysAD[14]
SysAD[42]
SysAD[8]
SysAD[36]
ColdReset*
SysAD[0]
ScTOE*
H3
N2
SysCmd[3]
SysCmd[2]
SysADC[7]
ScLine[5]
ScLine[7]
ScLine[11]
Vcc
T7
V10
V11
V12
V13
V14
V15
V16
V17
V18
Vcc
B4
SysADC[4]
SysADC[0]
SysAD[18
SysAD[20]
SysAD[54]
SysAD[26]
0SysAD[58]
SysAD[30]
SysAD[46]
SysAD[12]
SysAD[40]
SysAD[6]
Vss
D7
H4
N3
T8
Vss
B5
D8
H15
H16
H17
H18
J1
N4
T9
Vcc
B6]
B7]
B8
D9
N15
N16
N17
N18
P1
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
SysAD[45]
SysAD[41]
SysAD[7]
SysAD[5]
SysAD[33]
Reset*
Vss
D10
D11
D12S
D13
D14
D15
D16
D17
D18
E1
Vcc
Vss
B9
Vss
Vss
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
J2
WrRdy*
ValidIn*
ExtReq*
JTDO
Vcc
Vcc
J3
P2
SysCmd[0]
SysCmdP
SysADC[1]
ScLine[2]
ScLine[4]
ScLine[9]
Vss
Vss
J4
P3
ScLine[1]
Vcc
J15
J16
J17
J18
K1
P4
JTDI
P15
P16
P17
P18
R1
Vcc
Vcc
JTCK
Vcc
Vss
Vcc
U2
Vcc
Vcc
E2
INT[0]*
Vcc
U3
Vss
Vcc
E3
INT[2]*
K2
ScMatch
RdRdy*
cDOE*
JTMS
Vcc
U4
SysAD[21]
SysAD[53]
SysAD[25]
SysAD[59]
SysAD[61]
Vcc
E4
NT[4]*
K3
R2
SysADC[5]
SysADC[3]
BigEndian
SysAD[49]
U5
C2
Vcc
E15
E16
SysAD[32]
ScDCE[1]*
K4S
K15
R3
U6
C3
ValidOut*
NMI*
R4
U7
C4
E17
ScCWE[1]* K16
VccP
R5
U8
13 of 16
79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
272-Ball SBGA package
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
272-Ball SBGA
M
N
P
R
T
U
V
W
Y
AA
Figure 3 Ball Grid Array Package (Bottom View)
14 of 16
79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
272-Ball SBGA Pinout
Pkg Pin Function Pkg Pin
Function
SysAD0
ScTOE*
ScCLR*
ScTDE*
ModeClock
JTDI
Pkg Pin Function Pkg Pin Function
Pkg Pin
P21
R1
Function
SysAD55
Vss
Pkg Pin
W1
Function
Vss
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
A1
Vss
Vcc
B5
B6
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
E1
Vss
Vcc
J2
J3
SysAD46
SysAD14
Vss
W2
Vcc
Vss
B7
Vccp
J4
R2
SysAD18
SysAD48
Vcc
W3
Vcc
ValidOut*
Vss
B8
Vcc
J18
J19
J20
J21
K1
Vss
R3
W4
Vcc
B9
Vss
SysAD9
SysAD41
Vss
R4
W5
Int*5
Int*0
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
C1
Vcc
R18
R19
R20
R21
T1
Vcc
W6
Int*4
Vss
JTCK
Vcc
SysAD53
SysAD23
Vss
W7
Int*1
Reserved
Vss
N/C
Vss
SysAD60
SysAD30
SysAD62
Vcc
W8
Reserved
Reserved
Reserved
ValidIn*
ScDOE*
SysCmd7
SysCmd4
SysCmd1
SysADC7
SysADC5
SysAD47
BigEndian
Vcc
ScLine14
ScLine10
ScLine9
ScLine6
ScLine3
ScLine1
Vcc
Vcc
K2
W9
WrRdy*
Vss
Vss
K3
SysAD16
SysADC0
SysADC2
Vss
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
Y1
Vcc
K4
T2
ScMatch
Vss
Vcc
K18
K19
K20
K21
L1
Vcc
T3
Vcc
SysAD11
SysAD43
SysAD13
Vss
T4
SysCmd6
Vss
Vss
T18
T19
T20
T21
U1
Vss
E2
SysAD36
SysAD4
Vcc
SysAD19
SysAD51
SysAD21
Vss
SysCmd2
Vss
Vcc
E3
Vcc
E4
L2
SysAD58
SysAD28
Vcc
SysADC3
Vss
Vss
E18
E19
E20
E21
F1
Vcc
L3
C2
Vcc
ScWord1
ScWord0
Vss
L4
U2
SysADC4
SysADC6
Vcc
Vcc
C3
ColdReset*
SysAD34
ScDCE*1
ScDCE*0
ScCWE*0
ScTCE*
ModeIn
JTDO
L18
L19
L20
L21
M1
M2
M3
M4
M18
M19
M20
M21
N1
Vcc
U3
Vss
C4
SysAD45
SysAD63
Vss
U4
Vss
Vss
C5
SysAD8
SysAD38
SysAD6
Vss
U18
U19
U20
U21
V1
Vcc
Vcc
A2
Vcc
C6
F2
SysAD17
SysAD49
Vss
Y2
Vcc
A3
Vss
C7
F3
SysAD26
SysAD56
SysAD24
Vcc
Y3
Vcc
A4
SysAD32
Vss
C8
F4
Y4
Release*
Int*3
A5
C9
F18
F19
F20
F21
G1
Vss
Vcc
Y5
A6
ScCWE*1
Vss
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
D1
SysAD1
SysAD33
SysAD3
Vss
V2
Vcc
Y6
Int*2
A7
Vssp
Vcc
V3
Vcc
Y7
ScValid
Reserved
Reserved
Reserved
ExtRqst*
RdRdy*
SysCmd8
SysCmd5
SysCmd3
SysCmd0
SysCmdP
SysADC1
SysAD15
A8
VCCOK
Vss
JTMS
SysAD29
SysAd61
SysAD31
Vss
V4
Vss
Y8
A9
ScLine13
ScLine11
ScLine8
ScLine5
ScLine4
ScLine0
Reset*
Vcc
V5
NMI*
Y9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
MasterClk
Vss
G2
SysAD10
SysAD40
Vcc
V6
Vss
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
G3
V7
Vcc
ScLine15
Vss
G4
N2
SysAD54
SysAD22
Vss
V8
Vcc
G18
G19
G20
G21
H1
Vcc
N3
V9
Vss
ScLine12
Vss
SysAD35
SysAD5
Vss
N4
V10
V11
V12
V13
V14
V15
Vcc
N18
N19
N20
N21
P1
Vss
Vcc
ScLine7
Vss
SysAD27
SysAD59
Vss
Vcc
Vss
SysAD42
SysAD44
SysAD12
Vss
ScLine2
Vss
Vcc
H2
Vcc
D2
Vcc
H3
SysAD50
Vcc
15 of 16
79RC5000
MULTI-ISSUE 64-BIT MICROPROCESSOR
A20
A21
B1
Vcc
D3
D4
D5
D6
D7
D8
Vcc
Vss
Vcc
Vss
Vcc
Vcc
H4
H18
H19
H20
H21
J1
Vcc
Vcc
P2
P3
SysAD52
SysAD20
Vcc
V16
V17
V18
V19
V20
V21
Vss
Vcc
Vss
Vcc
Vcc
Vcc
Y20
Y21
Vcc
Vcc
Vss
Vcc
SysAD7
SysAD39
SysAD37
Vss
P4
B2
Vcc
P18
P19
P20
Vcc
B3
Vcc
SysAD25
SysAD57
B4
SysAD2
Table 5: 272-Ball SBGA Pinout
Ordering information
IDT79
YY
XXXX
999
A
A
Operating
Voltage
Device
Type
Speed
Package
Temp range/
Process
Blank Commercial
(0°C to +85°C Case)
G
223-ball CPGA
BS
272-ball SBGA
180 MHz Pipeline
180
200 MHz Pipeline
250 MHz Pipeline
267 MHz Pipeline
300 MHz Pipeline
200
250
267
300
5000 Multi-Issue
64-bit Microprocessor
RV
3.3+/-5%
Valid Combinations
IDT79RV5000 - 180, 200MHz
G
CPGA package
SBGA package
IDT79RV5000 - 180, 200, 250 ,267, 300MHz BS
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet, to improve design or performance and to supply the best product possible
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 Fax (408) 492-8674
16 of 16
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