IDT82V3203BNLG [IDT]
Telecom Circuit, 1-Func, CMOS, PQCC68, GREEN, PLASTIC, VFQFPN-68;
| 型号： | IDT82V3203BNLG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Telecom Circuit, 1-Func, CMOS, PQCC68, GREEN, PLASTIC, VFQFPN-68 电信 电信集成电路 |
| 文件： | 总118页 (文件大小：1288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EBU WAN PLL
IDT82V3203B
Version -
August 21, 2007
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2006 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
FEATURES.............................................................................................................................................................................. 7
HIGHLIGHTS.................................................................................................................................................................................................... 7
MAIN FEATURES ............................................................................................................................................................................................ 7
OTHER FEATURES......................................................................................................................................................................................... 7
APPLICATIONS....................................................................................................................................................................... 7
DESCRIPTION......................................................................................................................................................................... 8
FUNCTIONAL BLOCK DIAGRAM.......................................................................................................................................... 9
1 PIN ASSIGNMENT ........................................................................................................................................................... 10
2 PIN DESCRIPTION .......................................................................................................................................................... 11
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 15
3.1 RESET ........................................................................................................................................................................................................... 15
3.2 MASTER CLOCK .......................................................................................................................................................................................... 15
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 16
3.3.1 Input Clocks .................................................................................................................................................................................... 16
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 16
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 17
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 19
3.5.1 Activity Monitoring ......................................................................................................................................................................... 19
3.5.2 Frequency Monitoring ................................................................................................................................................................... 20
3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 21
3.6.1 External Fast Selection .................................................................................................................................................................. 21
3.6.2 Forced Selection ............................................................................................................................................................................ 22
3.6.3 Automatic Selection ....................................................................................................................................................................... 22
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 23
3.7.1 DPLL Locking Detection ................................................................................................................................................................ 23
3.7.1.1 Fast Loss .......................................................................................................................................................................... 23
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 23
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 23
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 23
3.7.2 Locking Status ............................................................................................................................................................................... 23
3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 23
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 25
3.8.1 Input Clock Validity ........................................................................................................................................................................ 25
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 25
3.8.2.1 Revertive Switch ............................................................................................................................................................... 25
3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 25
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 25
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 27
3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 29
3.10.1 Six Operating Modes ..................................................................................................................................................................... 29
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 29
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 29
3.10.1.3 Locked Mode .................................................................................................................................................................... 29
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 29
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 29
3.10.1.5 Holdover Mode ................................................................................................................................................................. 29
Table of Contents
3
August 21, 2007
IDT82V3203B
EBU WAN PLL
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 30
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 30
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 30
3.10.1.5.4 Manual ........................................................................................................................................................... 30
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 30
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 30
3.11 DPLL OUTPUT .............................................................................................................................................................................................. 32
3.11.1 PFD Output Limit ............................................................................................................................................................................ 32
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 32
3.11.3 PBO ................................................................................................................................................................................................. 32
3.11.4 Four Paths of T0 DPLL Outputs .................................................................................................................................................... 32
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 34
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 34
3.13.1 Output Clocks ................................................................................................................................................................................. 34
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 36
3.14 INTERRUPT SUMMARY ............................................................................................................................................................................... 38
3.15 T0 SUMMARY ............................................................................................................................................................................................... 38
3.16 LINE CARD APPLICATION .......................................................................................................................................................................... 39
4 I2C PROGRAMMING INTERFACE .................................................................................................................................. 40
4.1 FUNCTION DESCRIPTION ........................................................................................................................................................................... 40
4.1.1 Data Transfer Format ..................................................................................................................................................................... 41
4.1.1.1 Slave-receiver Mode (Write) ............................................................................................................................................. 41
4.1.1.2 Slave-transmitter Mode (Read) ........................................................................................................................................ 41
4.1.2 Address Assignment ..................................................................................................................................................................... 42
4.2 TIMING DEFINITION ..................................................................................................................................................................................... 42
5 JTAG ................................................................................................................................................................................ 43
6 PROGRAMMING INFORMATION .................................................................................................................................... 44
6.1 REGISTER MAP ............................................................................................................................................................................................ 44
6.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 49
6.2.1 Global Control Registers ............................................................................................................................................................... 49
6.2.2 Interrupt Registers ......................................................................................................................................................................... 56
6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 60
6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 68
6.2.5 T0 DPLL Input Clock Selection Registers .................................................................................................................................... 77
6.2.6 T0 DPLL State Machine Control Registers .................................................................................................................................. 80
6.2.7 T0 DPLL & T0/T4 APLL Configuration Registers ........................................................................................................................ 82
6.2.8 Output Configuration Registers .................................................................................................................................................... 93
6.2.9 PBO & Phase Offset Control Registers ........................................................................................................................................ 96
6.2.10 Synchronization Configuration Registers ................................................................................................................................... 97
7 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 99
7.1 ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 99
7.2 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 99
7.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 100
7.3.1 CMOS Input / Output Port ............................................................................................................................................................ 100
7.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 102
7.3.2.1 PECL Input / Output Port ................................................................................................................................................ 102
7.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 104
7.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 105
7.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 108
7.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 109
7.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 110
PACKAGE DIMENSIONS - 68-PIN NL ............................................................................................................................... 115
ORDERING INFORMATION................................................................................................................................................ 118
Table of Contents
4
August 21, 2007
List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 11
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 15
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 16
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 18
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 20
Table 6: Input Clock Selection ................................................................................................................................................................................... 21
Table 7: External Fast Selection ................................................................................................................................................................................ 21
Table 8: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 22
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 22
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 23
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 23
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 24
Table 13: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 26
Table 14: T0 DPLL Operating Mode Control ............................................................................................................................................................... 27
Table 15: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 28
Table 16: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 29
Table 17: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 30
Table 18: Holdover Frequency Offset Read ................................................................................................................................................................ 30
Table 19: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 31
Table 20: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 33
Table 21: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 34
Table 22: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs ..................................................................................................................... 34
Table 23: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 35
Table 24: Frame Sync Input Signal Selection .............................................................................................................................................................. 36
Table 25: Synchronization Control ............................................................................................................................................................................... 36
Table 26: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 37
Table 27: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 38
Table 28: Definition of S/Sr and P Conditions ............................................................................................................................................................. 40
Table 29: Timing Definition .......................................................................................................................................................................................... 42
Table 30: JTAG Timing Characteristics ....................................................................................................................................................................... 43
Table 31: Register List and Map .................................................................................................................................................................................. 44
Table 32: Absolute Maximum Rating ........................................................................................................................................................................... 99
Table 33: Recommended Operation Conditions .......................................................................................................................................................... 99
Table 34: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 100
Table 35: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 100
Table 36: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 100
Table 37: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 101
Table 38: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 103
Table 39: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 104
Table 40: Output Clock Jitter Generation .................................................................................................................................................................. 105
Table 41: Output Clock Phase Noise ......................................................................................................................................................................... 106
Table 42: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 106
Table 43: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 106
Table 44: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 106
Table 45: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 107
Table 46: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 107
Table 47: Input/Output Clock Timing ......................................................................................................................................................................... 109
Table 48: Output Clock Timing .................................................................................................................................................................................. 110
List of Tables
5
August 21, 2007
List of Figures
Figure 1. Functional Block Diagram .............................................................................................................................................................................. 9
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 10
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 17
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 19
Figure 5. External Fast Selection ................................................................................................................................................................................ 21
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 27
Figure 7. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 36
Figure 8. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 36
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing ............................................................................................................................................... 37
Figure 10. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 37
Figure 11. Line Card Application ................................................................................................................................................................................. 39
Figure 12. Data Transfer on the I2C-bus ..................................................................................................................................................................... 40
Figure 13. Slave-receiver Mode ................................................................................................................................................................................... 41
Figure 14. Slave-transmitter Mode .............................................................................................................................................................................. 41
Figure 15. Address Assignment ................................................................................................................................................................................... 42
Figure 16. Timing Definition of I2C-bus ....................................................................................................................................................................... 42
Figure 17. JTAG Interface Timing Diagram ................................................................................................................................................................. 43
Figure 18. Recommended PECL Input Port Line Termination .................................................................................................................................. 102
Figure 19. Recommended PECL Output Port Line Termination ................................................................................................................................ 102
Figure 20. Recommended LVDS Input Port Line Termination .................................................................................................................................. 104
Figure 21. Recommended LVDS Output Port Line Termination ................................................................................................................................ 104
Figure 22. Output Wander Generation ...................................................................................................................................................................... 108
Figure 23. Input / Output Clock Timing ...................................................................................................................................................................... 109
Figure 24. 68-Pin NL Package Dimensions (a) (in Millimeters) ................................................................................................................................. 115
Figure 25. 68-Pin NL Package Dimensions (b) (in Millimeters) ................................................................................................................................. 116
Figure 26. 68-Pin NL Package Dimensions (c) (in Millimeters) ................................................................................................................................. 117
List of Figures
6
August 21, 2007
EBU WAN PLL
IDT82V3203B
•
Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and
a 2 kHz and an 8 kHz frame sync output signals
Provides three input clocks whose frequency cover from 2 kHz to
622.08 MHz
FEATURES
HIGHLIGHTS
•
The first single PLL chip:
•
•
•
- Features 0.1 Hz to 560 Hz bandwidth
- Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
Option I) jitter generation requirements
- Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
Provides two output clocks whose frequency cover from 1 Hz to
622.08 MHz
- Provides clocks for DSL access concentrators (DSLAM), espe-
cially for Japan TCM-ISDN network timing based ADSL equip-
ments
•
•
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports CMOS input/output and PECL/LVDS input/output technol-
ogies
•
•
•
Supports master clock calibration
Supports Line Card application
Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812,
ITU-T G.813 and ITU-T G.783 criteria
MAIN FEATURES
•
•
•
Provides an integrated single-chip solution for Synchronous Equip-
ment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are Free-
Run, Locked and Holdover
OTHER FEATURES
2
•
•
•
•
I C programming interface
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
68-pin VFQFPN package, Green package options available
•
Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11
steps) and damping factor (1.2 to 20 in 5 steps)
-5
-8
APPLICATIONS
•
•
•
Supports 1.1X10 ppm absolute holdover accuracy and 4.4X10
ppm instantaneous holdover accuracy
•
•
•
•
•
•
•
•
•
•
BITS / SSU
SMC / SEC (SONET / SDH)
Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
DWDM cross-connect and transmission equipments
Central Office Timing Source and Distribution
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
IP and ATM core switches and access equipments
Cellular and WLL base-station node clocks
Broadband and multi-service access equipments
Any other telecom equipments that need synchronous equipment
system timing
•
•
•
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock fail-
ure
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
7
August 21, 2007
2006 Integrated Device Technology, Inc.
DSC-6983/-
IDT82V3203B
EBU WAN PLL
performance without being affected by operating conditions or silicon
process variations.
DESCRIPTION
The IDT82V3203B is an integrated, single-chip solution for the Syn-
chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.1 Hz to 560
Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-
tings cover all SONET / SDH clock synchronization requirements.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
A high stable input is required for the master clock in different appli-
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
An input clock is automatically or manually selected for DPLL lock-
ing. The DPLL supports three primary operating modes: Free-Run,
Locked and Holdover. In Free-Run mode, the DPLL refers to the master
clock. In Locked mode, the DPLL locks to the selected input clock. In
Holdover mode, the DPLL resorts to the frequency data acquired in
Locked mode. Whatever the operating mode is, the DPLL gives a stable
2
All the read/write registers are accessed only through an I C pro-
gramming interface.
The device can be used typically in Line Card application.
Description
8
August 21, 2007
IDT82V3203B
EBU WAN PLL
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
Functional Block Diagram
9
August 21, 2007
IDT82V3203B
EBU WAN PLL
1
PIN ASSIGNMENT
AGND
IC1
1
2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
RST
SCL
AGND1
VDDA1
NC
3
AD2
4
AD1
5
AD0
INT_REQ
OSCI
6
IC6
7
NC
DGND1
VDDD1
VDDD3
DGND3
DGND2
VDDD2
FF_SRCSW
VDDA2
AGND2
IC2
8
IC5
9
TMS
DGND5
VDDD5
VDDD5
IDT82V3203B
10
11
12
13
14
15
16
17
TRST
VDDD5
EX_SYNC3
IN3_CMOS
EX_SYNC2
Figure 2. Pin Assignment (Top View)
Pin Assignment
10
August 21, 2007
IDT82V3203B
EBU WAN PLL
2
PIN DESCRIPTION
Table 1: Pin Description
Description 1
Name
Pin No.
I/O
Type
Global Control Signal
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
OSCI
7
I
CMOS
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) . The
2
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
I
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
FF_SRCSW
14
CMOS
pull-down
After reset, this pin selects an input clock for the T0 DPLL if the External Fast selection is
enabled:
High: IN1_DIFF is selected.
Low: IN2_DIFF is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
I
SONET/SDH
68
51
CMOS
CMOS
pull-down
RST: Reset
I
RST
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
pull-up
Frame Synchronization Input Signal
EX_SYNC1: External Sync Input 1
I
EX_SYNC1
EX_SYNC2
EX_SYNC3
30
35
37
CMOS
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
pull-down
I
EX_SYNC2: External Sync Input 2
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
CMOS
CMOS
pull-down
I
EX_SYNC3: External Sync Input 3
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
pull-down
Input Clock
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN1_POS8
IN1_NEG
24
25
I
I
PECL/LVDS
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN2_POS9
IN2_NEG
26
27
PECL/LVDS
CMOS
IN3_CMOS: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
I
IN3_CMOS
36
18
pull-down
Output Frame Synchronization Signal
FRSYNC_8K: 8 kHz Frame Sync Output
CMOS
FRSYNC_8K
O
An 8 kHz signal is output on this pin.
Pin Description
11
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 1: Pin Description (Continued)
Description 1
MFRSYNC_2K: 2 kHz Multiframe Sync Output
Name
Pin No.
I/O
Type
MFRSYNC_2K
19
O
CMOS
A 2 kHz signal is output on this pin.
Output Clock
OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT1_POS
OUT1_NEG
20
21
O
O
PECL/LVDS
CMOS
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT2
59
I2C Programming Interface
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
INT_REQ
6
O
I
CMOS
CMOS
AD0
AD1
AD2
47
48
49
AD[2:0]: Address Input 2 to 0
The address is input on these pins.
SCL: Serial Clock Line
The serial clock is input on this pin. The clock is 400 kbit/s in Fast-mode and 3.4 Mbit/s in
High-speed mode.
SCL
SDA
50
55
I
CMOS
CMOS
SDA: Serial Data Input/Output
This pin is used as the input/output for the serial data.
I/O
JTAG (per IEEE 1149.1)
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
I
TRST
39
43
CMOS
CMOS
pull-down
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
I
TMS
pull-up
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
I
TCK
TDI
52
54
53
CMOS
CMOS
CMOS
pull-down
I
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
pull-up
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.
TDO
O
Pin Description
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Table 1: Pin Description (Continued)
Description 1
Name
Pin No.
I/O
Type
Power & Ground
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
9
13
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.
10
Power
-
34
38, 40, 41
VDDD6
VDDA1
57
4
VDDAn: 3.3 V Analog Power Supply
Each VDDAn should be paralleled with ground through a 0.1 µF capacitor.
VDDA2
15
Power
Power
-
-
VDDA3
VDD_DIFF
DGND1
60
23
8
VDD_DIFF: 3.3 V Power Supply for OUT1
DGNDn: Digital Ground
DGND2
DGND3
DGND4
DGND5
12
11
33
42
Ground
-
DGND6
AGND1
56
3
AGNDn: Analog Ground
AGND2
16
Ground
-
AGND3
GND_DIFF
AGND
61
22
1
Ground
Ground
-
-
GND_DIFF: Ground for OUT1
AGND: Analog Ground
Pin Description
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Table 1: Pin Description (Continued)
Description 1
Name
Pin No.
I/O
Type
Others
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
2
IC: Internal Connected
Internal Use. These pins should be left open for normal operation.
17
32
31
44
46
58
63
64
65
66
67
-
-
NC
5, 28, 29, 45, 62
-
-
NC: Not Connected
Note:
1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care.
2. The contents in the brackets indicate the position of the register bit/bits.
3. N x 8 kHz: 1 < N < 19440.
4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64.
5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96.
6. N x 13.0 MHz: N = 1, 2, 4.
7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40.
8. IN1_POS and IN1_NEG equals to IN1_DIFF.
9. IN2_POS and IN2_NEG equals to IN2_DIFF.
Pin Description
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3.2
MASTER CLOCK
3
FUNCTIONAL DESCRIPTION
RESET
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
3.1
The reset operation resets all registers and state machines to their
default value or status.
After power on, the device must be reset for normal operation.
In fact, an offset from the nominal frequency may input on the OSCI
pin. This offset can be compensated by setting the
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
For a complete reset, the RST pin must be asserted low for at least
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
The performance of the master clock should meet GR-1244-CORE,
GR-253-CORE, ITU-T G.812 and G.813 criteria.
Table 2: Related Bit / Register in Chapter 3.2
Bit
Register
Address (Hex)
NOMINAL_FREQ_VALUE[23:0]
OSC_EDGE
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
06, 05, 04
0A
Functional Description
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bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3
INPUT CLOCKS & FRAME SYNC SIGNALS
Altogether three clocks and three frame sync signals are input to the
device.
3.3.2
FRAME SYNC INPUT SIGNALS
3.3.1
INPUT CLOCKS
Three 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the
EX_SYNC1, EX_SYNC2 and EX_SYNC3 pins respectively. They are
CMOS inputs. The input frequency should match the setting in the
SYNC_FREQ[1:0] bits. The frame sync signals are only valid for the OC-
n clock (6.48 MHz, 19.44 MHz, 38.88 MHz and 77.76 MHz) input.
The device provides a CMOS input clock port: IN3_CMOS, and two
PECL/LVDS input clock ports: IN1_DIFF and IN2_DIFF. IN1_DIFF and
IN2_DIFF automatically detect whether the signal is PECL or LVDS
(IN1_POS and IN1_NEG equals to IN1_DIFF, IN2_POS and IN2_NEG
equals to IN2_DIFF).
Only one of the three frame sync input signals is used for frame sync
output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC
Output Signals for details.
According to the input clock source, the following clock sources are
supported:
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
Table 3: Related Bit / Register in Chapter 3.3
Bit
Register
Address (Hex)
The clock sources can be from T1, T2 or T3.
IN_SONET_SDH
SYNC_FREQ[1:0]
INPUT_MODE_CNFG
09
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
Functional Description
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Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
The DivN Divider can only divide the input clock whose frequency is
lower than (<) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN1_DIFF and IN2_DIFF), a DivN Divider and a Lock 8k
Divider, as shown in Figure 3.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
The HF Divider, which is only available for IN1_DIFF and IN2_DIFF,
should be used when the input clock is higher than (>) 155.52 MHz. The
input clock can be divided by 4, 5 or can bypass the HF Divider, as
determined by the IN1_DIFF_DIV[1:0]/IN2_DIFF_DIV[1:0] bits corre-
spondingly.
The input clock on the IN2_DIFF pin is 622.08 MHz; the DPLL
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_DIFF to ‘0010’. Do the following step by step to divide the
input clock:
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN2_DIFF_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN2_DIFF_CNFG to ‘1’ and
the LOCK_8K bit in Register IN2_DIFF_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
When the DivN Divider is used, the division factor setting should
observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Pre-Divider
IN1_DIFF_DIV[1:0] bits / IN2_DIFF_DIV[1:0] bits
DIRECT_DIV bit
LOCK_8K bit
HF Divider
input clock
(for IN1_DIFF &
IN2_DIFF only)
DivN Divider
DPLL required clock
Lock 8k Divider
Figure 3. Pre-Divider for An Input Clock
Functional Description
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EBU WAN PLL
Table 4: Related Bit / Register in Chapter 3.4
Bit
Register
Address (Hex)
IN1_DIFF_DIV[1:0]
IN2_DIFF_DIV[1:0]
IN_FREQ[3:0]
IN1_DIFF_IN2_DIFF_HF_DIV_CNFG
18
DIRECT_DIV
IN1_DIFF_CNFG, IN2_DIFF_CNFG, IN3_CMOS_CNFG
19, 1A, 1D
LOCK_8K
IN_2K_4K_8K_INV
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
FR_MFR_SYNC_CNFG
PRE_DIV_CH_CNFG
74
23
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
25, 24
Functional Description
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IDT82V3203B
EBU WAN PLL
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
3.5
INPUT CLOCK QUALITY MONITORING
The qualities of all the input clocks are always monitored in the fol-
lowing aspects:
• Activity
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
• Frequency
The qualified clocks are available for T0 DPLL selection. The T0
selected input clock has to be monitored further. Refer to Chapter 3.7
Selected Input Clock Monitoring for details.
3.5.1
ACTIVITY MONITORING
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 4.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
The no-activity alarm status of the input clock is indicated by the
INn_CMOS_NO_ACTIVITY_ALARM
bit
(n
=
3)
/
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2) bit.
The input clock with a no-activity alarm is disqualified for clock selec-
tion for T0 DPLL.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
clock signal with events
clock signal with no event
Input Clock
Decay
Rate
Bucket Size
Upper Threshold
Leaky Bucket Accumulator
No-activity Alarm Indication
Lower Threshold
0
Figure 4. Input Clock Activity Monitoring
Functional Description
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EBU WAN PLL
3.5.2
FREQUENCY MONITORING
The input clock with a frequency hard alarm is disqualified for clock
selection for T0 DPLL.
Frequency is monitored by comparing the input clock with a refer-
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0 DPLL.
The input clock is qualified if any edge drifts inside ±5%. This function is
supported only when the IN_NOISE_WINDOW bit is ‘1’.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
Input Clock Frequency (ppm)
FREQ_MON_FACTOR[3:0]
= IN_FREQ_VALUE[7:0] X
status
of
the
input
clock
is
bit
indicated
(n
by
3)
the
/
INn_CMOS_FREQ_HARD_ALARM
=
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
INn_DIFF_FREQ_HARD_ALARM bit (n = 1 or 2). When the
FREQ_MON_HARD_EN bit is ‘0’, no frequency hard alarm is raised
even if the input clock is above the frequency hard alarm threshold.
Table 5: Related Bit / Register in Chapter 3.5
Bit
Register
Address (Hex)
BUCKET_SIZE_n_DATA[7:0] (3 ≥ n ≥ 0)
UPPER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
LOWER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
DECAY_RATE_n_DATA[1:0] (3 ≥ n ≥ 0)
BUCKET_SEL[1:0]
BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG
UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG
LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG
DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG
33, 37, 3B, 3F
31, 35, 39, 3D
32, 36, 3A, 3E
34, 38, 3C, 40
19, 1A, 1D
IN1_DIFF_CNFG, IN2_DIFF_CNFG, IN3_CMOS_CNFG
INn_CMOS_NO_ACTIVITY_ALARM (n = 3)
INn_CMOS_FREQ_HARD_ALARM (n = 3)
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
FREQ_MON_CLK
IN1_IN2_DIFF_STS, IN3_CMOS_STS
IN1_IN2_DIFF_STS
44, 45
45
MON_SW_PBO_CNFG
0B
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
ALL_FREQ_MON_THRESHOLD_CNFG
FREQ_MON_FACTOR_CNFG
PHASE_MON_PBO_CNFG
IN_FREQ_READ_CH_CNFG
IN_FREQ_READ_STS
2F
2E
78
41
42
IN_NOISE_WINDOW
IN_FREQ_READ_CH[3:0]
IN_FREQ_VALUE[7:0]
Functional Description
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IDT82V3203B
EBU WAN PLL
monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not
affect input clock selection.
3.6
DPLL INPUT CLOCK SELECTION
The EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit dur-
ing reset, refer to Chapter 2 Pin Description), the
input clock selection, as shown in Table 6:
Table 6: Input Clock Selection
Control Bits
IN1_DIFF_SEL_PRIORITY[3:0]
bits
and
the
IN2_DIFF_SEL_PRIORITY[3:0] bits, as shown in Figure 5 and Table 7:
Input Clock Selection
EXT_SW
T0_INPUT_SEL[3:0]
1
don’t-care
other than 0000
0000
External Fast selection
Forced selection
IN1_DIFF_SEL_PRIORITY[3:0] bits
0
Automatic selection
FF_SRCSW pin
IN1_DIFF
External Fast selection is done between IN1_DIFF and IN2_DIFF.
Forced selection is done by setting the related registers.
attempted to be
locked in T0 DPLL
Automatic selection is done based on the results of input clocks qual-
ity monitoring and the related registers configuration.
IN2_DIFF
The selected input clock is attempted to be locked by T0 DPLL.
3.6.1
EXTERNAL FAST SELECTION
IN2_DIFF_SEL_PRIORITY[3:0] bits
In External Fast selection, only IN1_DIFF and IN2_DIFF are avail-
able for selection. Refer to Figure 5. The results of input clocks quality
Figure 5. External Fast Selection
Table 7: External Fast Selection
Control Pin & Bits
the Selected Input Clock
FF_SRCSW (after reset)
IN1_DIFF_SEL_PRIORITY[3:0]
IN2_DIFF_SEL_PRIORITY[3:0]
high
low
other than 0000
don’t-care
don’t-care
IN1_DIFF
IN2_DIFF
other than 0000
Functional Description
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IDT82V3203B
EBU WAN PLL
3.6.2
FORCED SELECTION
selected. The priority is configured by the corresponding
INn_CMOS_SEL_PRIORITY[3:0] bits (n = 3). If more than one qualified
input clock is available and has the same priority, the input clock with the
smallest ‘n’ is selected. See Table 8 for the ‘n’ assigned to the input
clock.
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring
(refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the
input clock selection.
Table 8: ‘n’ Assigned to the Input Clock
3.6.3
AUTOMATIC SELECTION
Input Clock
‘n’ Assigned to the Input Clock
In Automatic selection, the input clock selection is determined by its
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
In all the qualified input clocks, the one with the highest priority is
IN1_DIFF
IN2_DIFF
IN3_CMOS
2
4
5
Table 9: Related Bit / Register in Chapter 3.6
Bit
Register
Address (Hex)
EXT_SW
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
0B
50
2A
28
T0_INPUT_SEL[3:0]
INn_CMOS_SEL_PRIORITY[3:0] (n = 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
IN3_CMOS_SEL_PRIORITY_CNFG
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
Functional Description
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EBU WAN PLL
3.7.1.3
Fine Phase Loss
3.7
SELECTED INPUT CLOCK MONITORING
The T0 DPLL compares the selected input clock with the feedback
signal. If the phase-compared result exceeds the fine phase limit pro-
grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is trig-
gered. It is cleared once the phase-compared result is within the fine
phase limit.
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1
DPLL LOCKING DETECTION
The following events is always monitored:
• Fast Loss;
• Coarse Phase Loss;
• Fine Phase Loss;
The occurrence of the fine phase loss will result in T0 DPLL unlocked
if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
Hard Limit Exceeding
• Hard Limit Exceeding.
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0 DPLL locking status. The DPLL soft alarm is indi-
cated by the corresponding T0_DPLL_SOFT_FREQ_ALARM bit. The
occurrence of the DPLL hard alarm will result in T0 DPLL unlocked if the
FREQ_LIMT_PH_LOS bit is ‘1’.
3.7.1.1
Fast Loss
A fast loss is triggered when the selected input clock misses 2 con-
secutive clock cycles. It is cleared once an active clock edge is detected.
The occurrence of the fast loss will result in T0 DPLL unlocked if the
FAST_LOS_SW bit is ‘1’.
3.7.1.2
Coarse Phase Loss
The T0 DPLL compares the selected input clock with the feedback
signal. If the phase-compared result exceeds the coarse phase limit, a
coarse phase loss is triggered. It is cleared once the phase-compared
result is within the coarse phase limit.
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 10. When the selected input clock is of other frequencies but 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11.
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2
LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
• Fast Loss (the FAST_LOS_SW bit is ‘1’);
Table 10: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
• Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
MULTI_PH_8K_4K
WIDE_EN
Coarse Phase Limit
_2K_EN
0
don’t-care
±1 UI
±1 UI
0
1
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
Table 11: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
The DPLL locking status is indicated by the T0_DPLL_LOCK bit.
WIDE_EN
Coarse Phase Limit
3.7.3
PHASE LOCK ALARM
0
1
±1 UI
set by the PH_LOS_COARSE_LIMT[3:0] bits
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be cal-
culated as follows:
The occurrence of the coarse phase loss will result in T0 DPLL
unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding
INn_CMOS_PH_LOCK_ALARM
bit
(n
=
3)
/
INn_DIFF_PH_LOCK_ALARM bit (n = 1 or 2).
Functional Description
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IDT82V3203B
EBU WAN PLL
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
• Be cleared when a ‘1’ is written to the corresponding
INn_CMOS_PH_LOCK_ALARM
INn_DIFF_PH_LOCK_ALARM bit;
bit
/
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in second) which starts from when the
alarm is raised.
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
Table 12: Related Bit / Register in Chapter 3.7
Bit
Register
Address (Hex)
FAST_LOS_SW
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
WIDE_EN
PHASE_LOSS_FINE_LIMIT_CNFG
5B
5A
PHASE_LOSS_COARSE_LIMIT_CNFG
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
OPERATING_STS
52
65
DPLL_FREQ_SOFT_LIMT[6:0]
FREQ_LIMT_PH_LOS
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
DPLL_FREQ_HARD_LIMT[15:0]
67, 66
08
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
PHASE_ALARM_TIME_OUT_CNFG
INn_CMOS_PH_LOCK_ALARM (n = 3)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
PH_ALARM_TIMEOUT
IN3_CMOS_STS
IN1_IN2_DIFF_STS
INPUT_MODE_CNFG
47
45
09
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Conditions of the qualified input clocks available for T0 selection are
as the following:
3.8
SELECTED INPUT CLOCK SWITCH
If the input clock is selected by External Fast selection or by Forced
1
1
• Valid, i.e., the INn_CMOS / INn_DIFF bit is ‘1’;
• Priority enabled, i.e., the corresponding INn_CMOS_SEL
_PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not
‘0000’.
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection & Chapter 3.6.2 Forced Selection)
any time. In this case, whether the input clock is qualified for DPLL lock-
ing does not affect the clock switch.
The input clock is disqualified if any of the above conditions is not
satisfied.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
In summary, the selected input clock can be switched by:
• External Fast selection;
• Forced selection;
• Revertive switch;
3.8.1
INPUT CLOCK VALIDITY
For all the input clocks, the validity depends on the results of input
clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni-
toring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
• Non-Revertive switch.
3.8.2.1
Revertive Switch
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
• No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM /
INn_DIFF_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_CMOS_FREQ_HARD_
ALARM / INn_DIFF_FREQ_HARD_ALARM bit is ‘0’);
The selected input clock is switched if any of the following is satis-
fied:
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
• No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM /
INn_DIFF_PH_LOCK bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
• The selected input clock is disqualified;
• Another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the highest priority is selected by revertive
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smallest ‘n’ is selected. See
Table 8 for the ‘n’ assigned to each input clock.
3.8.2.2
Non-Revertive Switch
1
The validities of all the input clocks are indicated by the INn_CMOS
1
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected. See Table 8 for the ‘n’ assigned to
each input clock.
bit (n = 3) /INn_DIFF bit (n = 1 or 2). When the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), the
2
2
3
INn_CMOS / INn_DIFF bit will be set. If the INn_CMOS / INn_DIFF
3
bit is ‘1’, an interrupt will be generated.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the
1
2
T0_MAIN_REF_FAILED bit will be set. If the T0_MAIN_REF_FAILED
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.3
The
CURRENTLY_SELECTED_INPUT[3:0] bits.
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
selected input clock is indicated by the
The qualified input clocks with the three highest priorities are indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits, the
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] bits and the
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] bits respectively. If
more than one input clock has the same priority, the input clock with the
smallest ‘n’ is indicated by the HIGHEST_PRIORITY_VALIDATED[3:0]
bits. See Table 8 for the ‘n’ assigned to the input clock.
3.8.2
SELECTED INPUT CLOCK SWITCH
Revertive and Non-Revertive switches are supported, as selected by
the REVERTIVE_MODE bit.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
When the device is configured in Automatic selection and Revertive
switch is enabled, the input clock indicated by the
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
Functional Description
25
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IDT82V3203B
EBU WAN PLL
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
Table 13: Related Bit / Register in Chapter 3.8
Bit
Register
Address (Hex)
4A, 4B
INn_CMOS 1 (n = 3) / INn_DIFF 1 (n = 1 or 2)
INn_CMOS 2 (n = 3) / INn_DIFF 2 (n = 1 or 2)
INPUT_VALID1_STS, INPUT_VALID2_STS
INTERRUPTS1_STS, INTERRUPTS2_STS
0D, 0E
INn_CMOS 3 (n = 3) / INn_DIFF 3 (n = 1 or 2)
INn_CMOS_NO_ACTIVITY_ALARM (n = 3)
INn_CMOS_FREQ_HARD_ALARM (n = 3)
INn_CMOS_PH_LOCK_ALARM (n = 3)
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
IN_NOISE_WINDOW
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
10, 11
IN3_CMOS_STS
47
45
IN1_IN2_DIFF_STS
PHASE_MON_PBO_CNFG
MON_SW_PBO_CNFG
INTERRUPTS2_STS
78
0B
0E
ULTR_FAST_SW
LOS_FLAG_TO_TDO
T0_MAIN_REF_FAILED 1
T0_MAIN_REF_FAILED 2
REVERTIVE_MODE
INTERRUPTS2_ENABLE_CNFG
INPUT_MODE_CNFG
11
09
2A
28
INn_CMOS_SEL_PRIORITY[3:0] (n = 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
CURRENTLY_SELECTED_INPUT[3:0]
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
IN3_CMOS_SEL_PRIORITY_CNFG
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
PRIORITY_TABLE1_STS
PRIORITY_TABLE2_STS
4E
4F
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3.9
SELECTED INPUT CLOCK STATUS VS. DPLL
OPERATING MODE
Table 14: T0 DPLL Operating Mode Control
T0_OPERATING_MODE[2:0]
T0 DPLL Operating Mode
Automatic
T0 DPLL supports three primary operating modes: Free-Run, Locked
and Holdover, and three secondary, temporary operating modes: Pre-
Locked, Pre-Locked2 and Lost-Phase. The operating mode of T0 DPLL
can be switched automatically or by force, as controlled by the
T0_OPERATING_MODE[2:0] bits.
000
001
010
100
101
110
111
Forced - Free-Run
Forced - Holdover
Forced - Locked
Forced - Pre-Locked2
Forced - Pre-Locked
Forced - Lost-Phase
When the operating mode is switched by force, the operating mode
switch is under external control and the status of the selected input clock
takes no effect to the operating mode selection. The forced operating
mode switch is applicable for special cases, such as testing.
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 6.
When the operating mode is switched automatically, the internal
state machine for T0 automatically determine the operating mode.
Whether the operating mode is under external control or is switched
automatically, the current operating mode is always indicated by the
T0_DPLL_OPERATING_MODE[2:0] bits. When the operating mode
The T0 DPLL operating mode is controlled by the
T0_OPERATING_MODE[2:0] bits, as shown in Table 14:
1
switches, the T0_OPERATING_MODE
bit will be set. If the
2
T0_OPERATING_MODE bit is ‘1’, an interrupt will be generated.
1
Free-Run mode
3
2
Pre-Locked
4
mode
5
Locked
mode
6
10
Holdover
mode
9
8
7
11
Pre-Locked2
mode
12
15
Lost-Phase
mode
13
14
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode
Functional Description
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Notes to Figure 6:
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified AND No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified AND No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified AND No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
switched to another one’ - are: (The T0 selected input clock is disquali-
fied AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selec-
tion or Forced selection).
Refer to Chapter 3.8.2 Selected Input Clock Switch for details about
T0 input clock qualification.
Table 15: Related Bit / Register in Chapter 3.9
Bit
Register
Address (Hex)
T0_OPERATING_MODE[2:0]
T0_DPLL_OPERATING_MODE[2:0]
T0_DPLL_LOCK
T0_OPERATING_MODE_CNFG
53
52
OPERATING_STS
T0_OPERATING_MODE 1
T0_OPERATING_MODE 2
INTERRUPTS2_STS
0E
11
INTERRUPTS2_ENABLE_CNFG
Functional Description
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3.10.1.1 Free-Run Mode
3.10
DPLL OPERATING MODE
In Free-Run mode, the T0 DPLL output refers to the master clock
and is not affected by any input clock. The accuracy of the T0 DPLL out-
put is equal to that of the master clock.
The T0 DPLL gives a stable performance in different applications
without being affected by operating conditions or silicon process varia-
tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
3.10.1.2 Pre-Locked Mode
In Pre-Locked mode, the T0 DPLL output attempts to track the
selected input clock.
The PFD detects the phase error, including the fast loss, coarse
phase loss and fine phase loss (refer to Chapter 3.7.1.1 Fast Loss to
Chapter 3.7.1.3 Fine Phase Loss). The averaged phase error of the T0
DPLL feedback with respect to the selected input clock is indicated by
the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
The Pre-Locked mode is a secondary, temporary mode.
3.10.1.3 Locked Mode
In Locked mode, the T0 selected input clock is locked. The phase
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro-
grammable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damp-
ing factor is, the longer the locking time is and the more the gain is.
In this mode, if the T0 selected input clock is in fast loss status and
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast Loss) and will enter Lost-Phase mode when the
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock-
ing status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
The DCO controls the DPLL output. The frequency of the DPLL out-
put is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
3.10.1.3.1 Temp-Holdover Mode
The T0 DPLL will automatically enter Temp-Holdover mode with a
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to Chapter 3.10.1.5 Holdover
Mode) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode for details about the methods. The
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in Table 16:
3.10.1
The T0 DPLL loop is closed except in Free-Run mode and Holdover
mode.
SIX OPERATING MODES
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the T0 DPLL attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
Table 16: Frequency Offset Control in Temp-Holdover Mode
TEMP_HOLDOVER_MODE[1:0] Frequency Offset Acquiring Method
00
01
10
11
the same as that used in Holdover mode
Automatic Instantaneous
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
Automatic Fast Averaged
Automatic Slow Averaged
When the T0 selected input clock is locked, the locked bandwidth
and damping factor are used. They are set by the
The device automatically controls the T0 DPLL to exit from Temp-
Holdover mode.
T0_DPLL_LOCKED_BW[4:0]
bits
and
the
3.10.1.4 Lost-Phase Mode
T0_DPLL_LOCKED_DAMPING[2:0] bits respectively.
In Lost-Phase mode, the T0 DPLL output attempts to track the
selected input clock.
The corresponding bandwidth and damping factor are used when the
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
The Lost-Phase mode is a secondary, temporary mode.
Only the locked bandwidth and damping factor can be used regard-
less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
3.10.1.5 Holdover Mode
In Holdover mode, the T0 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T0 DPLL output is not
Functional Description
29
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IDT82V3203B
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phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in Table 17:
Table 17: Frequency Offset Control in Holdover Mode
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
0
don’t-care
Automatic Instantaneous
Automatic Slow Averaged
Automatic Fast Averaged
Manual
0
1
0
1
1
don’t-care
3.10.1.5.1 Automatic Instantaneous
3.10.1.5.5 Holdover Frequency Offset Read
By this method, the T0 DPLL freezes at the operating frequency
The offset value, which is acquired by Automatic Slow Averaged,
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in Table 18.
-8
when it enters Holdover mode. The accuracy is 4.4X10 ppm.
3.10.1.5.2 Automatic Slow Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
Table 18: Holdover Frequency Offset Read
Offset Value Read from
READ_AVG FAST_AVG
-5
T0_HOLDOVER_FREQ[23:0]
1.1X10 ppm.
0
1
don’t-care The value is equal to the one written to.
3.10.1.5.3 Automatic Fast Averaged
The value is acquired by Automatic Slow Averaged
method, not equal to the one written to.
0
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
1
-5
1.1X10 ppm.
The frequency offset in ppm is calculated as follows:
3.10.1.5.4 Manual
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
By this method, the frequency offset is set by the
-5
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10 ppm.
3.10.1.6 Pre-Locked2 Mode
The frequency offset of the T0 DPLL output is indicated by the
CURRENT_DPLL_FREQ[23:0] bits.
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
selected input clock.
The device provides a reference for the value to be written to the
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover
Frequency Offset Read); or then be processed by external software fil-
tering.
The Pre-Locked2 mode is a secondary, temporary mode.
Functional Description
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Table 19: Related Bit / Register in Chapter 3.10
Bit
Register
Address (Hex)
CURRENT_PH_DATA[15:0]
CURRENT_DPLL_PHASE[15:8]_STS, CURRENT_DPLL_PHASE[7:0]_STS
69, 68
CURRENT_DPLL_FREQ[23:16]_STS, CURRENT_DPLL_FREQ[15:8]_STS,
CURRENT_DPLL_FREQ[7:0]_STS
CURRENT_DPLL_FREQ[23:0]
64, 63, 62
T0_DPLL_START_BW[4:0]
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW_SEL
T0_DPLL_START_BW_DAMPING_CNFG
T0_DPLL_ACQ_BW_DAMPING_CNFG
T0_DPLL_LOCKED_BW_DAMPING_CNFG
56
57
58
T0_BW_OVERSHOOT_CNFG
59
5B
FAST_LOS_SW
PHASE_LOSS_FINE_LIMIT_CNFG
TEMP_HOLDOVER_MODE[1:0]
MAN_HOLDOVER
AUTO_AVG
T0_HOLDOVER_MODE_CNFG
5C
FAST_AVG
READ_AVG
T0_HOLDOVER_FREQ[23:16]_CNFG, T0_HOLDOVER_FREQ[15:8]_CNFG,
T0_HOLDOVER_FREQ[7:0]_CNFG
T0_HOLDOVER_FREQ[23:0]
5F, 5E, 5D
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The last condition is specially for stratum 2 and 3E clocks. The PBO
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase-
time changes of 3.5 µs or greater over an interval of less than 0.1 sec-
onds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 µs or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
1.0 µs but less than 3.5 µs that occur over an interval of less than 0.1
seconds may or may not be built-out.
3.11
DPLL OUTPUT
The DPLL output is locked to the selected input clock. According to
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1
PFD OUTPUT LIMIT
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined
by the MULTI_PH_APP bit.
An integrated Phase Transient Monitor can be enabled by the
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is pro-
grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:
3.11.2
FREQUENCY OFFSET LIMIT
The DPLL output is limited to be within the DPLL hard limit (refer to
Chapter 3.7.1.4 Hard Limit Exceeding).
The integral path value can be frozen when the DPLL hard limit is
reached. This function, enabled by the T0_LIMT bit, will minimize the
subsequent overshoot when T0 DPLL is pulling in.
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
The phase offset induced by PBO will never result in a coarse or fine
phase loss.
3.11.3
PBO
When a PBO event is triggered, the phase offset of the selected input
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase tran-
sients on the T0 DPLL output are minimized.
3.11.4
FOUR PATHS OF T0 DPLL OUTPUTS
The T0 DPLL output are phase aligned with the T0 selected input
clock every 125 µs period. T0 DPLL has four output paths as follows:
• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
• GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or
16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_
SEL[1:0] bits;
A PBO event is triggered if any one of the following conditions
occurs:
• T0 selected input clock switches (the PBO_EN bit is ‘1’);
• T0 DPLL exits from Holdover mode or Free-Run mode (the
PBO_EN bit is ‘1’);
• Phase-time changes on the T0 selected input clock are greater
than a programmable limit over an interval of less than 0.1 sec-
onds (the PH_MON_PBO_EN bit is ‘1’).
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
T0 selected input clock is compared with a T0 DPLL output for DPLL
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the out-
put is automatically divided to get the same frequency as the T0
selected input clock.
For the first two conditions, the phase transients on the T0 DPLL out-
put are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase off-
set with respect to the T0 selected input clock.
T0 DPLL outputs are provided for T0/T4 APLL or device output pro-
cess.
Functional Description
32
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 20: Related Bit / Register in Chapter 3.11
Bit
Register
Address (Hex)
MULTI_PH_APP
T0_LIMT
PHASE_LOSS_COARSE_LIMIT_CNFG
T0_BW_OVERSHOOT_CNFG
5A
59
PBO_EN
MON_SW_PBO_CNFG
0B
PBO_FREZ
PH_MON_PBO_EN
PH_MON_EN
PHASE_MON_PBO_CNFG
78
PH_TR_MON_LIMT[3:0]
PH_OFFSET_EN
PHASE_OFFSET[9:8]_CNFG
INPUT_MODE_CNFG
7B
09
IN_SONET_SDH
T0_GSM_OBSAI_16E1_16T1_SEL[1:0]
T0_12E1_24T1_E3_T3_SEL[1:0]
T0_DPLL_APLL_PATH_CNFG
55
Functional Description
33
August 21, 2007
IDT82V3203B
EBU WAN PLL
3.12
T0 / T4 APLL
3.13
OUTPUT CLOCKS & FRAME SYNC SIGNALS
A T0 APLL and a T4 APLL are provided for a better jitter and wander
performance of the device output clocks.
The device supports 2 output clocks and 2 frame sync output signals
altogether.
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
3.13.1
OUTPUT CLOCKS
The device provides 2 output clocks.
OUT1 outputs a PECL or LVDS signal, as selected by the
OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal.
The input of the T0/T4 APLL can be derived from one of the T0 DPLL
outputs, as selected by the T0_APLL_PATH[3:0] / T4_APLL_PATH[3:0]
bits respectively.
The outputs on OUT1 and OUT2 are variable, depending on the sig-
nals derived from the T0 DPLL and T0/T4 APLL outputs, and the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal can
be from the T0 DPLL and T0/T4 APLL outputs, as selected by the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is derived
from one of the T0 DPLL outputs, please refer to Table 22 for the output
frequency. If the signal is derived from the T0/T4 APLL output, please
refer to Table 23 for the output frequency.
Both the APLL and DPLL outputs are provided for selection for the
device output.
Table 21: Related Bit / Register in Chapter 3.12
Bit
Register
Address (Hex)
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
T0_T4_APLL_BW_CNFG
6A
The outputs on OUT1 and OUT2 can be inverted, as determined by
the corresponding OUTn_INV bit (n = 1 or 2).
T0_DPLL_APLL_PATH_CNFG
T4_APLL_PATH_CNFG
55
60
Both the output clocks derived from T0 selected input clock are
aligned with the T0 selected input clock every 125 µs period.
Table 22: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs
outputs on OUT1 & OUT2 if derived from T0 DPLL outputs 2
OUTn_DIVIDER[3:0]
1
(Output Divider)
77.76 MHz
12E1
16E1
24T1
16T1
E3
T3
GSM (26 MHz) OBSAI (30.72 MHz)
0000
0001
0010
0011
Output is disabled (output low).
12E1
6E1
3E1
2E1
16E1
8E1
24T1
12T1
6T1
16T1
8T1
E3
T3
13 MHz
15.36 MHz
0100
0101
0110
4E1
4T1
4T1
2E1
E1
3T1
2T1
T1
0111
E1
2T1
1000
1001
1010
1011
T1
64 kHz
8 kHz
2 kHz
400 Hz
1Hz
1100
1101
1110
1111
Output is disabled (output high).
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
Functional Description
34
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 23: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL
outputs on OUT1 & OUT2 if derived from T0/T4 APLL output 2
OUTn_DIVIDER[3:0]
1
(Output Divider)
77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4
E3
T3
GSM (26 MHz X 2) OBSAI (30.72 MHz X 10)
0000
0001
Output is disabled (output low).
622.08 MHz 3
311.04 MHz 3
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
0010
0011
0100
0101
0110
0111
1000
1001
48E1
24E1
12E1
8E1
64E1
32E1
16E1
96T1
48T1
24T1
16T1
12T1
8T1
64T1
32T1
16T1
E3
T3
52 MHz
26 MHz
13 MHz
153.6 MHz
76.8 MHz
6E1
8E1
4E1
8T1
4T1
38.4 MHz
4E1
3E1
6T1
61.44 MHz 4
30.72 MHz 4
15.36 MHz 4
7.68 MHz 4
3.84 MHz 4
2E1
4T1
1010
1011
1100
1101
2E1
E1
3T1
2T1
2T1
T1
6.48 MHz
E1
T1
1110
1111
Output is disabled (output high).
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. In the APLL, the selected T0 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1.
4. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL.
Functional Description
35
August 21, 2007
IDT82V3203B
EBU WAN PLL
3.13.2
FRAME SYNC OUTPUT SIGNALS
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 25 for details.
A 2 kHz and an 8 kHz frame sync signals are output on the
MFRSYNC_2K and FRSYNC_8K pin if enabled by the 2K_EN and
8K_EN bits respectively. They are CMOS outputs.
When the selected frame sync input signal is enabled to synchronize
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting the sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1
,2 or 3 corresponding to EX_SYNC1, EX_SYNC2 or EX_SYNC3
respectively) will compensate this early/late. Refer to Figure 7 to
Figure 10.
The frame sync signals are derived from the T0 APLL output and are
aligned with the output clock. They can be synchronized to one of the
three frame sync input signals.
One of the three frame sync input signals is selected, as determined
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
Table 24:
Table 24: Frame Sync Input Signal Selection
Selected Frame Sync Input
SYNC_BYPASS T0 Selected Input Clock
Signal
The EX_SYNC_ALARM_MON bit indicates whether the selected
frame sync input signal is in external sync alarm status. The external
0
don’t-care
IN1_DIFF
IN2_DIFF
IN3_CMOS
none
EX_SYNC1
EX_SYNC1
EX_SYNC2
EX_SYNC3
none
1
sync alarm is indicated by the EX_SYNC_ALARM
bit. If the
2
EX_SYNC_ALARM bit is ‘1’, the occurrence of the external sync alarm
will trigger an interrupt.
1
The 8 kHz and the 2 kHz frame sync output signals can be inverted
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT2; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
If the selected frame sync input signal with respect to the T0 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signals. The exter-
nal sync alarm is cleared once the selected frame sync input signal with
respect to the T0 selected input clock is within the limit. If it is within the
Table 25: Synchronization Control
SYNC_BYPASS
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
don’t-care
0
1
1
Disabled
Enabled
Disabled
Enabled
0
1
0
1
don’t-care
T0 selected
input clock
T0 selected
input clock
Selected frame
sync input signal
Selected frame
sync input signal
Frame sync
output signals
Frame sync
output signals
Output clocks
Output clocks
Figure 7. On Target Frame Sync Input Signal Timing
Figure 8. 0.5 UI Early Frame Sync Input Signal Timing
Functional Description
36
August 21, 2007
IDT82V3203B
EBU WAN PLL
T0 selected
input clock
T0 selected
input clock
Selected frame
Selected frame
sync input signal
sync input signal
Frame sync
Frame sync
output signals
output signals
Output clocks
Output clocks
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing
Figure 10. 1 UI Late Frame Sync Input Signal Timing
Table 26: Related Bit / Register in Chapter 3.13
Bit
Register
Address (Hex)
OUT1_PECL_LVDS
OUTn_PATH_SEL[3:0] (n = 1 or 2)
OUTn_DIVIDER[3:0] (n = 1 or 2)
IN_SONET_SDH
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
DIFFERENTIAL_IN_OUT_OSCI_CNFG
0A
OUT1_FREQ_CNFG, OUT2_FREQ_CNFG
71, 6D
INPUT_MODE_CNFG
09
OUTn_INV (n = 1 or 2)
8K_EN
OUT1_INV_CNFG, OUT2_INV_CNFG
73, 72
2K_EN
8K_INV
2K_INV
FR_MFR_SYNC_CNFG
74
8K_PUL
2K_PUL
2K_8K_PUL_POSITION
SYNC_BYPASS
SYNC_MONITOR_CNFG
7C
SYNC_MON_LIMT[2:0]
SYNC_PHn[1:0] (n = 1, 2 or 3)
EX_SYNC_ALARM_MON
SYNC_PHASE_CNFG
OPERATING_STS
7D
52
0F
EX_SYNC_ALARM 1
EX_SYNC_ALARM 2
INTERRUPTS3_STS
INTERRUPTS3_ENABLE_CNFG
12
Functional Description
37
August 21, 2007
IDT82V3203B
EBU WAN PLL
3.14
INTERRUPT SUMMARY
3.15
T0 SUMMARY
The interrupt sources of the device are as follows:
The main features supported by the T0 path are as follows:
• Phase lock alarm;
• T0 Input clocks validity change
• T0 selected input clock fail
• T0 DPLL operating mode switch
• External sync alarm
• Forced or Automatic input clock selection/switch;
• 3 primary and 3 secondary, temporary DPLL operating modes,
switched automatically or under external control;
• Automatic switch between starting, acquisition and locked band-
widths/damping factors;
• Programmable DPLL bandwidths from 0.1 Hz to 560 Hz in 11
steps;
• Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
All of the above interrupt events are indicated by the corresponding
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output charac-
teristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
Interrupt events are cleared by writing a ‘1’ to the corresponding
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
• Output phase and frequency offset limited;
• Automatic Instantaneous, Automatic Slow Averaged, Automatic
Fast Averaged or Manual holdover frequency offset acquiring;
• PBO to minimize output phase transients;
In addition, the interrupt of T0 selected input clock fail can be
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
• Programmable output phase offset;
• Low jitter multiple clock outputs with programmable polarity;
• Low jitter 2 kHz and 8 kHz frame sync signal outputs with pro-
grammable pulse width and polarity;
Table 27: Related Bit / Register in Chapter 3.14
Bit
Register
Address (Hex)
HZ_EN
INT_POL
INTERRUPT_CNFG
0C
0B
LOS_FLAG_TO_TDO
MON_SW_PBO_CNFG
Functional Description
38
August 21, 2007
IDT82V3203B
EBU WAN PLL
3.16
LINE CARD APPLICATION
Clock
Sync
OC-n Clock
Sync
Master Clock
Board
SDH/SONET
System
Optical signal
155 M, 622 M, 2.5 G,
or 10 Gbit/s
Chip
e.g.
Transciever
TSE
IDT82V3203B
Clock
Sync
Slave Clock
Board
......
OC-n Line Card Board
Backplane
Figure 11. Line Card Application
Functional Description
39
August 21, 2007
IDT82V3203B
EBU WAN PLL
2
4.1
FUNCTION DESCRIPTION
4
I C PROGRAMMING
The timing of a complete data transfer is shown in Figure 12.
INTERFACE
The transfer process can be divided into three phases:
• START (S) or repeated START (Sr) condition;
• Byte data transfer condition;
2
The I C bus interface provides access to read and write the registers
in the IDT82V3203B.
• STOP (P) condition.
The definitions of S/Sr and P conditions are shown in Table 28:
Table 28: Definition of S/Sr and P Conditions
Condition
Definition
S/Sr
P
A high to low transition on the SDA pin while the SCL pin is high.
A low to high transition on the SDA pin while the SCL pin is high.
Every byte put on the SDA line must be 8-bit long. The number of
bytes that can be transmitted per transfer is unrestricted in theory. Each
byte has to be followed by an acknowledge bit (ACK). So the whole data
transfer needs a period of 9 clock cycles. The data is transferred with the
most significant bit (MSB) first.
P
SDA
SCL
acknowledgement
signal from the slave device
acknowledgement
signal from receiver
MSB
Sr
byte complete,
interrupt within the Slave device
clock line held low while
interrupts are serviced
9
2
3-8
2
8
1
9
1
7
S
or
Sr
Sr
or
P
ACK
ACK
STOP or
repeated START
condition
START or
repeated START
condition
2
Figure 12. Data Transfer on the I C-bus
I2C Programming Interface
40
August 21, 2007
IDT82V3203B
EBU WAN PLL
4.1.1
Two kinds of data transfer formats are supported by the
IDT82V3203B:
• Slave-receiver mode (Write);
• Slave-transmitter mode (Read);
DATA TRANSFER FORMAT
4.1.1.1
Slave-receiver Mode (Write)
The Slave-receiver mode is as shown in Figure 13.
The Master device asserts the slave address followed by the Write
bit. The Slave device acknowledges and the Master device delivers the
address byte. The Slave device again acknowledges before the Master
device sends the data byte. The Slave device acknowledges each byte,
and the entire transaction is finished with a STOP condition.
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Address Byte
A
Data Byte
A
P
S
Start Condition
Master-to-Slave
Slave-to-Master
Write (bit value of 0)
Stop Condition
Wr
P
A
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
Figure 13. Slave-receiver Mode
4.1.1.2
Slave-transmitter Mode (Read)
The Slave-transmitter mode is as shown in Figure 14.
First the Master device must write an address byte to the slave
device. Then it must follow that address byte with a repeated START
condition to denote a read from that device’s address. The Slave device
then returns one byte data corresponding the address. Note that there is
no STOP condition before the repeated STRAT condition, and that a no-
acknowledge (NACK) signifies the end of the read transfer.
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Address Byte
A
Slave Address
Rd
A
Data Byte
A
P
S
S
Start Condition
P
Stop Condition
Read (bit value of 1)
Master-to-Slave
Rd
Wr
Write (bit value of 0)
Slave-to-Master
A
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
Figure 14. Slave-transmitter Mode
I2C Programming Interface
41
August 21, 2007
IDT82V3203B
EBU WAN PLL
4.1.2
ADDRESS ASSIGNMENT
Each device is recognized by a unique slave address. The slave
addressing procedure for the I2C-bus is such that the first byte after the
START condition usually determines which slave device will be selected
by the Master device. In this specification, the 4 MSB bits of the address
byte are fixed and the 3 LSB bits are decided by address input pins
AD[2:0], as shown in Figure 15.
A6
1
A5
0
A4
1
A3
0
A2
A1
A0
R/W
AD2 AD1 AD0 1/0
The R/W bit is used as a data transfer direction bit which is deter-
mined by the Master device. A ‘0’ on this bit indicates a transmission
(Write) to registers and a ‘1’ indicates a request for data (Read) from the
registers.
Figure 15. Address Assignment
4.2
TIMING DEFINITION
The timing of I2C-bus is as shown in Figure 16.
SDA
tf
tf
tSU: DAT
tHD: STA
tr
tBUF
tSP
tLOW
tr
SCL
tSU: STO
tHD: STA
tSU: STA
tHD: DAT
S
tHIGH
P
S
Sr
2
Figure 16. Timing Definition of I C-bus
Table 29: Timing Definition
Symbol
Limits
Parameter
Unit
Min
10
60
120
120
60
0
Max
SCL
Serial clock frequency
2000
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD; STA
Hold time (repeated) START condition. After this period, the first clock pulse is generated
LOW period of the SCL clock
-
-
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tr
HIGH period of the SCL clock
-
Set-up time for a repeated START condition
-
Data hold time: for CBUS compatible masters for I2C-bus devices
Data set-up time
150
-
10
20
20
60
100
0
Rise time of both SDA and SCL signals
80
80
-
tf
Fall time of both SDA and SCL signals
tSU; STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes which must be suppressed by the input filter
-
tsp
50
I2C Programming Interface
42
August 21, 2007
IDT82V3203B
EBU WAN PLL
5
JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
dard except the following:
• The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
• The TRST pin is set low by default and JTAG is disabled in order
to be consistent with other manufacturers.
The JTAG interface timing diagram is shown in Figure 17.
tTCK
TCK
tS
tH
TMS
TDI
tD
TDO
Figure 17. JTAG Interface Timing Diagram
Table 30: JTAG Timing Characteristics
Symbol
Parameter
Min
100
25
Typ
Max
Unit
ns
tTCK
tS
TCK period
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
ns
tH
25
ns
tD
50
ns
JTAG
43
August 21, 2007
IDT82V3203B
EBU WAN PLL
6
PROGRAMMING INFORMATION
After reset, all the registers are set to their default values. The regis-
ters are read or written via the microprocessor interface.
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration con-
figuration will take effect after all the three registers are configured. Dur-
ing read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
Before any write operation, the value in register
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
• Protected mode: no other registers can be written except register
PROTECTION_CNFG itself;
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one more register can be written
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device auto-
matically switches to Protected mode.
Certain bit locations within the device register map are designated as
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
Writing ‘0’ to the registers will take no effect if the registers are
cleared by writing ‘1’.
6.1
REGISTER MAP
Table 31 is the map of all the registers, sorted in an ascending order
of their addresses.
The access of the Multi-word Registers is different from that of the
Single-word Registers. Take the registers (04H, 05H and 06H) for an
Table 31: Register List and Map
Address
Reference
Page
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Hex)
Global Control Registers
00
01
ID[7:0] - Device ID 1
ID[7:0]
P 49
P 49
ID[15:8] - Device ID 2
ID[15:8]
NOMINAL_FREQ[7:0]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 1
04
05
06
08
09
0A
NOMINAL_FREQ_VALUE[7:0]
NOMINAL_FREQ_VALUE[15:8]
NOMINAL_FREQ_VALUE[23:16]
P 49
P 50
P 50
P 51
P 52
P 53
NOMINAL_FREQ[15:8]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 2
NOMINAL_FREQ[23:16]_CNFG
-
Crystal Oscillator Frequency Offset
Calibration Configuration 3
PHASE_ALARM_TIME_OUT_CNFG -
Phase Lock Alarm Time-Out Configu- MULTI_FACTOR[1:0]
ration
TIME_OUT_VALUE[5:0]
IN_SONET
AUTO_EX
T_SYNC_
EN
PH_ALAR
M_TIMEO
UT
INPUT_MODE_CNFG - Input Mode
Configuration
EXT_SYN
C_EN
REVERTIV
E_MODE
SYNC_FREQ[1:0]
-
_SDH
DIFFERENTIAL_IN_OUT_OSCI_CNF
G - Differential Input / Output Port &
Master Clock Configuration
OSC_EDG OUT1_PE
-
-
-
-
-
-
E
CL_LVDS
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
LOS_FLA
G_TO_TD
O
FREQ_MO
N_HARD_
EN
FREQ_MO
N_CLK
ULTR_FAS
T_SW
PBO_FRE
Z
0B
7E
EXT_SW
PBO_EN
-
P 54
P 55
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
PROTECTION_DATA[7:0]
Interrupt Registers
INTERRUPT_CNFG - Interrupt Config-
uration
0C
-
-
-
-
-
-
HZ_EN
INT_POL
P 56
Programming Information
44
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 31: Register List and Map (Continued)
Address
Reference
Page
Register Name
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTERRUPTS1_STS - Interrupt Status
0D
1
-
-
IN2_DIFF IN1_DIFF
-
-
-
-
P 56
T0_OPER T0_MAIN_
ATING_MO REF_FAIL
INTERRUPTS2_STS - Interrupt Status
2
0E
-
-
-
-
-
-
-
IN3_CMOS
P 57
DE
ED
INTERRUPTS3_STS - Interrupt Status EX_SYNC
0F
10
-
-
-
-
-
-
-
-
-
P 57
P 58
3
_ALARM
-
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
-
-
-
IN2_DIFF IN1_DIFF
T0_OPER T0_MAIN_
ATING_MO REF_FAIL
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
11
12
-
-
-
-
-
-
-
IN3_CMOS
-
P 58
P 59
DE
ED
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
- EX_SYNC
_ALARM
-
-
-
-
Input Clock Frequency & Priority Configuration Registers
IN1_IN2_DIFF_HF_DIV_CNFG - Dif-
18
ferential Input Clock 1 & 2 High Fre- IN2_DIFF_DIV[1:0]
quency Divider Configuration
-
-
-
-
IN1_DIFF_DIV[1:0]
P 60
IN1_DIFF_CNFG - Differential Input DIRECT_D
LOCK_8K
19
1A
1D
23
24
25
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 61
P 62
P 63
P 64
P 64
P 65
Clock 1 Configuration
IV
IN2_DIFF_CNFG - Differential Input DIRECT_D
LOCK_8K
LOCK_8K
-
IN_FREQ[3:0]
IN_FREQ[3:0]
Clock 2 Configuration
IV
IN3_CMOS_CNFG - CMOS Input DIRECT_D
Clock 3 Configuration
IV
-
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
-
-
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN_VALUE[7:0]
PRE_DIVN_VALUE[14:8]
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
-
DivN
-
IN1_IN2_DIFF_SEL_PRIORITY_CNF
G - Differential Input Clock 1 & 2 Prior-
ity Configuration
28
IN2_DIFF_SEL_PRIORITY[3:0]
IN1_DIFF_SEL_PRIORITY[3:0]
P 66
P 67
IN3_CMOS_SEL_PRIORITY_CNFG -
CMOS Input Clock 3 Priority Configu-
ration
2A
-
-
-
-
IN3_CMOS_SEL_PRIORITY[3:0]
Input Clock Quality Monitoring Configuration & Status Registers
FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration
2E
2F
-
-
-
-
FREQ_MON_FACTOR[3:0]
P 68
P 68
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
All Input Clocks Configuration
-
-
-
-
ALL_FREQ_HARD_THRESHOLD[3:0]
UPPER_THRESHOLD_0_CNFG
-
31
Upper Threshold for Leaky Bucket
Configuration 0
UPPER_THRESHOLD_0_DATA[7:0]
P 69
LOWER_THRESHOLD_0_CNFG
-
32
33
Lower Threshold for Leaky Bucket
Configuration 0
LOWER_THRESHOLD_0_DATA[7:0]
BUCKET_SIZE_0_DATA[7:0]
P 69
P 69
BUCKET_SIZE_0_CNFG
- Bucket
Size for Leaky Bucket Configuration 0
Programming Information
45
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 31: Register List and Map (Continued)
Address
Reference
Page
Register Name
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0
DECAY_RATE_0_DATA
[1:0]
34
-
-
-
-
-
-
P 70
UPPER_THRESHOLD_1_CNFG
-
35
36
Upper Threshold for Leaky Bucket
Configuration 1
UPPER_THRESHOLD_1_DATA[7:0]
P 70
P 70
LOWER_THRESHOLD_1_CNFG
-
Lower Threshold for Leaky Bucket
Configuration 1
LOWER_THRESHOLD_1_DATA[7:0]
BUCKET_SIZE_1_DATA[7:0]
BUCKET_SIZE_1_CNFG
- Bucket
37
38
P 71
P 71
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
for Leaky Bucket Configuration 1
DECAY_RATE_1_DATA
[1:0]
-
-
-
-
-
-
-
-
UPPER_THRESHOLD_2_CNFG
-
39
Upper Threshold for Leaky Bucket
Configuration 2
UPPER_THRESHOLD_2_DATA[7:0]
P 71
P 72
LOWER_THRESHOLD_2_CNFG
-
3A
Lower Threshold for Leaky Bucket
Configuration 2
LOWER_THRESHOLD_2_DATA[7:0]
BUCKET_SIZE_2_DATA[7:0]
BUCKET_SIZE_2_CNFG
- Bucket
3B
3C
P 72
P 72
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
for Leaky Bucket Configuration 2
DECAY_RATE_2_DATA
[1:0]
-
-
-
-
-
UPPER_THRESHOLD_3_CNFG
-
3D
3E
Upper Threshold for Leaky Bucket
Configuration 3
UPPER_THRESHOLD_3_DATA[7:0]
P 73
P 73
LOWER_THRESHOLD_3_CNFG
-
Lower Threshold for Leaky Bucket
Configuration 3
LOWER_THRESHOLD_3_DATA[7:0]
BUCKET_SIZE_3_DATA[7:0]
BUCKET_SIZE_3_CNFG
- Bucket
3F
40
P 73
P 74
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
for Leaky Bucket Configuration 3
DECAY_RATE_3_DATA
[1:0]
-
-
-
-
-
-
-
-
-
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
41
42
IN_FREQ_READ_CH[3:0]
P 74
P 75
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
IN_FREQ_VALUE[7:0]
IN2_DIFF_
IN2_DIFF_ IN2_DIFF_
FREQ_HA NO_ACTIV
RD_ALAR ITY_ALAR
IN1_DIFF_ IN1_DIFF_
FREQ_HA NO_ACTIV
RD_ALAR ITY_ALAR
IN1_DIFF_
PH_LOCK
_ALARM
IN1_IN2_DIFF_STS - Differential Input
Clock 1 & 2 Status
45
47
-
-
PH_LOCK
_ALARM
-
P 75
P 76
M
M
M
M
IN3_CMOS IN3_CMOS
_FREQ_H _NO_ACTI
ARD_ALA VITY_ALA
IN3_CMOS
_PH_LOC
K_ALARM
IN3_CMOS_STS - CMOS Input Clock
3 Status
-
-
-
-
RM
RM
T0 DPLL Input Clock Selection Registers
INPUT_VALID1_STS - Input Clocks
Validity 1
4A
4B
-
-
-
-
IN2_DIFF IN1_DIFF
-
-
-
-
-
-
-
P 77
P 78
PRIORITY_TABLE1_STS
Status 1
- Priority
-
-
IN3_CMOS
Programming Information
46
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 31: Register List and Map (Continued)
Address
Reference
Page
Register Name
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRIORITY_TABLE1_STS
Status 1
-
-
Priority
Priority
4E
4F
50
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
P 78
PRIORITY_TABLE2_STS
Status 2
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
P 79
P 79
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
-
-
-
-
T0_INPUT_SEL[3:0]
T0 DPLL State Machine Control Registers
EX_SYNC
_ALARM_
MON
T0_DPLL_
SOFT_FRE
Q_ALARM
OPERATING_STS - DPLL Operating
Status
T0_DPLL_
LOCK
52
53
-
-
T0_DPLL_OPERATING_MODE[2:0]
T0_OPERATING_MODE[2:0]
P 80
P 81
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
-
-
-
-
-
T0 DPLL & T0/T4 APLL Configuration Registers
T0_GSM_OBSAI_16E1 T0_12E1_24T1_E3_T3
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
55
56
T0_APLL_PATH[3:0]
P 82
P 83
_16T1_SEL[1:0]
_SEL[1:0]
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth & T0_DPLL_START_DAMPING[2:0]
Damping Factor Configuration
T0_DPLL_START_BW[4:0]
T0_DPLL_ACQ_BW_DAMPING_CNF
57
58
59
5A
G - T0 DPLL Acquisition Bandwidth & T0_DPLL_ACQ_DAMPING[2:0]
Damping Factor Configuration
T0_DPLL_ACQ_BW[4:0]
P 84
P 85
P 85
P 86
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth & T0_DPLL_LOCKED_DAMPING[2:0]
Damping Factor Configuration
T0_DPLL_LOCKED_BW[4:0]
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configu-
ration
AUTO_BW
_SEL
-
-
-
T0_LIMT
-
-
-
PHASE_LOSS_COARSE_LIMIT_CNF COARSE_
G - Phase Loss Coarse Detector Limit PH_LOS_L WIDE_EN
Configuration IMT_EN
MULTI_PH
_8K_4K_2
K_EN
MULTI_PH
_APP
PH_LOS_COARSE_LIMT[3:0]
PHASE_LOSS_FINE_LIMIT_CNFG - FINE_PH_
Phase Loss Fine Detector Limit Con- LOS_LIMT
FAST_LOS
_SW
5B
5C
5D
-
-
-
PH_LOS_FINE_LIMT[2:0]
P 87
P 88
P 88
figuration
_EN
T0_HOLDOVER_MODE_CNFG - T0 MAN_HOL AUTO_AV
READ_AV TEMP_HOLDOVER_M
FAST_AVG
-
-
DPLL Holdover Mode Configuration
DOVER
G
G
ODE[1:0]
T0_HOLDOVER_FREQ[7:0]_CNFG -
T0 DPLL Holdover Frequency Config-
uration 1
T0_HOLDOVER_FREQ[7:0]
T0_HOLDOVER_FREQ[15:8]
T0_HOLDOVER_FREQ[23:16]
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 2
5E
5F
P 89
P 89
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 3
T4_APLL_PATH_CNFG - T4 APLL
Path Configuration
60
62
63
T4_APLL_PATH[3:0]
-
CURRENT_DPLL_FREQ[7:0]
CURRENT_DPLL_FREQ[15:8]
-
P 89
P 90
P 90
CURRENT_DPLL_FREQ[7:0]_STS
DPLL Current Frequency Status 1
-
CURRENT_DPLL_FREQ[15:8]_STS -
DPLL Current Frequency Status 2
Programming Information
47
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 31: Register List and Map (Continued)
Address
Reference
Page
Register Name
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3
64
CURRENT_DPLL_FREQ[23:16]
P 90
DPLL_FREQ_SOFT_LIMIT_CNFG - FREQ_LIM
65
66
67
68
69
6A
DPLL_FREQ_SOFT_LIMT[6:0]
DPLL_FREQ_HARD_LIMT[7:0]
DPLL_FREQ_HARD_LIMT[15:8]
CURRENT_PH_DATA[7:0]
P 91
P 91
P 91
P 92
P 92
P 92
DPLL Soft Limit Configuration
T_PH_LOS
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS -
DPLL Current Phase Status 1
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2
CURRENT_PH_DATA[15:8]
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
-
-
T0_APLL_BW[1:0]
-
-
T4_APLL_BW[1:0]
Output Configuration Registers
OUT2_FREQ_CNFG - Output Clock 2
Frequency Configuration
6D
71
72
73
OUT2_PATH_SEL[3:0]
OUT2_DIVIDER[3:0]
OUT1_DIVIDER[3:0]
P 93
P 93
P 94
P 94
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
OUT1_PATH_SEL[3:0]
OUT1_INV_CNFG - Output Clock 1
Invert Configuration
-
-
-
-
-
-
-
-
-
-
OUT1_INV
-
-
-
OUT2_INV_CNFG - Output Clock 2
Invert Configuration
-
OUT2_INV
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
2K_8K_PU
L_POSITI 8K_INV
ON
IN_2K_4K_
8K_INV
74
78
8K_EN
2K_EN
8K_PUL
2K_INV
2K_PUL
P 95
P 96
PBO & Phase Offset Control Registers
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
IN_NOISE
_WINDOW
PH_MON_ PH_MON_
-
PH_TR_MON_LIMT[3:0]
EN
PBO_EN
Synchronization Configuration Registers
SYNC_MONITOR_CNFG - Sync Mon- SYNC_BY
7C
7D
SYNC_MON_LIMT[2:0]
-
-
-
-
P 97
P 98
itor Configuration
PASS
SYNC_PHASE_CNFG - Sync Phase
Configuration
-
-
SYNC_PH3[1:0]
SYNC_PH2[1:0]
SYNC_PH1[1:0]
Programming Information
48
August 21, 2007
IDT82V3203B
EBU WAN PLL
6.2
REGISTER DESCRIPTION
6.2.1
GLOBAL CONTROL REGISTERS
ID[7:0] - Device ID 1
Address: 00H
Type: Read
Default Value: 10001000
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit
Name
ID[7:0]
Description
7 - 0
Refer to the description of the ID[15:8] bits (b7~0, 01H).
ID[15:8] - Device ID 2
Address: 01H
Type: Read
Default Value: 00010001
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
Bit
Name
ID[15:8]
Description
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3203B.
7 - 0
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
Address: 04H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE7
NOMINAL_FRE
Q_VALUE6
NOMINAL_FRE
Q_VALUE5
NOMINAL_FRE
Q_VALUE4
NOMINAL_FRE
Q_VALUE3
NOMINAL_FRE
Q_VALUE2
NOMINAL_FRE
Q_VALUE1
NOMINAL_FRE
Q_VALUE0
Bit
Name
Description
7 - 0 NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
Programming Information
49
August 21, 2007
IDT82V3203B
EBU WAN PLL
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
Address: 05H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE15
NOMINAL_FRE
Q_VALUE14
NOMINAL_FRE
Q_VALUE13
NOMINAL_FRE
Q_VALUE12
NOMINAL_FRE
Q_VALUE11
NOMINAL_FRE
Q_VALUE10
NOMINAL_FRE
Q_VALUE9
NOMINAL_FRE
Q_VALUE8
Bit
Name
Description
7 - 0 NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
Address: 06H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE23
NOMINAL_FRE
Q_VALUE22
NOMINAL_FRE
Q_VALUE21
NOMINAL_FRE
Q_VALUE20
NOMINAL_FRE
Q_VALUE19
NOMINAL_FRE
Q_VALUE18
NOMINAL_FRE
Q_VALUE17
NOMINAL_FRE
Q_VALUE16
Bit
Name
Description
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
7 - 0 NOMINAL_FREQ_VALUE[23:16] calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
Programming Information
50
August 21, 2007
IDT82V3203B
EBU WAN PLL
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 08H
Type: Read / Write
Default Value: 00110010
7
6
5
4
3
2
1
0
MULTI_FACTO
R1
MULTI_FACTO
R0
TIME_OUT_VA
LUE5
TIME_OUT_VA
LUE4
TIME_OUT_VA
LUE3
TIME_OUT_VA
LUE2
TIME_OUT_VA
LUE1
TIME_OUT_VAL
UE0
Bit
Name
Description
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
7 - 6
MULTI_FACTOR[1:0]
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
5 - 0
TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
Programming Information
51
August 21, 2007
IDT82V3203B
EBU WAN PLL
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100X10
7
6
5
4
3
2
1
-
0
AUTO_EXT_SY
NC_EN
PH_ALARM_TI
MEOUT
IN_SONET_SD
H
REVERTIVE_M
ODE
EXT_SYNC_EN
SYNC_FREQ1
SYNC_FREQ0
Bit
Name
Description
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
7
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether the selected frame sync input signal is
enabled to synchronize the frame sync output signals.
AUTO_EXT_SYNC_EN EXT_SYNC_EN
Synchronization
6
don’t-care
0
1
1
Disabled (default)
Enabled
0
1
Disabled
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM bit (n = 1
PH_ALARM_TIMEOUT or 2) (b4/0, 44H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
5
(b7~6, 08H) in second) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC2 pins.
00: 8 kHz (default)
4 - 3
SYNC_FREQ[1:0] 01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H) are ‘0001’ and the T0 DPLL
output from the 16E1/16T1 path is 16E1.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H) are ‘0001’ and the T0
DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
Reserved.
2
IN_SONET_SDH
-
1
0
This bit selects Revertive or Non-Revertive switch.
REVERTIVE_MODE 0: Non-Revertive switch. (default)
1: Revertive switch.
Programming Information
52
August 21, 2007
IDT82V3203B
EBU WAN PLL
DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Address: 0AH
Type: Read / Write
Default Value: XXXXX00X
7
-
6
-
5
-
4
-
3
-
2
1
0
-
OSC_EDGE
OUT1_PECL_LVDS
Bit
Name
Description
7 - 3
-
Reserved.
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
2
OSC_EDGE
1: The falling edge.
This bit selects a port technology for OUT1.
1
0
OUT1_PECL_LVDS 0: LVDS. (default)
1: PECL.
-
Reserved
Programming Information
53
August 21, 2007
IDT82V3203B
EBU WAN PLL
MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
7
6
5
4
3
2
1
-
0
FREQ_MON_C LOS_FLAG_TO
LK _TDO
FREQ_MON_H
ARD_EN
ULTR_FAST_SW
EXT_SW
PBO_FREZ
PBO_EN
Bit
Name
Description
The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
7
FREQ_MON_CLK
LOS_FLAG_TO_TDO
ULTR_FAST_SW
EXT_SW
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE
1149.1.
6
5
4
This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
0: Valid. (default)
1: Invalid.
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the cur-
rent phase offset when a PBO event is triggered.
0: Not frozen. (default)
3
PBO_FREZ
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover
mode or Free-Run mode occurs.
0: Disabled.
1: Enabled. (default)
2
1
PBO_EN
-
Reserved.
This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the mas-
0
FREQ_MON_HARD_EN ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
Programming Information
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PROTECTION_CNFG - Register Protection Mode Configuration
Address: 7EH
Type: Read / Write
Default Value: 10000101
7
6
5
4
3
2
1
0
PROTECTION_ PROTECTION_ PROTECTION_ PROTECTION_ PROTECTION_ PROTECTION_ PROTECTION_
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1
PROTECTION_
DATA0
Bit
Name
Description
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
7 - 0
PROTECTION_DATA[7:0] 10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
Programming Information
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6.2.2
INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
7
-
6
-
5
-
4
-
3
-
2
-
1
0
HZ_EN
INT_POL
Bit
Name
Description
7 - 2
-
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
1
0
HZ_EN
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
INT_POL
INTERRUPTS1_STS - Interrupt Status 1
Address: 0DH
Type: Read / Write
Default Value: XX11XXXX
7
-
6
-
5
4
3
-
2
-
1
-
0
-
IN2_DIFF
IN1_DIFF
Bit
Name
Description
7 - 6
-
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_DIFF; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_DIFF bit (b5/4, 4AH). Here n is 2 or 1.
5 - 4
3 - 0
INn_DIFF
-
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
Programming Information
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INTERRUPTS2_STS - Interrupt Status 2
Address: 0EH
Type: Read / Write
Default Value: 00XXXXX1
7
6
5
-
4
-
3
-
2
-
1
-
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
IN3_CMOS
Bit
Name
Description
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
7
T0_OPERATING_MODE 0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS bit (4AH).
T0_MAIN_REF_FAILED 0: Has not failed. (default)
6
5 - 1
0
1: Has failed.
This bit is cleared by writing a ‘1’.
-
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN3_CMOS for T0 path, i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding IN3_CMOS bit (b0, 4BH).
IN3_CMOS
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
INTERRUPTS3_STS - Interrupt Status 3
Address: 0FH
Type: Read / Write
Default Value: 1XXXXXXX
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
EX_SYNC_ALARM
Bit
Name
Description
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
7
EX_SYNC_ALARM 0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
6 - 0
-
Reserved.
Programming Information
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INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
Address: 10H
Type: Read / Write
Default Value: XX00XXXX
7
-
6
-
5
4
3
-
2
-
1
-
0
-
IN2_DIFF
IN1_DIFF
Bit
Name
Description
7 - 6
5 - 4
3 - 0
-
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_DIFF bit (b5/4, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
INn_DIFF
-
Reserved.
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Address: 11H
Type: Read / Write
Default Value: 00XXXXX0
7
6
5
-
4
-
3
-
2
-
1
-
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
IN3_CMOS
Bit
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
7
T0_OPERATING_MODE
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
6
5 - 1
0
T0_MAIN_REF_FAILED
-
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
IN3_CMOS
Programming Information
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INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Address: 12H
Type: Read / Write
Default Value: 0XXXXXXX
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
EX_SYNC_ALARM
Bit
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
7
EX_SYNC_ALARM
-
6 - 0
Reserved.
Programming Information
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6.2.3
INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Frequency Divider Configuration
Address: 18H
Type: Read / Write
Default Value: 00XXXX00
7
6
5
-
4
-
3
-
2
-
1
0
IN2_DIFF_DIV1 IN2_DIFF_DIV0
IN1_DIFF_DIV1 IN1_DIFF_DIV0
Bit
Name
Description
These bits determine whether the HF Divider is used and what the division factor is for IN2_DIFF frequency division:
00: Bypassed. (default)
7 - 6
5 - 2
1 - 0
IN2_DIFF_DIV[1:0] 01: Divided by 4.
10: Divided by 5.
11: Reserved.
-
Reserved.
These bits determine whether the HF Divider is used and what the division factor is for IN1_DIFF frequency division:
00: Bypassed. (default)
IN1_DIFF_DIV[1:0] 01: Divided by 4.
10: Divided by 5.
11: Reserved.
Programming Information
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IN1_DIFF_CNFG - Differential Input Clock 1 Configuration
Address: 19H
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 19H).
Description
7
This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN1_DIFF:
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
6
LOCK_8K
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN1_DIFF:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
5 - 4
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN1_DIFF:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
3 - 0
IN_FREQ[3:0]
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
The required frequency should not be set higher than that of the input clock.
Programming Information
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IN2_DIFF_CNFG - Differential Input Clock 2 Configuration
Address: 1AH
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1AH).
Description
7
This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN2_DIFF:
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
6
LOCK_8K
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN2_DIFF:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
5 - 4
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2_DIFF:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
3 - 0
IN_FREQ[3:0]
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN2_DIFF, the required frequency should not be set higher than that of the input clock.
Programming Information
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IDT82V3203B
EBU WAN PLL
IN3_CMOS_CNFG - CMOS Input Clock 3 Configuration
Address: 1DH
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1DH).
This bit, together with the DIRECT_DIV bit (b7, 1DH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN3_CMOS:
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
6
LOCK_8K
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN3_CMOS:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
5 - 4
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN3_CMOS:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
3 - 0
IN_FREQ[3:0]
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN3_CMOS, the required frequency should not be set higher than that of the input clock.
Programming Information
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PRE_DIV_CH_CNFG - DivN Divider Channel Selection
Address: 23H
Type: Read / Write
Default Value: XXXX0000
7
-
6
-
5
-
4
-
3
2
1
0
PRE_DIV_CH_VALUE3 PRE_DIV_CH_VALUE2 PRE_DIV_CH_VALUE1 PRE_DIV_CH_VALUE0
Bit
Name
Description
7 - 4
-
Reserved.
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
3 - 0
PRE_DIV_CH_VALUE[3:0]
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Address: 24H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
PRE_DIVN_VA
LUE7
PRE_DIVN_VA
LUE6
PRE_DIVN_VA
LUE5
PRE_DIVN_VA
LUE4
PRE_DIVN_VA
LUE3
PRE_DIVN_VA
LUE2
PRE_DIVN_VA
LUE1
PRE_DIVN_VA
LUE0
Bit
Name
Description
7 - 0
PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
Programming Information
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PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Address: 25H
Type: Read / Write
Default Value: X0000000
7
-
6
5
4
3
2
1
0
PRE_DIVN_VAL PRE_DIVN_VAL PRE_DIVN_VAL PRE_DIVN_VAL PRE_DIVN_VAL PRE_DIVN_VAL PRE_DIVN_VAL
UE14
UE13
UE12
UE11
UE10
UE9
UE8
Bit
Name
Description
7
-
Reserved.
If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input
clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is lower than (<) 155.52 MHz.
6 - 0
PRE_DIVN_VALUE[14:8]
The division factor setting should observe the following order:
1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits.
Programming Information
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IDT82V3203B
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IN1_IN2_DIFF_SEL_PRIORITY_CNFG - Differential Input Clock 1 & 2 Priority Configuration
Address: 28H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
IN2_DIFF_SEL_ IN2_DIFF_SEL_ IN2_DIFF_SEL_ IN2_DIFF_SEL_ IN1_DIFF_SEL_ IN1_DIFF_SEL_ IN1_DIFF_SEL_ IN1_DIFF_SEL_
PRIORITY3
PRIORITY2
PRIORITY1
PRIORITY0
PRIORITY3
PRIORITY2
PRIORITY1
PRIORITY0
Bit
Name
Description
These bits set the priority of the corresponding IN2_DIFF.
0000: Disable IN2_DIFF for automatic selection. (default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
7 - 4
IN2_DIFF_SEL_PRIORITY[3:0] 0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
These bits set the priority of the corresponding IN1_DIFF.
0000: Disable IN1_DIFF for automatic selection. (default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
3 - 0
IN1_DIFF_SEL_PRIORITY[3:0] 0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15
Programming Information
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IN3_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 3 Priority Configuration
Address: 2AH
Type: Read / Write
Default Value: XXXX0100
7
-
6
-
5
-
4
-
3
2
1
0
IN3_CMOS_SE
L_PRIORITY3
IN3_CMOS_SE
L_PRIORITY2
IN3_CMOS_SE
L_PRIORITY1
IN3_CMOS_SE
L_PRIORITY0
Bit
7 - 4
Name
Description
-
Reserved.
These bits set the priority of the corresponding IN3_CMOS.
0000: Disable IN3_CMOS for automatic selection.
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4. (default)
0101: Priority 5.
0110: Priority 6.
3 - 0
IN3_CMOS_SEL_PRIORITY[3:0] 0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
Programming Information
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6.2.4
INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS
FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration
Address: 2EH
Type: Read / Write
Default Value: XXXX1011
7
-
6
-
5
-
4
-
3
2
1
0
FREQ_MON_F
ACTOR3
FREQ_MON_F
ACTOR2
FREQ_MON_F
ACTOR1
FREQ_MON_F
ACTOR0
Bit
7 - 4
Name
Description
-
Reserved.
These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to
the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input
clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)).
The factor represents the accuracy of the frequency monitor and should be set according to the requirements of differ-
ent applications.
0000: 0.0032.
0001: 0.0064.
0010: 0.0127.
0011: 0.0257.
0100: 0.0514.
0101: 0.103.
3 - 0
FREQ_MON_FACTOR[3:0]
0110: 0.206.
0111: 0.412.
1000: 0.823.
1001: 1.646.
1010: 3.292.
1011: 3.81. (default)
1100 - 1111: 4.6.
ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration
Address: 2FH
Type: Read / Write
Default Value: XXXX0011
7
-
6
-
5
-
4
-
3
2
1
0
ALL_FREQ_HARD_ ALL_FREQ_HARD_ ALL_FREQ_HARD_ ALL_FREQ_HARD_
THRESHOLD3 THRESHOLD2 THRESHOLD1 THRESHOLD0
Bit
Name
Description
7 - 4
-
Reserved.
These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as
follows:
3 - 0
ALL_FREQ_HARD_THRESHOLD[3:0]
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X
FREQ_MON_FACTOR[3:0] (b3~0, 2EH)
This threshold is symmetrical about zero.
Programming Information
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UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0
Address: 31H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_0_DAT
A7
UPPER_THRE
SHOLD_0_DAT
A6
UPPER_THRE
SHOLD_0_DAT
A5
UPPER_THRE
SHOLD_0_DAT
A4
UPPER_THRE
SHOLD_0_DAT
A3
UPPER_THRE
SHOLD_0_DAT
A2
UPPER_THRE
SHOLD_0_DAT
A1
UPPER_THRE
SHOLD_0_DAT
A0
Bit
Name
Description
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
7 - 0
UPPER_THRESHOLD_0_DATA[7:0]
LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0
Address: 32H
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_0_DAT
A7
LOWER_THRE
SHOLD_0_DAT
A6
LOWER_THRE
SHOLD_0_DAT
A5
LOWER_THRE
SHOLD_0_DAT
A4
LOWER_THRE
SHOLD_0_DAT
A3
LOWER_THRE
SHOLD_0_DAT
A2
LOWER_THRE
SHOLD_0_DAT
A1
LOWER_THRE
SHOLD_0_DAT
A0
Bit
Name
Description
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
7 - 0
LOWER_THRESHOLD_0_DATA[7:0]
BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0
Address: 33H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_0_DATA7
BUCKET_SIZE
_0_DATA6
BUCKET_SIZE
_0_DATA5
BUCKET_SIZE
_0_DATA4
BUCKET_SIZE
_0_DATA3
BUCKET_SIZE
_0_DATA2
BUCKET_SIZE
_0_DATA1
BUCKET_SIZE
_0_DATA0
Bit
Name
Description
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
7 - 0
BUCKET_SIZE_0_DATA[7:0]
Programming Information
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IDT82V3203B
EBU WAN PLL
DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0
Address: 34H
Type: Read / Write
Default Value: XXXXXX01
7
-
6
-
5
-
4
-
3
-
2
-
1
0
DECAY_RATE_ DECAY_RATE_
0_DATA1 0_DATA0
Bit
Name
Description
7 - 2
-
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
1 - 0
DECAY_RATE_0_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1
Address: 35H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_1_DAT
A7
UPPER_THRE
SHOLD_1_DAT
A6
UPPER_THRE
SHOLD_1_DAT
A5
UPPER_THRE
SHOLD_1_DAT
A4
UPPER_THRE
SHOLD_1_DAT
A3
UPPER_THRE
SHOLD_1_DAT
A2
UPPER_THRE
SHOLD_1_DAT
A1
UPPER_THRE
SHOLD_1_DAT
A0
Bit
Name
Description
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
7 - 0
UPPER_THRESHOLD_1_DATA[7:0]
LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1
Address: 36H
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_1_DAT
A7
LOWER_THRE
SHOLD_1_DAT
A6
LOWER_THRE
SHOLD_1_DAT
A5
LOWER_THRE
SHOLD_1_DAT
A4
LOWER_THRE
SHOLD_1_DAT
A3
LOWER_THRE
SHOLD_1_DAT
A2
LOWER_THRE
SHOLD_1_DAT
A1
LOWER_THRE
SHOLD_1_DAT
A0
Bit
Name
Description
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
7 - 0
LOWER_THRESHOLD_1_DATA[7:0]
Programming Information
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IDT82V3203B
EBU WAN PLL
BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1
Address: 37H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_1_DATA7
BUCKET_SIZE
_1_DATA6
BUCKET_SIZE
_1_DATA5
BUCKET_SIZE
_1_DATA4
BUCKET_SIZE
_1_DATA3
BUCKET_SIZE
_1_DATA2
BUCKET_SIZE
_1_DATA1
BUCKET_SIZE
_1_DATA0
Bit
Name
Description
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
7 - 0
BUCKET_SIZE_1_DATA[7:0]
DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1
Address: 38H
Type: Read / Write
Default Value: XXXXXX01
7
-
6
-
5
-
4
-
3
-
2
-
1
0
DECAY_RATE_
1_DATA1
DECAY_RATE_
1_DATA0
Bit
Name
Description
7 - 2
-
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
1 - 0
DECAY_RATE_1_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2
Address: 39H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_2_DAT
A7
UPPER_THRE
SHOLD_2_DAT
A6
UPPER_THRE
SHOLD_2_DAT
A5
UPPER_THRE
SHOLD_2_DAT
A4
UPPER_THRE
SHOLD_2_DAT
A3
UPPER_THRE
SHOLD_2_DAT
A2
UPPER_THRE
SHOLD_2_DAT
A1
UPPER_THRE
SHOLD_2_DAT
A0
Bit
Name
Description
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
7 - 0
UPPER_THRESHOLD_2_DATA[7:0]
Programming Information
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IDT82V3203B
EBU WAN PLL
LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2
Address: 3AH
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_2_DAT
A7
LOWER_THRE
SHOLD_2_DAT
A6
LOWER_THRE
SHOLD_2_DAT
A5
LOWER_THRE
SHOLD_2_DAT
A4
LOWER_THRE
SHOLD_2_DAT
A3
LOWER_THRE
SHOLD_2_DAT
A2
LOWER_THRE
SHOLD_2_DAT
A1
LOWER_THRE
SHOLD_2_DAT
A0
Bit
Name
Description
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is below this threshold, the no-activity alarm is cleared.
7 - 0
LOWER_THRESHOLD_2_DATA[7:0]
BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2
Address: 3BH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_2_DATA7
BUCKET_SIZE
_2_DATA6
BUCKET_SIZE
_2_DATA5
BUCKET_SIZE
_2_DATA4
BUCKET_SIZE
_2_DATA3
BUCKET_SIZE
_2_DATA2
BUCKET_SIZE
_2_DATA1
BUCKET_SIZE
_2_DATA0
Bit
Name
Description
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
7 - 0
BUCKET_SIZE_2_DATA[7:0]
DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2
Address: 3CH
Type: Read / Write
Default Value: XXXXXX01
7
-
6
-
5
-
4
-
3
-
2
-
1
0
DECAY_RATE_
2_DATA1
DECAY_RATE_
2_DATA0
Bit
Name
Description
7 - 2
-
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
1 - 0
DECAY_RATE_2_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
Programming Information
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IDT82V3203B
EBU WAN PLL
UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3
Address: 3DH
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_3_DAT
A7
UPPER_THRE
SHOLD_3_DAT
A6
UPPER_THRE
SHOLD_3_DAT
A5
UPPER_THRE
SHOLD_3_DAT
A4
UPPER_THRE
SHOLD_3_DAT
A3
UPPER_THRE
SHOLD_3_DAT
A2
UPPER_THRE
SHOLD_3_DAT
A1
UPPER_THRE
SHOLD_3_DAT
A0
Bit
Name
Description
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
7 - 0
UPPER_THRESHOLD_3_DATA[7:0]
LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3
Address: 3EH
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_3_DAT
A7
LOWER_THRE
SHOLD_3_DAT
A6
LOWER_THRE
SHOLD_3_DAT
A5
LOWER_THRE
SHOLD_3_DAT
A4
LOWER_THRE
SHOLD_3_DAT
A3
LOWER_THRE
SHOLD_3_DAT
A2
LOWER_THRE
SHOLD_3_DAT
A1
LOWER_THRE
SHOLD_3_DAT
A0
Bit
Name
Description
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is below this threshold, the no-activity alarm is cleared.
7 - 0
LOWER_THRESHOLD_3_DATA[7:0]
BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3
Address: 3FH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_3_DATA7
BUCKET_SIZE
_3_DATA6
BUCKET_SIZE
_3_DATA5
BUCKET_SIZE
_3_DATA4
BUCKET_SIZE
_3_DATA3
BUCKET_SIZE
_3_DATA2
BUCKET_SIZE
_3_DATA1
BUCKET_SIZE
_3_DATA0
Bit
Name
Description
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
7 - 0
BUCKET_SIZE_3_DATA[7:0]
Programming Information
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IDT82V3203B
EBU WAN PLL
DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3
Address: 40H
Type: Read / Write
Default Value: XXXXXX01
7
-
6
-
5
-
4
-
3
-
2
-
1
0
DECAY_RATE_
3_DATA1
DECAY_RATE_
3_DATA0
Bit
Name
Description
7 - 2
-
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
1 - 0
DECAY_RATE_3_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection
Address: 41H
Type: Read / Write
Default Value: XXXX0000
7
-
6
-
5
-
4
-
3
2
1
0
IN_FREQ_READ IN_FREQ_READ IN_FREQ_READ IN_FREQ_READ
_CH3
_CH2
_CH1
_CH0
Bit
Name
Description
7 - 4
3 - 0
-
Reserved.
These bits select an input clock, the frequency of which with respect to the reference clock can be read.
0000: Reserved. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
IN_FREQ_READ_CH[3:0]
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
IN_FREQ_READ_STS - Input Clock Frequency Read Value
Address: 42H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
IN_FREQ_VAL
UE7
IN_FREQ_VAL
UE6
IN_FREQ_VAL
UE5
IN_FREQ_VAL
UE4
IN_FREQ_VAL
UE3
IN_FREQ_VAL
UE2
IN_FREQ_VAL
UE1
IN_FREQ_VAL
UE0
Bit
Name
Description
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
7 - 0
IN_FREQ_VALUE[7:0]
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status
Address: 45H
Type: Read
Default Value: X110X110
7
-
6
5
4
3
-
2
1
0
IN2_DIFF_FREQ
_HARD_ALARM
IN2_DIFF_NO_A
CTIVITY_ALARM
IN2_DIFF_PH_L
OCK_ALARM
IN1_DIFF_FREQ
_HARD_ALARM
IN1_DIFF_NO_A
CTIVITY_ALARM
IN1_DIFF_PH_L
OCK_ALARM
Bit
Name
Description
7
-
Reserved.
This bit indicates whether IN2_DIFF is in frequency hard alarm status.
IN2_DIFF_FREQ_HARD_ALARM 0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN2_DIFF is in no-activity alarm status.
IN2_DIFF_NO_ACTIVITY_ALARM 0: No no-activity alarm.
6
5
1: In no-activity alarm status. (default)
This bit indicates whether IN2_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
4
IN2_DIFF_PH_LOCK_ALARM
-
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
3
2
Reserved.
This bit indicates whether IN1_DIFF is in frequency hard alarm status.
IN1_DIFF_FREQ_HARD_ALARM 0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN1_DIFF is in no-activity alarm status.
IN1_DIFF_NO_ACTIVITY_ALARM 0: No no-activity alarm.
1
0
1: In no-activity alarm status. (default)
This bit indicates whether IN1_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
IN1_DIFF_PH_LOCK_ALARM
Programming Information
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IDT82V3203B
EBU WAN PLL
IN3_CMOS_STS - CMOS Input Clock 3 Status
Address: 47H
Type: Read
Default Value:XXXXX110
7
-
6
-
5
-
4
-
3
-
2
1
0
IN3_CMOS_FRE
Q_HARD_ALAR
M
IN3_CMOS_NO_
ACTIVITY_ALAR
M
IN3_CMOS_PH_
LOCK_ALARM
Bit
Name
Description
7 - 3
-
Reserved.
This bit indicates whether IN3_CMOS is in frequency hard alarm status.
IN3_CMOS_FREQ_HARD_ALARM 0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN3_CMOS is in no-activity alarm status.
IN3_CMOS_NO_ACTIVITY_ALARM 0: No no-activity alarm.
2
1
0
1: In no-activity alarm status. (default)
This bit indicates whether IN3_CMOS is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
IN3_CMOS_PH_LOCK_ALARM
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
6.2.5
T0 DPLL INPUT CLOCK SELECTION REGISTERS
INPUT_VALID1_STS - Input Clocks Validity 1
Address: 4AH
Type: Read
Default Value: XX00XXXX
7
-
6
-
5
4
3
-
2
-
1
-
0
-
IN2_DIFF
IN1_DIFF
Bit
Name
Description
7 - 6
-
Reserved.
This bit indicates the validity of the corresponding INn_DIFF. Here n is 2 or 1.
5 - 4
3 - 0
INn_DIFF
-
0: Invalid. (default)
1: Valid.
Reserved.
INPUT_VALID2_STS - Input Clocks Validity 2
Address: 4BH
Type: Read
Default Value: XXXXXXX0
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
IN3_CMOS
Bit
Name
Description
7 - 1
-
Reserved.
This bit indicates the validity of the corresponding IN3_CMOS.
0
IN3_CMOS 0: Invalid. (default)
1: Valid.
Programming Information
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IDT82V3203B
EBU WAN PLL
PRIORITY_TABLE1_STS - Priority Status 1
Address: 4EH
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
HIGHEST_PRI
ORITY_VALIDA
TED3
HIGHEST_PRI
ORITY_VALIDA ORITY_VALIDA
TED2 TED1
HIGHEST_PRI
HIGHEST_PRI
ORITY_VALIDA
TED0
CURRENTLY_S CURRENTLY_S CURRENTLY_S CURRENTLY_S
ELECTED_INP
UT3
ELECTED_INP
UT2
ELECTED_INP
UT1
ELECTED_INP
UT0
Bit
Name
Description
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
7 - 4
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
1010 ~ 1111: Reserved.
These bits indicate the T0 selected input clock.
0000: No input clock is selected. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
3 - 0
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
PRIORITY_TABLE2_STS - Priority Status 2
Address: 4FH
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
THIRD_HIGHE
THIRD_HIGHE
THIRD_HIGHE
THIRD_HIGHE
SECOND_HIGH SECOND_HIGH SECOND_HIGH SECOND_HIGH
ST_PRIORITY_ ST_PRIORITY_ ST_PRIORITY_ ST_PRIORITY_ EST_PRIORITY EST_PRIORITY EST_PRIORITY EST_PRIORITY
VALIDATED3
VALIDATED2
VALIDATED1
VALIDATED0
_VALIDATED3
_VALIDATED2
_VALIDATED1
_VALIDATED0
Bit
Name
Description
These bits indicate a qualified input clock with the third highest priority.
0000: No input clock is qualified. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
0110: IN2_DIFF.
7 - 4
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001 ~ 0100: Reserved.
0101: IN1_DIFF.
0110: IN2_DIFF.
3 - 0
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Address: 50H
Type: Read / Write
Default Value: XXXX0000
7
-
6
-
5
-
4
-
3
2
1
0
T0_INPUT_SEL3 T0_INPUT_SEL2 T0_INPUT_SEL1 T0_INPUT_SEL0
Bit
Name
Description
7 - 4
-
Reserved.
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001 ~ 0100: Reserved.
0101: Forced selection - IN1_DIFF. is selected
0110: Forced selection - IN2_DIFF. is selected
0111, 1000: Reserved.
3 - 0
T0_INPUT_SEL[3:0]
1001: Forced selection - IN3_CMOS is selected.
1010 ~ 1111: Reserved.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
6.2.6
T0 DPLL STATE MACHINE CONTROL REGISTERS
OPERATING_STS - DPLL Operating Status
Address: 52H
Type: Read
Default Value: 1X0X0001
7
6
-
5
4
-
3
2
1
0
EX_SYNC_ALA
RM_MON
T0_DPLL_SOFT
_FREQ_ALARM
T0_DPLL_LO
CK
T0_DPLL_OPER T0_DPLL_OPER T0_DPLL_OPER
ATING_MODE2
ATING_MODE1
ATING_MODE0
Bit
Name
Description
This bit indicates whether the selected frame sync input signal is in external sync alarm status.
0: No external sync alarm.
1: In external sync alarm status. (default)
7
6
EX_SYNC_ALARM_MON
-
Reserved.
This bit indicates whether the T0 DPLL is in soft alarm status.
5
4
3
T0_DPLL_SOFT_FREQ_ALARM 0: No T0 DPLL soft alarm. (default)
1: In T0 DPLL soft alarm status.
-
Reserved.
This bit indicates the T0 DPLL locking status.
0: Unlocked. (default)
T0_DPLL_LOCK
1: Locked.
These bits indicate the current operating mode of T0 DPLL.
000: Reserved.
001: Free-Run. (default)
010: Holdover.
2 - 0
T0_DPLL_OPERATING_MODE[2:0] 011: Reserved.
100: Locked.
101: Pre-Locked2.
110: Pre-Locked.
111: Lost-Phase.
Programming Information
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IDT82V3203B
EBU WAN PLL
T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration
Address: 53H
Type: Read / Write
Default Value: XXXXX000
7
-
6
-
5
-
4
-
3
-
2
1
0
T0_OPERATING_MODE2 T0_OPERATING_MODE1 T0_OPERATING_MODE0
Bit
Name
Description
7 - 3
-
Reserved.
These bits control the T0 DPLL operating mode.
000: Automatic. (default)
001: Forced - Free-Run.
010: Forced - Holdover.
2 - 0
T0_OPERATING_MODE[2:0] 011: Reserved.
100: Forced - Locked.
101: Forced - Pre-Locked2.
110: Forced - Pre-Locked.
111: Forced - Lost-Phase.
Programming Information
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6.2.7
T0 DPLL & T0/T4 APLL CONFIGURATION REGISTERS
T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration
Address: 55H
Type: Read / Write
Default Value: 00000X0X
7
6
5
4
3
2
1
0
T0_APLL_PATH T0_APLL_PA
TH2
T0_APLL_PA
TH1
T0_APLL_PA
TH0
T0_GSM_OBSAI_
16E1_16T1_SEL1
T0_GSM_OBSAI_
16E1_16T1_SEL0
T0_12E1_24T1_
E3_T3_SEL1
T0_12E1_24T1_
E3_T3_SEL0
3
Bit
Name
Description
These bits select an input to the T0 APLL.
0000: The output of T0 DPLL 77.76 MHz path. (default)
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
0100 ~ 1111: Reserved.
7 - 4
T0_APLL_PATH[3:0]
These bits select an output clock from the T0 DPLL GSM/OBSAI/16E1/16T1 path.
00: 16E1.
01: 16T1.
3 - 2
T0_GSM_OBSAI_16E1_16T1_SEL[1:0] 10: GSM.
11: OBSAI.
The default value of the T0_GSM_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin dur-
ing reset.
These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path.
00: 12E1.
01: 24T1.
1 - 0
T0_12E1_24T1_E3_T3_SEL[1:0]
10: E3.
11: T3.
The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during
reset.
Programming Information
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IDT82V3203B
EBU WAN PLL
T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration
Address: 56H
Type: Read / Write
Default Value: 01101111
7
6
5
4
3
2
1
0
T0_DPLL_STA
RT_DAMPING2
T0_DPLL_STA
RT_DAMPING1
T0_DPLL_STA
RT_DAMPING0
T0_DPLL_STA
RT_BW4
T0_DPLL_STA
RT_BW3
T0_DPLL_STA
RT_BW2
T0_DPLL_STA
RT_BW1
T0_DPLL_STA
RT_BW0
Bit
Name
Description
These bits set the starting damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
7 - 5
T0_DPLL_START_DAMPING[2:0]
101: 20.
110, 111: Reserved.
These bits set the starting bandwidth for T0 DPLL.
00XXX: Reserved.
01000: 0.1 Hz.
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
4 - 0
T0_DPLL_START_BW[4:0]
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration
Address: 57H
Type: Read / Write
Default Value: 01101111
7
6
5
4
3
2
1
0
T0_DPLL_ACQ
_DAMPING2
T0_DPLL_ACQ
_DAMPING1
T0_DPLL_ACQ
_DAMPING0
T0_DPLL_ACQ
_BW4
T0_DPLL_ACQ
_BW3
T0_DPLL_ACQ
_BW2
T0_DPLL_ACQ
_BW1
T0_DPLL_ACQ
_BW0
Bit
Name
Description
These bits set the acquisition damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
7 - 5
T0_DPLL_ACQ_DAMPING[2:0]
101: 20.
110, 111: Reserved.
These bits set the acquisition bandwidth for T0 DPLL.
00XXX: Reserved.
01000: 0.1 Hz.
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
4 - 0
T0_DPLL_ACQ_BW[4:0]
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration
Address: 58H
Type: Read / Write
Default Value: 01101111
7
6
5
4
3
2
1
0
T0_DPLL_LOCK T0_DPLL_LOCK T0_DPLL_LOCK
T0_DPLL_LOC
KED_BW4
T0_DPLL_LOC
KED_BW3
T0_DPLL_LOC
KED_BW2
T0_DPLL_LOC
KED_BW1
T0_DPLL_LOC
KED_BW0
ED_DAMPING2
ED_DAMPING1
ED_DAMPING0
Bit
Name
Description
These bits set the locked damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
7 - 5
T0_DPLL_LOCKED_DAMPING[2:0]
101: 20.
110, 111: Reserved.
These bits set the locked bandwidth for T0 DPLL.
00XXX: Reserved.
01000: 0.1 Hz.
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz. (default)
01100: 2.5 Hz.
01101: 4 Hz.
4 - 0
T0_DPLL_LOCKED_BW[4:0]
01110: 8 Hz.
01111: 18 Hz.
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
7
6
-
5
-
4
-
3
2
-
1
-
0
-
AUTO_BW_SEL
T0_LIMT
Bit
Name
Description
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
AUTO_BW_SEL regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
7
stages. (default)
6 - 4
3
-
Reserved.
This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
T0_LIMT
-
2 - 0
Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration
Address: 5AH
Type: Read / Write
Default Value: 10000101
7
6
5
4
3
2
1
0
COARSE_PH_L
OS_LIMT_EN
MULTI_PH_8K_
4K_2K_EN
PH_LOS_COA
RSE_LIMT3
PH_LOS_COA
RSE_LIMT2
PH_LOS_COA
RSE_LIMT1
PH_LOS_COA
RSE_LIMT0
WIDE_EN
MULTI_PH_APP
Bit
Name
Description
This bit controls whether the occurrence of the coarse phase loss will result in the T0 DPLL unlocked.
COARSE_PH_LOS_LIMT_EN 0: Disabled.
1: Enabled. (default)
Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
7
6
WIDE_EN
This bit determines whether the PFD output of T0 DPLL is limited to ±1 UI or is limited to the coarse phase limit.
0: Limited to ±1 UI. (default)
1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends
on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input
clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the
PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details.
5
MULTI_PH_APP
This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the
coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequen-
cies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0]
bits.
Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN
Coarse Phase Limit
0
don’t-care
0
±1 UI
±1 UI
4
MULTI_PH_8K_4K_2K_EN
2 kHz, 4 kHz or 8 kHz
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
1
0
1
±1 UI
other than 2 kHz, 4
kHz and 8 kHz
don’t-care
set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the
MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
0000: ±1 UI.
0001: ±3 UI.
0010: ±7 UI.
0011: ±15 UI.
3 - 0 PH_LOS_COARSE_LIMT[3:0] 0100: ±31 UI.
0101: ±63 UI. (default)
0110: ±127 UI.
0111: ±255 UI.
1000: ±511 UI.
1001: ±1023 UI.
1010-1111: Reserved.
Programming Information
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IDT82V3203B
EBU WAN PLL
PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration
Address: 5BH
Type: Read / Write
Default Value: 10XXX010
7
6
5
-
4
-
3
-
2
1
0
FINE_PH_LOS_
LIMT_EN
PH_LOS_FINE
_LIMT2
PH_LOS_FINE
_LIMT1
PH_LOS_FINE
_LIMT0
FAST_LOS_SW
Bit
Name
Description
This bit controls whether the occurrence of the fine phase loss will result in the T0 DPLL unlocked.
FINE_PH_LOS_LIMT_EN 0: Disabled.
1: Enabled. (default)
This bit controls whether the occurrence of the fast loss will result in the T0 DPLL unlocked.
7
0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default)
1: Results in the T0 DPLL unlocked. T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating mode is switched
automatically.
6
FAST_LOS_SW
5 - 3
-
Reserved.
These bits set a fine phase limit.
000: 0.
001: ± (45 ° ~ 90 °).
010: ± (90 ° ~ 180 °). (default)
2 - 0
PH_LOS_FINE_LIMT[2:0] 011: ± (180 ° ~ 360 °).
100: ± (20 ns ~ 25 ns).
101: ± (60 ns ~ 65 ns).
110: ± (120 ns ~ 125 ns).
111: ± (950 ns ~ 955 ns).
Programming Information
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EBU WAN PLL
T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration
Address: 5CH
Type: Read / Write
Default Value: 010001XX
7
6
5
4
3
2
1
-
0
-
MAN_HOLDOV
ER
TEMP_HOLDO
VER_MODE1
TEMP_HOLDO
VER_MODE0
AUTO_AVG
FAST_AVG
READ_AVG
Bit
Name
Description
7
6
MAN_HOLDOVER
AUTO_AVG
Refer to the description of the FAST_AVG bit (b5, 5CH).
Refer to the description of the FAST_AVG bit (b5, 5CH).
This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a fre-
quency offset acquiring method in T0 DPLL Holdover Mode.
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
5
4
FAST_AVG
READ_AVG
0
don’t-care
Automatic Instantaneous
Automatic Slow Averaged (default)
Automatic Fast Averaged
Manual
0
1
0
1
1
don’t-care
This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits
(5FH ~ 5DH).
0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them.
(default)
1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them.
The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is ‘0’; or is acquired by
Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’.
These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode.
00: The method is the same as that used in T0 DPLL Holdover mode.
3 - 2
1 - 0
TEMP_HOLDOVER_MODE[1:0] 01: Automatic Instantaneous. (default)
10: Automatic Fast Averaged.
11: Automatic Slow Averaged.
-
Reserved.
T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1
Address: 5DH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER
T0_HOLDOVE
R_FREQ4
T0_HOLDOVE
R_FREQ3
T0_HOLDOVE
R_FREQ2
T0_HOLDOVE
R_FREQ1
T0_HOLDOVE
R_FREQ0
_FREQ7
_FREQ6
_FREQ5
Bit
Name
Description
7 - 0
T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
Programming Information
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IDT82V3203B
EBU WAN PLL
T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2
Address: 5EH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER
T0_HOLDOVE
R_FREQ12
T0_HOLDOVE
R_FREQ11
T0_HOLDOVE
R_FREQ10
T0_HOLDOVE
R_FREQ9
T0_HOLDOVE
R_FREQ8
_FREQ15
_FREQ14
_FREQ13
Bit
Name
Description
7 - 0
T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3
Address: 5FH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER
T0_HOLDOVE
R_FREQ20
T0_HOLDOVE
R_FREQ19
T0_HOLDOVE
R_FREQ18
T0_HOLDOVE
R_FREQ17
T0_HOLDOVE
R_FREQ16
_FREQ23
_FREQ22
_FREQ21
Bit
Name
Description
The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer.
In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu-
ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast aver-
aged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH).
7 - 0
T0_HOLDOVER_FREQ[23:16]
T4_APLL_PATH_CNFG - T4 APLL Path Configuration
Address: 60H
Type: Read / Write
Default Value: 0100XXXX
7
6
5
4
3
-
2
-
1
-
0
-
T4_APLL_PATH T4_APLL_PA
TH2
T4_APLL_PA
TH1
T4_APLL_PA
TH0
3
Bit
Name
Description
These bits select an input to the T4 APLL.
0000: The output of T0 DPLL 77.76 MHz path.
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
0100 ~ 1111: Reserved.
7 - 4
3 - 0
T4_APLL_PATH[3:0]
-
Reserved.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1
Address: 62H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ7
CURRENT_DP
LL_FREQ6
CURRENT_DP
LL_FREQ5
CURRENT_DP
LL_FREQ4
CURRENT_DP
LL_FREQ3
CURRENT_DP
LL_FREQ2
CURRENT_DP
LL_FREQ1
CURRENT_DP
LL_FREQ0
Bit
Name
Description
7 - 0
CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2
Address: 63H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ15
CURRENT_DP
LL_FREQ14
CURRENT_DP
LL_FREQ13
CURRENT_DP
LL_FREQ12
CURRENT_DP
LL_FREQ11
CURRENT_DP
LL_FREQ10
CURRENT_DP
LL_FREQ9
CURRENT_DP
LL_FREQ8
Bit
Name
Description
7 - 0
CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3
Address: 64H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ23
CURRENT_DP
LL_FREQ22
CURRENT_DP
LL_FREQ21
CURRENT_DP
LL_FREQ20
CURRENT_DP
LL_FREQ19
CURRENT_DP
LL_FREQ18
CURRENT_DP
LL_FREQ17
CURRENT_DP
LL_FREQ16
Bit
Name
Description
The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mul-
7 - 0
CURRENT_DPLL_FREQ[23:16] tiplied by 0.000011, the current frequency offset of the T0 DPLL output in ppm with respect to the master clock will
be gotten.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration
Address: 65H
Type: Read / Write
Default Value: 10001100
7
6
5
4
3
2
1
0
FREQ_LIMT_P
H_LOS
DPLL_FREQ_S
OFT_LIMT6
DPLL_FREQ_S
OFT_LIMT5
DPLL_FREQ_S DPLL_FREQ_S DPLL_FREQ_S DPLL_FREQ_S DPLL_FREQ_S
OFT_LIMT4 OFT_LIMT3 OFT_LIMT2 OFT_LIMT1 OFT_LIMT0
Bit
Name
Description
This bit determines whether the T0 DPLL in hard alarm status will result in it unlocked.
7
FREQ_LIMT_PH_LOS
0: Disabled.
1: Enabled. (default)
These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 path in ppm will
DPLL_FREQ_SOFT_LIMT[6:0] be gotten.
The DPLL soft limit is symmetrical about zero.
6 - 0
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
Address: 66H
Type: Read / Write
Default Value: 10101011
7
6
5
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT7
DPLL_FREQ_H
ARD_LIMT6
DPLL_FREQ_H
ARD_LIMT5
DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H
ARD_LIMT4 ARD_LIMT3 ARD_LIMT2 ARD_LIMT1 ARD_LIMT0
Bit
Name
Description
7 - 0
DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
Address: 67H
Type: Read / Write
Default Value: 00011001
7
6
5
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT15
DPLL_FREQ_H
ARD_LIMT14
DPLL_FREQ_H
ARD_LIMT13
DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H DPLL_FREQ_H
ARD_LIMT12 ARD_LIMT11 ARD_LIMT10 ARD_LIMT9 ARD_LIMT8
Bit
Name
Description
The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the
7 - 0
DPLL_FREQ_HARD_LIMT[15:8] DPLL hard limit for T0 path in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1
Address: 68H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_PH
_DATA7
CURRENT_PH
_DATA6
CURRENT_PH
_DATA5
CURRENT_PH
_DATA4
CURRENT_PH
_DATA3
CURRENT_PH
_DATA2
CURRENT_PH
_DATA1
CURRENT_PH
_DATA0
Bit
Name
Description
7 - 0
CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2
Address: 69H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_PH
_DATA15
CURRENT_PH
_DATA14
CURRENT_PH
_DATA13
CURRENT_PH
_DATA12
CURRENT_PH
_DATA11
CURRENT_PH
_DATA10
CURRENT_PH
_DATA9
CURRENT_PH
_DATA8
Bit
Name
Description
The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
averaged phase error of the T0 DPLL feedback with respect to the selected input clock in ns will be gotten.
7 - 0
CURRENT_PH_DATA[15:8]
T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration
Address: 6AH
Type: Read / Write
Default Value: XX01XX01
7
-
6
-
5
4
3
-
2
-
1
0
T0_APLL_BW1
T0_APLL_BW0
T4_APLL_BW1
T4_APLL_BW0
Bit
Name
Description
7 - 6
5 - 4
3 - 2
1 - 0
-
Reserved.
These bits set the bandwidth for T0 APLL.
00: 100 kHz.
T0_APLL_BW[1:0] 01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
-
Reserved.
These bits set the bandwidth for T4 APLL.
00: 100 kHz.
T4_APLL_BW[1:0] 01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
Programming Information
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6.2.8
OUTPUT CONFIGURATION REGISTERS
OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration
Address: 6DH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
OUT2_PATH_S
EL3
OUT2_PATH_S
EL2
OUT2_PATH_S
EL1
OUT2_PATH_S OUT2_DIVIDER OUT2_DIVIDER OUT2_DIVIDER OUT2_DIVIDER
EL0
3
2
1
0
Bit
Name
Description
These bits select an input to OUT2.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
7 - 4
OUT2_PATH_SEL[3:0]
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
These bits select a division factor of the divider for OUT2.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
3 - 0
OUT2_DIVIDER[3:0] (selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0 DPLL outputs, please
refer to Table 22 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 23 for the division factor selection.
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
Address:71H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
OUT1_PATH_S
EL3
OUT1_PATH_S
EL2
OUT1_PATH_S
EL1
OUT1_PATH_S OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER
EL0
3
2
1
0
Bit
Name
Description
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
7 - 4
OUT1_PATH_SEL[3:0]
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
3 - 0
OUT1_DIVIDER[3:0] (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0 DPLL outputs, please
refer to Table 22 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 23 for the division factor selection.
Programming Information
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EBU WAN PLL
OUT1_INV_CNFG - Output Clock 1 Invert Configuration
Address:72H
Type: Read / Write
Default Value: XXXXXX0X
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
OUT1_INV
Bit
Name
Description
7 - 2
-
Reserved.
This bit determines whether the output on OUT1 is inverted.
0: Not inverted. (default)
1: Inverted.
1
0
OUT1_INV
-
Reserved.
OUT2_INV_CNFG - Output Clock 2 Invert Configuration
Address:73H
Type: Read / Write
Default Value: XXXXX0XX
7
-
6
-
5
-
4
-
3
-
2
1
-
0
-
OUT2_INV
Bit
Name
Description
7 - 3
-
Reserved.
This bit determines whether the output on OUT2 is inverted.
0: Not inverted. (default)
1: Inverted.
2
OUT2_INV
-
1 - 0
Reserved.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration
Address:74H
Type: Read / Write
Default Value: 01100000
7
6
5
4
3
2
1
0
IN_2K_4K_8K_I
NV
2K_8K_PUL_P
OSITION
8K_EN
2K_EN
8K_INV
8K_PUL
2K_INV
2K_PUL
Bit
Name
Description
This bit determines whether the input clock is inverted before locked by the T0 DPLL when the input clock is 2 kHz, 4 kHz
or 8 kHz.
0: Not inverted. (default)
1: Inverted.
7
IN_2K_4K_8K_INV
This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K.
0: Disabled. FRSYNC_8K outputs low.
1: Enabled. (default)
6
5
8K_EN
2K_EN
Reserved.
This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H)
and the 2K_PUL bit (b0, 74H) is ‘1’ or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both ‘1’. It deter-
4
2K_8K_PUL_POSITION mines the pulse position referring to the standard 50:50 duty cycle.
0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default)
1: Pulsed on the rising edge of the standard 50:50 duty cycle position.
This bit determines whether the output on FRSYNC_8K is inverted.
3
2
1
0
8K_INV
8K_PUL
2K_INV
2K_PUL
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed.
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT2.
This bit determines whether the output on MFRSYNC_2K is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed.
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT2.
Programming Information
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IDT82V3203B
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6.2.9
PBO & PHASE OFFSET CONTROL REGISTERS
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
Address:78H
Type: Read / Write
Default Value: 0X000110
7
6
-
5
4
3
2
1
0
IN_NOISE_WIN
DOW
PH_MON_PBO PH_TR_MON_L PH_TR_MON_L PH_TR_MON_L PH_TR_MON_L
_EN IMT3 IMT2 IMT1 IMT0
PH_MON_EN
Bit
Name
Description
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be
selected for T0 DPLL.
0: Disabled. (default)
1: Enabled.
7
6
5
IN_NOISE_WINDOW
-
Reserved.
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
is enabled to monitor the phase-time changes on the T0 selected input clock.
0: Disabled. (default)
1: Enabled.
PH_MON_EN
This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
4
PH_MON_PBO_EN is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
3 - 0
PH_TR_MON_LIMT[3:0]
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.
Programming Information
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IDT82V3203B
EBU WAN PLL
6.2.10
SYNCHRONIZATION CONFIGURATION REGISTERS
SYNC_MONITOR_CNFG - Sync Monitor Configuration
Address:7CH
Type: Read / Write
Default Value: 00101011
7
6
5
4
3
-
2
-
1
-
0
-
SYNC_BYPASS
SYNC_MON_LIMT2 SYNC_MON_LIMT1 SYNC_MON_LIMT0
Bit
Name
Description
This bit selects one frame sync input signal to synchronize the frame sync output signals.
0: EX_SYNC1 is selected. (default)
7
SYNC_BYPASS
1: When the T0 selected input clock is IN1_DIFF, EX_SYNC1 is selected; when the T0 selected input clock is IN2_DIFF,
EX_SYNC2 is selected; when the T0 selected input clock is IN3_CMOS, EX_SYNC3 is selected; when there is no T0
selected input clock, no frame sync input signal is selected.
These bits set the limit for the external sync alarm.
000: ±1 UI.
001: ±2 UI.
010: ±3 UI. (default)
6 - 4
3 - 0
SYNC_MON_LIMT[2:0] 011: ±4 UI.
100: ±5 UI.
101: ±6 UI.
110: ±7 UI.
111: ±8 UI.
-
These bits must be set to ‘1011’.
Programming Information
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IDT82V3203B
EBU WAN PLL
SYNC_PHASE_CNFG - Sync Phase Configuration
Address:7DH
Type: Read / Write
Default Value: XX000000
7
-
6
-
5
4
3
2
1
0
SYNC_PH31
SYNC_PH30
SYNC_PH21
SYNC_PH20
SYNC_PH11
SYNC_PH10
Bit
Name
Description
7 - 6
-
Reserved.
These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
5 - 4
SYNC_PH3[1:0]
SYNC_PH2[1:0]
SYNC_PH1[1:0]
11: 0.5 UI late.
These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
3 - 2
11: 0.5 UI late.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
1 - 0
11: 0.5 UI late.
Programming Information
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August 21, 2007
IDT82V3203B
EBU WAN PLL
7
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATING
7.1
Table 32: Absolute Maximum Rating
Symbol
VDD
Parameter
Min
Max
4.0
Unit
V
Supply Voltage VDD
-0.5
VIN
Input Voltage (non-supply pins)
Output Voltage (non-supply pins)
Storage Temperature
5.5
V
VOUT
TSTOR
5.5
V
-50
+150
°C
7.2
RECOMMENDED OPERATION CONDITIONS
Table 33: Recommended Operation Conditions
Symbol
VDD
Parameter
Min
3.0
-40
Typ
Max
Unit
V
Power Supply (DC voltage) VDD
Ambient Temperature Range
Supply Current
3.3
3.6
+85
262
0.94
TA
°C
mA
W
IDD
233
PTOT
Total Power Dissipation
0.77
Electrical Specifications
99
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IDT82V3203B
EBU WAN PLL
7.3
I/O SPECIFICATIONS
7.3.1
CMOS INPUT / OUTPUT PORT
Table 34: CMOS Input Port Electrical Characteristics
Parameter
Description
Min
Typ
Max
Unit
Test Condition
VIH
VIL
IIN
Input Voltage High
Input Voltage Low
Input Current
2.0
V
V
0.8
10
µA
V
VIN
Input Voltage
-0.5
5.5
Table 35: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics
Parameter
VIH
Description
Min
Typ
Max
Unit
Test Condition
Input Voltage High
Input Voltage Low
2.0
V
V
VIL
0.8
38
82
23
41
TDI, TMS pin
RST pin
PU
Pull-Up Resistor
82
85
40
20
165
140
80
KΩ
TDI, TMS pin
RST pin
IIN
Input Current
Input Voltage
40
µA
VIN
-0.5
5.5
V
Table 36: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics
Parameter
VIH
Description
Min
Typ
Max
Unit
Test Condition
Input Voltage High
Input Voltage Low
2.0
V
V
VIL
0.8
14
8
TRST and TCK pin
16
23
other CMOS input port with internal pull-down resistor
SDI, CLKE pin
PD
Pull-Down Resistor
183
390
180
15
366
640
340
30
KΩ
TRST and TCK pin
other CMOS input port with internal pull-down resistor
SDI, CLKE pin
IIN
Input Current
Input Voltage
µA
VIN
-0.5
5.5
V
Electrical Specifications
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IDT82V3203B
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Table 37: CMOS Output Port Electrical Characteristics
Application Pin
Parameter
Description
Min
2.4
0
Typ
Max
Unit
V
Test Condition
VOH
VOL
tR
VDD
IOH = 8 mA
Output Voltage High
Output Voltage Low
Rise time (20% to 80%)
Fall time (20% to 80%)
Output Voltage High
Output Voltage Low
Rise Time (20% to 80%)
Fall Time (20% to 80%)
I
OL = 8 mA
15 pF
0.4
0.4
V
Output Clock
0.3
0.3
ns
ns
V
tF
0.4
15 pF
VOH
VOL
tR
VDD
IOH = 4 mA
IOL= 4 mA
50 pF
2.4
0
0.4
10
10
V
Other Output
ns
ns
tF
50 pF
Electrical Specifications
101
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IDT82V3203B
EBU WAN PLL
7.3.2
PECL / LVDS INPUT / OUTPUT PORT
PECL Input / Output Port
130 Ω 82 Ω
7.3.2.1
VDD (+ 3.3 V)
GND
50 Ω (transmission line)
2 kHz
to
667 MHz
OUT1_POS
OUT1_NEG
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
50 Ω (transmission line)
VDD (+ 3.3 V)
GND
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
82 Ω
130 Ω
82 Ω
2 kHz
to
667 MHz
GND
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
Figure 19. Recommended PECL Output Port Line Ter-
mination
82 Ω
GND
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
82 Ω
GND
2 kHz
to
667 MHz
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
82 Ω
GND
Figure 18. Recommended PECL Input Port Line Termi-
nation
Electrical Specifications
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IDT82V3203B
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Table 38: PECL Input / Output Port Electrical Characteristics
Parameter
VIL
Description
Min
Typ
Max
Unit
Test Condition
Input Low Voltage, Differential Inputs 1
Input High Voltage, Differential Inputs 1
Input Differential Voltage
VDD - 2.5
VDD - 2.4
VDD - 0.5
VDD - 0.4
V
V
VIH
VID
0.1
1.4
V
Input Low Voltage, Single-ended Input 2
Input High Voltage, Single-ended Input 2
VIL_S
VIH_S
IIH
VDD - 2.4
VDD - 1.3
VDD - 1.5
VDD - 0.5
V
V
Input High Current, Input Differential Voltage VID = 1.4 V
-10
-10
10
µA
µA
V
IIL
Input Low Current, Input Differential Voltage VID = 1.4 V
10
Output Voltage Low 3
Output Voltage High 3
Output Differential Voltage3
Output Rise time (20% to 80%)
Output Fall time (20% to 80%)
Output Differential Skew
VOL
VDD - 2.1
VDD - 1.25
VDD - 1.62
VDD - 0.88
VOH
VOD
tRISE
tFALL
tSKEW
V
580
200
200
900
300
300
50
mV
pS
pS
pS
Note:
1. Assuming a differential input voltage of at least 100 mV.
2. Unused differential input terminated to VDD-1.4 V.
3. With 50 Ω load on each pin to VDD-2 V, i.e. 82 to GND and 130 to VDD
.
Electrical Specifications
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August 21, 2007
IDT82V3203B
7.3.2.2 LVDS Input / Output Port
EBU WAN PLL
50 Ω (transmission line)
100 Ω
OUT1_POS
OUT1_NEG
2 kHz
to
667 MHz
50 Ω (transmission line)
100 Ω
IN1_POS
IN1_NEG
2 kHz
to
667 MHz
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
100 Ω
IN2_POS
IN2_NEG
2 kHz
to
Figure 21. Recommended LVDS Output Port Line Ter-
mination
667 MHz
50 Ω (transmission line)
Figure 20. Recommended LVDS Input Port Line Termi-
nation
Table 39: LVDS Input / Output Port Electrical Characteristics
Parameter
VCM
Description
Min
0
Typ
Max
2400
900
100
105
1475
1100
400
1275
120
20
Unit
mV
mV
mV
Ω
Test Condition
Input Common-mode Voltage Range
Input Peak Differential Voltage
Input Differential Threshold
1200
VDIFF
VIDTH
RTERM
VOH
100
-100
95
External Differential Termination Impedance
Output Voltage High
100
100
R
LOAD = 100 Ω ± 1%
1350
925
250
1125
80
mV
mV
mV
mV
Ω
VOL
RLOAD = 100 Ω ± 1%
Output Voltage Low
VOD
R
R
LOAD = 100 Ω ± 1%
LOAD = 100 Ω ± 1%
Differential Output Voltage
VOS
Output Offset Voltage
RO
VCM = 1.0 V or 1.4 V
Differential Output Impedance
RO Mismatch between A and B
Change in VOD between Logic 0 and Logic 1
Change in VOS between Logic 0 and Logic 1
∆RO
VCM = 1.0 V or 1.4 V
RLOAD = 100 Ω ± 1%
RLOAD = 100 Ω ± 1%
Driver shorted to GND
Driver shorted together
%
∆VOD
∆VOS
ISA, ISB
ISAB
25
mV
mV
mA
mA
pS
25
Output Current
Output Current
24
12
tRISE
R
R
LOAD = 100 Ω ± 1%
LOAD = 100 Ω ± 1%
Output Rise time (20% to 80%)
Output Fall time (20% to 80%)
Output Differential Skew
200
200
300
300
50
tFALL
pS
tSKEW
RLOAD = 100 Ω ± 1%
pS
Electrical Specifications
104
August 21, 2007
IDT82V3203B
EBU WAN PLL
7.4
JITTER & WANDER PERFORMANCE
Table 40: Output Clock Jitter Generation
Peak to Peak
Typ
RMS
Typ
Test Definition 1
Note
Test Filter
N x 2.048MHz without APLL
N x 2.048MHz with T0/T4 APLL
N x 1.544 MHz without APLL
N x 1.544 MHz with T0/T4 APLL
44.736 MHz without APLL
<2 ns
<1 ns
<2 ns
<1 ns
<1 ns
<2 ns
<1 ns
<2 ns
<200 ps
<100 ps
<200 ps
<100 ps
<100 ps
<200 ps
<100 ps
<200 ps
20 Hz - 100 kHz
See Table 41: Output Clock Phase Noise for details 20 Hz - 100 kHz
10 Hz - 40 kHz
See Table 41: Output Clock Phase Noise for details
10 Hz - 40 kHz
See Table 41: Output Clock Phase Noise for details 100 Hz - 800 kHz
100 Hz - 800 kHz
44.736 MHz with T0/T4 APLL
34.368 MHz without APLL
See Table 41: Output Clock Phase Noise for details 10 Hz - 400 kHz
10 Hz - 400 kHz
34.368 MHz with T0/T4 APLL
GR-253, G.813 Option 2
0.004 UI p-p 0.001 UI RMS
0.004 UI p-p 0.001 UI RMS
0.001 UI p-p 0.001 UI RMS
0.018 UI p-p 0.007 UI RMS
0.028 UI p-p 0.009 UI RMS
0.002 UI p-p 0.001 UI RMS
0.162 UI p-p 0.03 UI RMS
0.01 UI p-p 0.009 UI RMS
limit 0.1 UI p-p
(1 UI-6430 ps)
12 kHz - 1.3 MHz
500 Hz - 1.3 MHz
65 kHz - 1.3 MHz
12 kHz - 5 MHz
1 kHz - 5 MHz
OC-3
G.813 Option 1, G.812
limit 0.5 UI p-p
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output
(1 UI-6430 ps)
G.813 Option 1
limit 0.1 UI p-p
(1 UI-6430 ps)
GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-1608 ps)
OC-12
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
transceiver)
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-1608 ps)
G.813 Option 1, G.812
limit 0.1 UI p-p
250 kHz - 5 MHz
5 kHz - 20 MHz
1 MHz - 20 MHz
(1 UI-160 8ps)
G.813 Option 1, G.812
limit 0.5 UI p-p
STM-16
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
transceiver)
(1 UI-402 ps)
G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-402 ps)
Note:
1. CMAC E2747 TCXO is used.
Electrical Specifications
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IDT82V3203B
EBU WAN PLL
Table 41: Output Clock Phase Noise
Output Clock 1
@100Hz Offset @1kHz Offset @10kHz Offset @100kHz Offset @1MHz Offset @5MHz Offset
Unit
Typ
Typ
Typ
Typ
Typ
Typ
622.08 MHz (T0 DPLL + T0/T4 APLL)
155.52 MHz (T0 DPLL + T0/T4 APLL)
38.88 MHz (T0 DPLL + T0/T4 APLL)
16E1 (T0/T4 APLL)
-70
-82
-94
-94
-95
-93
-92
-86
-98
-95
-100
-112
-124
-125
-127
-124
-122
-107
-119
-131
-131
-132
-131
-126
-128
-140
-143
-142
-143
-138
-141
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
-107
-118
-118
-120
-116
-116
-110
-110
-112
-109
-108
16T1 (T0/T4 APLL)
E3 (T0/T4 APLL)
T3 (T0/T4 APLL)
Note:
1. CMAC E2747 TCXO is used.
Table 42: Input Jitter Tolerance (155.52 MHz)
Table 44: Input Jitter Tolerance (2.048 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
12 µHz
178 µHz
1.6 mHz
15.6 mHz
0.125 Hz
19.3 Hz
500 Hz
> 2800
> 2800
> 311
> 311
> 39
1 Hz
5 Hz
150
140
130
40
20 Hz
300 Hz
400 Hz
700 Hz
2400 Hz
10 kHz
50 kHz
100 kHz
33
> 39
18
> 1.5
5.5
1.3
0.4
0.4
6.5 kHz
65 kHz
> 1.5
> 0.15
> 0.15
1.3 MHz
Table 43: Input Jitter Tolerance (1.544 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
5 Hz
150
140
130
38
20 Hz
300 Hz
400 Hz
700 Hz
2400 Hz
10 kHz
40 kHz
25
15
5
1.2
0.5
Electrical Specifications
106
August 21, 2007
IDT82V3203B
EBU WAN PLL
Table 45: Input Jitter Tolerance (8 kHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
5 Hz
0.8
0.7
20 Hz
0.6
300 Hz
400 Hz
700 Hz
2400 Hz
3600 Hz
0.16
0.14
0.07
0.02
0.01
Table 46: T0 DPLL Jitter Transfer & Damping Factor
3 dB Bandwidth
Programmable Damping Factor
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
4 Hz
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
8 Hz
18 Hz
35 Hz
70 Hz
560 Hz
Electrical Specifications
107
August 21, 2007
IDT82V3203B
EBU WAN PLL
7.5
OUTPUT WANDER GENERATION
template
template
tested result
tested result
Figure 22. Output Wander Generation
Electrical Specifications
108
August 21, 2007
IDT82V3203B
EBU WAN PLL
7.6
INPUT / OUTPUT CLOCK TIMING
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
8 kHz Input Clock
8 kHz Output Clock
t1
t2
t3
t4
t5
t6
6.48 MHz Input Clock
6.48 MHz Output Clock
19.44 MHz Input Clock
19.44 MHz Output Clock
25.92 MHz Input Clock
25.92 MHz Output Clock
38.88 MHz Input Clock
38.88 MHz Output Clock
51.84 MHz Input Clock
51.84 MHz Output Clock
Figure 23. Input / Output Clock Timing
Table 47: Input/Output Clock Timing
Symbol
Typical Delay 1 (ns)
Peak to Peak Delay Variation (ns)
t1
t2
t3
t4
t5
t6
4
1
1.6
1.6
1.6
1.6
1.6
1.6
1
2
1.4
3
Note:
1. Typical delay provided as reference only.
Electrical Specifications
109
August 21, 2007
IDT82V3203B
EBU WAN PLL
7.7
OUTPUT CLOCK TIMING
MFRSYNC_2K/
FRSYNC_8K
t1
t2
N X T1 (1.544 MHz)
N X E1 (2.048 MHz)
t3
t4
E3 (34.368 MHz)
T3 (44.736 MHz)
6.48 MHz
t5
t6
t7
t8
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
t9
t10
t11
t12
311.04 MHz
622.08 MHz
t13
Table 48: Output Clock Timing
Symbol
Typical Delay (ns)
Peak to Peak Delay Variation (ns)
t1
t2
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
t3
2
t4
2
t5
2
t6
2
t7
2
t8
2
t9
2
t10
t11
t12
t13
2
1.5
1.5 (not recommended to use)
1.5 (not recommended to use)
Electrical Specifications
110
August 21, 2007
Glossary
3G
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
Third Generation
ADSL
AMI
Asymmetric Digital Subscriber Line
Alternate Mark Inversion
APLL
ATM
Analog Phase Locked Loop
Asynchronous Transfer Mode
Building Integrated Timing Supply
Complementary Metal-Oxide Semiconductor
Digital Controlled Oscillator
Digital Phase Locked Loop
Digital Subscriber Line
BITS
CMOS
DCO
DPLL
DSL
DSLAM
DWDM
EPROM
GPS
Digital Subscriber Line Access MUX
Dense Wavelength Division Multiplexing
Erasable Programmable Read Only Memory
Global Positioning System
Global System for Mobile Communications
Infinite Impulse Response
GSM
IIR
IP
Internet Protocol
ISDN
JTAG
LOS
Integrated Services Digital Network
Joint Test Action Group
Loss Of Signal
LPF
Low Pass Filter
LVDS
MTIE
MUX
OBSAI
OC-n
Low Voltage Differential Signal
Maximum Time Interval Error
Multiplexer
Open Base Station Architecture Initiative
Optical Carried rate, n = 1, 3, 12, 48, 192, 768; 51 Mbit/s, 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s, 10 Gbit/s, 40 Gbit/s.
Glossary
111
August 21, 2007
IDT82V3203B
EBU WAN PLL
PBO
PDH
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
Phase Build-Out
Plesiochronous Digital Hierarchy
Positive Emitter Coupled Logic
Phase & Frequency Detector
Phase Locked Loop
PECL
PFD
PLL
RMS
PRS
Root Mean Square
Primary Reference Source
Synchronous Digital Hierarchy
SDH / SONET Equipment Clock
SONET Minimum Clock
SDH
SEC
SMC
SONET
SSU
Synchronous Optical Network
Synchronization Supply Unit
Synchronous Transfer Mode
Time Compression Multiplexing Integrated Services Digital Network
Time Deviation
STM
TCM-ISDN
TDEV
UI
Unit Interval
WLL
Wireless Local Loop
Glossary
112
August 21, 2007
Index
Frequency Hard Alarm .................................................................20, 25
Frequency Hard Alarm Threshold ...................................................... 20
H
A
Averaged Phase Error ........................................................................29
B
Hard Limit ........................................................................................... 23
Holdover Frequency Offset ................................................................ 30
I
Bandwidths and Damping Factors .....................................................29
Acquisition Bandwidth and Damping Factor ...............................29
Locked Bandwidth and Damping Factor .....................................29
Starting Bandwidth and Damping Factor ....................................29
IIR ...................................................................................................... 30
Input Clock Frequency ....................................................................... 20
Input Clock Selection ......................................................................... 21
C
Calibration ..........................................................................................15
Coarse Phase Loss ............................................................................23
Crystal Oscillator ................................................................................15
Current Frequency Offset ...................................................................29
D
Automatic selection ..............................................................22, 25
External Fast selection ............................................................... 25
Forced selection ...................................................................22, 25
Internal Leaky Bucket Accumulator ................................................... 19
Bucket Size ................................................................................ 19
Decay Rate ................................................................................ 19
Lower Threshold ........................................................................ 19
Upper Threshold ........................................................................ 19
DCO ...................................................................................................29
Division Factor ....................................................................................17
DPLL Hard Alarm ...............................................................................23
DPLL Hard Limit .................................................................................23
DPLL Operating Mode
L
Limit ................................................................................................... 32
LPF .................................................................................................... 29
M
Free-Run mode ..........................................................................29
Holdover mode ...........................................................................29
Automatic Fast Averaged ...................................................30
Automatic Instantaneous ....................................................30
Automatic Slow Averaged ..................................................30
Manual ................................................................................30
Locked mode ..............................................................................29
Temp-Holdover mode .........................................................29
Lost-Phase mode .......................................................................29
Pre-Locked mode .......................................................................29
Pre-Locked2 mode .....................................................................30
Master Clock ...................................................................................... 15
N
No-activity Alarm ..........................................................................19, 25
P
PFD .................................................................................................... 29
Phase Lock Alarm ........................................................................23, 25
Phase-compared ..........................................................................23, 32
Phase-time ......................................................................................... 32
Pre-Divider ......................................................................................... 17
DPLL Soft Alarm .................................................................................23
DPLL Soft Limit ..................................................................................23
E
External Sync Alarm ...........................................................................36
F
DivN Divider ............................................................................... 17
HF Divider .................................................................................. 17
Lock 8k Divider .......................................................................... 17
Fast Loss ............................................................................................23
Fine Phase Loss .................................................................................23
Index
113
August 21, 2007
IDT82V3203B
EBU WAN PLL
Non-Revertive switch ................................................................. 25
Revertive switch ......................................................................... 25
R
Reference Clock .................................................................................20
State Machine .................................................................................... 27
S
V
Selected Input Clock Switch ...............................................................25
Validity ............................................................................................... 25
Index
114
August 21, 2007
IDT82V3203B
EBU WAN PLL
PACKAGE DIMENSIONS - 68-PIN NL
Figure 24. 68-Pin NL Package Dimensions (a) (in Millimeters)
115
August 21, 2007
IDT82V3203B
EBU WAN PLL
Figure 25. 68-Pin NL Package Dimensions (b) (in Millimeters)
116
August 21, 2007
IDT82V3203B
EBU WAN PLL
Y
OL
BM
Figure 26. 68-Pin NL Package Dimensions (c) (in Millimeters)
117
August 21, 2007
IDT82V3203B
EBU WAN PLL
ORDERING INFORMATION
XXXXXXX
Device Type
XX
X
IDT
Process/
Temperature
Range
Blank
Industrial (-40 °C to +85 °C)
Thermally Enhanced Plastic Very Fine Pitch Quad
Flat No Lead Package (VFQFPN, NL68)
NL
Green Thermally Enhanced Plastic Very Fine Pitch Quad
Flat No Lead Package (VFQFPN, NLG68)
NLG
82V3203B WAN PLL
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118
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