IDT82V8313BBG [IDT]
Framer, PBGA208, 17 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208;
| 型号： | IDT82V8313BBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Framer, PBGA208, 17 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208 |
| 文件： | 总140页 (文件大小：1708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT M13 MULTIPLEXER
IDT82V8313
Version 3
June 3, 2004
2975 Stender Way, Santa Clara, California 95054
Telephone: (800) 345-7015 • • FAX: (408) 492-8674
Printed in U.S.A.
© 2004 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
Table of Contents
FEATURES................................................................................................................................................................................................................ 1
PACKAGE ..............................................................................................................................................................................................................2-4
PIN DESCRIPTIONS.........................................................................................................................................................................................5-12
REGISTER MEMORY MAP..........................................................................................................................................................................13-16
REGISTER DESCRIPTIONS............................................................................................................................................................................. 17
Master Reset/Lock Status............................................................................................................................................................................... 17
Revision/Global PMON Update ...................................................................................................................................................................... 17
Master Bypass Configuration.......................................................................................................................................................................... 18
Master HDLC Configuration............................................................................................................................................................................ 19
Master Loopback Configuration...................................................................................................................................................................... 20
Master Interface Configuration........................................................................................................................................................................ 21
Master Alarm Enable/Network Requirement Bit ............................................................................................................................................. 22
Master Test ..................................................................................................................................................................................................... 23
Master Interrupt Source #1............................................................................................................................................................................. 24
Master Interrupt Source #2............................................................................................................................................................................. 25
Master Interrupt Source #3............................................................................................................................................................................. 25
DS3 Transmit Configuration............................................................................................................................................................................ 26
DS3 Transmit Diagnostic ................................................................................................................................................................................ 27
DS3 PMON Interrupt Enable/Status ............................................................................................................................................................... 28
DS3 LCV Count LSB....................................................................................................................................................................................... 28
DS3 LCV Count MSB...................................................................................................................................................................................... 29
DS3 FERR Count LSB.................................................................................................................................................................................... 29
DS3 FERR Count MSB................................................................................................................................................................................... 29
DS3 EXZS Count LSB .................................................................................................................................................................................... 30
DS3 EXZS Count MSB ................................................................................................................................................................................... 30
DS3 PERR Count LSB.................................................................................................................................................................................... 30
DS3 PERR Count MSB................................................................................................................................................................................... 31
DS3 CPERR Count LSB................................................................................................................................................................................. 31
DS3 CPERR Count MSB................................................................................................................................................................................ 31
DS3 FEBE Count LSB .................................................................................................................................................................................... 32
DS3 FEBE Count MSB ................................................................................................................................................................................... 32
XFDL TSB Configuration ................................................................................................................................................................................ 33
XFDL Interrupt Status ..................................................................................................................................................................................... 33
XFDL TSB Transmit Data ............................................................................................................................................................................... 34
RFDL TSB Configuration ................................................................................................................................................................................ 34
Table of Contents
iv
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RFDL TSB Interrupt Control/Status ................................................................................................................................................................ 35
RFDL TSB Status ........................................................................................................................................................................................... 36
RFDL TSB Receive Data................................................................................................................................................................................ 36
MX23 Configuration........................................................................................................................................................................................ 37
DeMux AIS Insert Register ............................................................................................................................................................................. 38
MX23 MUX AIS Insert Register ...................................................................................................................................................................... 38
MX23 Loopback Activate Register.................................................................................................................................................................. 39
MX23 Loopback Request Insert Register....................................................................................................................................................... 39
MX23 Loopback Request Detect Register...................................................................................................................................................... 40
MX23 Loopback Request Interrupt Register................................................................................................................................................... 40
FEAC XBOC TSB Code.................................................................................................................................................................................. 41
RBOC Configuration/Interrupt Enable............................................................................................................................................................. 41
RBOC Interrupt Status.................................................................................................................................................................................... 42
DS3 FRMR Configuration............................................................................................................................................................................... 43
DS3 FRMR Interrupt Enable (ACE=0)............................................................................................................................................................ 44
DS3 FRMR Additional Configuration Register (ACE=1)................................................................................................................................. 45
DS3 FRMR Interrupt Status............................................................................................................................................................................ 46
DS3 FRMR Status .......................................................................................................................................................................................... 47
DS2 FRMR Configuration............................................................................................................................................................................... 48
DS2 FRMR Interrupt Enable........................................................................................................................................................................... 49
DS2 Framer Interrupt Status........................................................................................................................................................................... 50
DS2 Framer Status ......................................................................................................................................................................................... 51
DS2 Framer Monitor Interrupt Enable/Status.................................................................................................................................................. 52
DS2 FRMR FERR Count................................................................................................................................................................................ 52
DS2 FRMR PERR Count (LSB)...................................................................................................................................................................... 53
DS2 FRMR PERR Count (MSB)..................................................................................................................................................................... 53
MX12 Configuration And Control.................................................................................................................................................................... 54
MX12 Loopback Code Select Register........................................................................................................................................................... 55
MX12 AIS Insert Register ............................................................................................................................................................................... 56
MX12 Loopback Activate Register.................................................................................................................................................................. 56
MX12 Loopback Interrupt Register................................................................................................................................................................. 57
DS1 Transmit And Receive Edge Select ........................................................................................................................................................ 57
FUNCTIONAL DESCRIPTION..................................................................................................................................................................... 59-78
DATA LINK......................................................................................................................................................................................................... 79-92
FUNCTIONAL TIMING................................................................................................................................................................................... 93-94
LOOPBACK MODES.................................................................................................................................................................................... 95-100
DC ELECTRICAL CHARACTERISTICS .............................................................................................................................................. 101-102
Absolute Maximum Ratings .......................................................................................................................................................................... 101
Recommended Operating Conditions(1) ...................................................................................................................................................... 101
DC Electrical Characteristics ........................................................................................................................................................................ 102
Table of Contents
iv
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
AC ELECTRICAL CHARACTERISTICS .............................................................................................................................................. 103-114
Microprocesser Interface Timing Characteristics/Microprocessor Read Access .......................................................................................... 103
Microprocessor Write Access ....................................................................................................................................................................... 104
Timing Characteristics .................................................................................................................................................................................. 105
Transmit DS3 Input....................................................................................................................................................................................... 106
Transmit Overhead input .............................................................................................................................................................................. 106
Transmit Tributary Input................................................................................................................................................................................ 107
Transmit Data Link Input............................................................................................................................................................................... 107
Transmit Data Link EOM Input...................................................................................................................................................................... 108
Transmit DS3 Output .................................................................................................................................................................................... 109
Receive DS3 Output......................................................................................................................................................................................110
Receive Overhead Output .............................................................................................................................................................................111
Transmit Overhead Output ............................................................................................................................................................................112
Receive Tributary Output...............................................................................................................................................................................112
Receive Data Link Output..............................................................................................................................................................................113
JTAG ................................................................................................................................................................................................................ 115-120
JTAG Timing Solutionsl..................................................................................................................................................................................115
JTAG AC Electrical Characteristics................................................................................................................................................................116
Identification Register Definitions...................................................................................................................................................................116
Scan Register Sizes.......................................................................................................................................................................................116
System Interface Parameters ........................................................................................................................................................................117
JTAG Scan Order................................................................................................................................................................................... 118-120
ORDERING INFORMATION............................................................................................................................................................................ 121
GLOSSARY ................................................................................................................................................................................................... 123-126
STANDARDS................................................................................................................................................................................................. 127-128
INDEX .............................................................................................................................................................................................................. 129-130
Table of Contents
iv
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Table of Contents
iv
June 3, 2004
*Notice: The information in this document is subject to change without notice
List of Tables
Table 1 — Pin Descriptions ..................................................................................................................................................................................... 5-11
Table 2 — Register Memory Map...........................................................................................................................................................................13-16
Table 3 — FERF Status (X1 & X2 State)..................................................................................................................................................................... 62
Table 4 — C-Bit Parity Mode DS3 C-Bit Assignments................................................................................................................................................. 63
Table 5 — DS3 FEAC Loopback Control Message..................................................................................................................................................... 65
Table 6 — DS3 FEAC Alarm and Status Message...................................................................................................................................................... 65
Table 7 — DS1 Bit Oriented Codes Command and Response Message.................................................................................................................... 67
Table 8 — DS1 Bit Oriented Priority Message............................................................................................................................................................. 67
Table 9 — DS1 Bit Oriented Codes Reserved Messages ........................................................................................................................................... 67
Table 10 — Data Link Format...................................................................................................................................................................................... 68
Table 11 — Max Jitter Tolerance on DS if CAT II......................................................................................................................................................... 70
List of Tables
vi
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
List of Tables
vi
June 3, 2004
*Notice: The information in this document is subject to change without notice
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
DS3 Framer Block................................................................................................................................................................................ 59
DS3 Frame .......................................................................................................................................................................................... 59
B3ZS Coding ....................................................................................................................................................................................... 60
Transmit BOC...................................................................................................................................................................................... 66
Receive BOC....................................................................................................................................................................................... 66
Jitter Definition..................................................................................................................................................................................... 69
Maximum Jitter Tolerance on DSn Interface Inputs............................................................................................................................. 70
M23 Multiplexer Block.......................................................................................................................................................................... 71
DS3 Stuff Block.................................................................................................................................................................................... 72
DS2 Framer Block................................................................................................................................................................................ 73
DS2 Frame ......................................................................................................................................................................................... 73
G.747 Frame Format ........................................................................................................................................................................... 74
M12 Block............................................................................................................................................................................................ 77
DS2 Stuff Block.................................................................................................................................................................................... 78
XFDL.................................................................................................................................................................................................... 79
XFDL Polled Mode............................................................................................................................................................................... 80
XFDL Interrupt Mode ........................................................................................................................................................................... 81
XFDL Interrupt Service Routine........................................................................................................................................................... 81
XFDL DMA Mode................................................................................................................................................................................. 82
XFDL Normal Data Sequence ............................................................................................................................................................. 83
XFDL Underrun Sequence................................................................................................................................................................... 84
TDLINT Timing Normal Data TX.......................................................................................................................................................... 85
TDLEOMI Timing EOMI After CRC...................................................................................................................................................... 86
RFDL .................................................................................................................................................................................................. 87
RFDL Polled Mode............................................................................................................................................................................... 88
RFDL Interrupt Driven Mode................................................................................................................................................................ 89
RFDL Interrupt Service Routine........................................................................................................................................................... 89
RFDL DMA Mode................................................................................................................................................................................. 90
RFDL Normal Data And Abort Sequence ............................................................................................................................................ 91
Receive DS3 OH Serial Stream........................................................................................................................................................... 93
Transmit DS3 OH Serial Stream.......................................................................................................................................................... 93
Functional Receive OH Timing Low-Speed......................................................................................................................................... 93
Functional Receive Timing PMON....................................................................................................................................................... 94
Functional Receive OH Timing High-Speed........................................................................................................................................ 94
DS3 Diagnostic Loopback.................................................................................................................................................................... 96
DS3 Line Loopback ............................................................................................................................................................................. 97
DS2/G.747 Demultiplex Loopback....................................................................................................................................................... 98
DS1/E1 Demultiplex Loopback............................................................................................................................................................ 99
Microprocessor Read Access Timing ................................................................................................................................................ 103
Microprocessor Write Access Timing................................................................................................................................................. 104
Receive DS3 Input Timing................................................................................................................................................................. 105
Transmit DS3 Input Timing................................................................................................................................................................ 106
Transmit Overhead Input Timing ....................................................................................................................................................... 106
Transmit Tributary Input Timing......................................................................................................................................................... 107
Transmit Data Link Input Timing........................................................................................................................................................ 107
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
List of Figures
viii
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Transmit Data Link EOM Input Timing............................................................................................................................................... 108
Transmit DS3 Output Timing ............................................................................................................................................................. 109
Receive DS3 Output Timing .............................................................................................................................................................. 110
Receive Overhead Output Timing ..................................................................................................................................................... 111
Transmit Overhead Output Timing .................................................................................................................................................... 112
Receive Tributary Output Timing....................................................................................................................................................... 112
Receive Data Output Link Output Timing .......................................................................................................................................... 113
Standad JTAG Timing ....................................................................................................................................................................... 115
List of Figures
viii
June 3, 2004
*Notice: The information in this document is subject to change without notice
3.3 VOLT M13 MULTIPLEXER
IDT82V8313
DS2 LOF detectors and DS2 AIS DS2 X-bit access
FEATURES:
DS2 transmit/receive X-bit control/status
DS2 F, M, and X bit insertion
Full featured single chip M13-ideal for upgrading existing
multi-line T1/E1 line cards to single line channelized T3 service
DS2 FERF and AIS under microprocessor control
Small footprint 17mm x 17mm BGA package and 208 pin PQFP
packages available
Transmission of RAI and reserved bit under microprocessor
control
3.3V operation with 5V tolerant I/O
Programmable preemptive inversion of C-bits for remote
loopback
28 independent DS1 clock inputs each with programmable
clock edge adapter
DS3 idle signal generators
28 independent DS1 outputs eatch with programmable clock
edge adapter
DS3 LOS, LOF, P-bit Parity, C-bit Parity, AIS and idle detectors
DS3 X-bit access
M12 bypass for direct input of DS2 in to the M23 multiplexer
Programmable clock edge
DS3 transmit and receive AIS generation and detection
DS3 M-frame and M-subframe boundary indications
Supports M23 or C-bit parity format formats
G.747 formats for E1 to be multiplexed onto a DS3
JTAG
TX O/H
Access
XBOC TX
FEAC
XFDL TX
HDLC
TXDS1CLK1-4
TXDS1D1-4
M12
MUX
#1
1
DS2 TX
Framer #1
TX3CLK
DS3 TX
Framer
B3ZS
Encoder
•
•
•
M23
MUX
•
•
•
TX3POS/TX3D
TX3NEG/TX3FP
TXDS1CLK5-28
TXDS1D5-28
M12
MUX
#2-7
2-7
DS2 TX
Framer #2-7
M21
MUX
#1
1
RXDS1CLK1-4
RXDS1D1-4
DS2 RX
Framer #1
RX3CLK
B3ZS
Decoder
•
•
•
DS3 RX
Framer
•
•
•
M32
MUX
RX3POS/RX3D
RX3NEG/RX3FP
2-7
M21
MUX
#2-7
RXDS1CLK5-28
RXDS1D5-28
DS2 RX
Framer #2-7
RFDL RX
RDLCLK
RX O/H
Access
RBOC RX
FEAC
PMON
Microprocessor
Port
6143 drw01
IDT an the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1
June 3, 2004
DSC -6143/2
2004 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
PACKAGE
A1 BALL PAD CORNER
A
TCLK
TD2CLK
RD1
DAT1
RD1
CLK1
RD1
DAT2 DAT3
TD1
RD1
CLK3
RD1
CLK4
TD1
CLK5
TD1
CLK6
TD1
CLK7
RD1
DAT8
RD1
CLK8
TD1
DAT9
RD1
DAT9
TD1
DAT1
B
TD1
CLK4
TPOS_
DAT
GD2CLK TIMFP
TD1
CLK1
TD1
DAT2
TD1
CLK2 DAT3
RD1
GND
RD1
DAT5
RD1
DAT6
RD1
DAT7
TD1
DAT8
TD1
CLK8
RD1
CLK9
TD1
CLK9
C
TNEG_
MFP
TICLK
RAIS
TDLCLK TDLSIG_ RD1
TD1
CLK3
TD1
DAT4
RD1
DAT4
TD1
DAT5
TD1
DAT6
TD1
DAT7
RD1
CLK7
TD1
RD1
TD1
DAT10
_INT
UDR
CLK2
CLK10 DAT10
D
RDLCLK
_INT
TD1
CLK11
TDLEOMI GND
VCC
VCC
VCC
VCC
RD1
CLK5
RD1
CLK6
RD1
DAT11 DAT11
TDI
RD1
CLK10
RODAT
ROCLK
RMFP
E
ROHP
TOHCLK TOHFP RDLSIG
_EOM
TD1
RD1
TD1
RD1
CLK11
CLK12 DAT12 DAT12
F
RMSFP
TOH
TOHEN ROHFP
TD1
RD1
TD1
RD1
CLK13 DAT13 DAT13
CLK12
G
ROH
ROHCLK RLOS
VCC
VCC
GND
GND
GND
GND
VCC
RD1
DAT14 DAT14
TD1
RD1
CLK13
H
RCLK
ROOF_ RFERF
RED
GND
GND
GND
GND
GND
GND
GND
GND
GND
TD1
DAT5
RD1
CLK14
TD1
CLK14
VCC
VCC
J
RNEG_
LCV
RPOS_
DAT
REXZ
RD1
DAT15 CLK15
TD1
RD1
CLK15
VCC
VCC
K
D1
D0
D4
GND
GND
GND
TD1
RD1
TD1
CLK16
INT
VCC
RD1
DAT16 DAT16
L
D5
D3
D2
D6
TD1
RD1
TD1
CLK17
CLK16 DAT17 DAT17
M
D7
A0
RD1
TD1
RD1
TD1
CLK18
ALE
CS
A1
A3
CLK17 DAT18 DAT18
N
A2
RD1
DAT28
TD1
CLK27
VCC
RD1
VCC
RD1
VCC
TD1
VCC
RD1
VCC
RD1
TD1
TD1
RD1
TD1
RD1
DAT19
VCC
CLK23 CLK22 CLK18 DAT19
P
A4
EX_RST
TD1
CLK28
JTAG_
TDI
JTAG_
RD1
RD1
TD1
TD1
CLK19
RD1
CLK19
CLK26 DAT26 CLK25 DAT25
CLK24 TCLK DAT23 DAT22 CLK21
R
RD
WR
3
RD1
CLK28
A5
A8
A7
RD1
TD1
JTAG_
RD1
CLK25
JTAG_
TMS
TD1 TD1 TD1 TD1 RD1
CLK24 DAT24 DAT23 DAT22 DAT21 CLK20
RD1
TD1
DAT20
CLK27 DAT27 TDO
T
JTAG_
TRST
RD1
DAT20
A6
TD1 RD1 TD1
DAT28 DAT27 CLK26 DAT26 DAT25
TD1
TD1
RD1
RD1
RD1
RD1
TD1
TD1
DAT24 CLK23 CLK22 CLK21 DAT21 CLK20
1
2
4
5
6
7
8
9
10
11
12
13
14
15
16
6143 drw02
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
PACKAGE
2
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
PIN 1
TICLK
TCLK
TPOS/TDAT
RAIS
TNEG/TMFP
GD2CLK
1
TD1CLK9
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
2
RD1CLK9
TD1DAT10
RD1DAT10
TD1CLK10
RD1CLK10
TD1DAT11
RD1DAT11
TD1CLK11
3
4
5
6
RODAT
GND
VCC
ROCLK
RMFP
ROHP
7
8
9
(2)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
NC
RD1CLK11
TD1DAT12
RD1DAT12
TD1CLK12
RD1CLK12
(2)
NC
TOHCLK
TOHFP
RMSFP
TOH
TOHEN
ROHFP
ROH
ROHCLK
RLOS
RFERF
TD1DAT13
(2)
NC
RD1DAT13
TD1CLK13
RD1CLK13
TD1DAT14
RD1DAT14
TD1CLK14
RD1CLK14
GND
ROOF/RRED
REXZ
RCLK/VCLK
(2)
NC
GND
TD1DAT15
RD1DAT15
TD1CLK15
RD1CLK15
TD1DAT16
(2)
NC
RPOS/RDAT
RNEG/RLCV
RDLCLK/RDLINT
RDLSIG/RDLEOM
(2)
NC
RD1DAT16
TD1CLK16
RD1CLK16
VCC
INT
D0
D1
GND
D2
D3
TD1DAT17
(2)
NC
D4
RD1DAT17
TD1CLK17
RD1CLK17
TD1DAT18
RD1DAT18
(2)
NC
D5
D6
VCC
D7
CS
(2)
NC
TD1CLK18
GND
RD1CLK18
TD1DAT19
RD1DAT19
TD1CLK19
ALE
A0
A1
A2
A3
A4
A5
RD1CLK19
TD1DAT20
6143 drw03
NOTE:
1. JTAG
2. NC = No Connect
PQFP: 0.50mm pitch, 28mm x 28mm (DS208-1, order code: DS)
TOP VIEW
PACKAGE
3
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
PACKAGE
4
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
PIN DESCRIPTIONS
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
RCLK
Receive Clock
I
26
29
H1
J2
This is the DS3 receive clock input. RCLK is nominally a 44.736 MHz, 50% duty cycle
clock.
RPOS/RDAT
RNEG/RLCV
ReceivePositive
Pulse/Receive
Data
I
I
In dual rail mode, this pin is RPOS and represents the positive pulses of a B3ZS-encoded
signal. In single rail mode, this pin is RDAT and represents the unipolar DS3 input data.
The M13 can be configured to sample data on either the rising or falling edge of RCLK.
Receive
30
J1
In dual rail mode, this pin is RNEG and represents the negative pulses of a
B3ZS-encoded signal. In single rail mode, this pin is RLCV and can be used to insert line
code violations on the DS3 input. The M13 can be configured to sample data on either
the rising or falling edge of RCLK.
Negative Pulse/
Receive Line
Code Violation
ROCLK
RODAT
RMFP
Receive Output
Clock
O
O
O
10
7
D2
D1
D3
The DS3 receive output clock is a buffered version of the input RCLK. Like the RCLK, this
is nominally a 44.736 MHz, 50% duty cycle clock. REXZ, RLOS, RMFP, RMSFP, and
RODAT are updated on the falling edge of ROCLK.
Receive Output
Data
This is a 44.736 Mb/s DS3 NRZ receive data stream decoded from the B3ZS line signal.
RODAT is aligned to the frame alignment signals RMFP, RMSFP, and ROHP. RODAT is
updated in the falling edge of ROCLK.
Receive M-
Frame Pulse
11
The receive M-frame pulse signal and marks the first bit in the M-frame (X1) of the DS3
data on RODAT. In an OOF (Out Of Frame) condition the M13 internal counters will
maintain the old M-frame alignment position. When the framer regains frame alignment
the RMFP timing will be updated to the new timing. This may result in a change of frame
alignment. RMFP is updated on the falling edge of ROCLK.
RMSFP
Receive M-
subframe Frame
Pulse
O
16
F1
The receive M-subframe pulse signal and marks the first bit of each M-subframe
(X, P, and M) in each M-subframe of the DS3 on RODAT. In an OOF (Out Of Frame)
condition the M13 internal counters will maintain the old M-frame alignment position.
When the framer regains frame alignment the RMSFP timing will be updated to the new
timing. This may result in a change of frame alignment. RMSFP is updated on the falling
edge of ROCLK.
ROHP
Receive
Overhead Pulse
O
O
12
21
E1
G2
The receive overhead pulse signal and marks the overhead bit positions (X, P, M, C, and
F) in the DS3 data on RODAT. In an OOF (Out Of Frame) condition the M13 internal
counters will maintain the old frame alignment position. When the framer regains frame
alignment, the ROHP timing will be updated to the new timing. This may result in a
change of frame alignment. ROHP is updated in the falling edge of ROCLK.
ROHCLK
Receive
Overhead Clock
The receive overhead clock and transitions on each overhead bit. ROHCLK is nominally
a 526 KHz. RAIS, RFERF, RFERR, RIDL, ROH, ROHFP, and ROOF are updated on the
falling edge of ROHCLK.
ROH
Receive
Overhead Data
O
O
20
19
G1
F4
The receive overhead data signal transmits the overhead bits, C, F, M, P, and X bits from
the receive DS3 stream. ROH is updated on the falling edge of ROHCLK.
ROHFP
Receive
Overhead
Frame Pulse
The receive overhead frame pulse is used to mark the positions of the overhead bits
within the overhead stream, ROH. ROHFP will remain high during the X1 overhead bit.
ROHFP is updated on the falling edge of ROHCLK.
RLOS
Receive Loss of
Signal
O
22
G3
The receive loss of signal will remain high when the dual rail NRZ format stream is
selected or when a loss of signal condition is detected (175 successive zeros on RPOS
and RNEG). When the one’s density is greater than 33% for 175 +/i 1 bit period on the
RPOS and RNEG inputs, RLOS will be set low. RLOS is updated on the falling edge of
ROCLK.
PIN DESCRIPTION
5
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
REXZ
Receive
Excessive Zeros
O
25
J3
The receive excessive zero indicates the detection of an excessive zero condition. When
3 or more successive zeros are received on the DS3 bipolar stream REXZ pulses high for
one ROCLK cycle. In the uni-polar mode, REXZ is low. REXZ is updated on the falling
edge of ROCLK.
RAIS
Receive Alarm
Indication Signal
O
O
4
C3
The receive alarm indication signal is used to indicate and AIS (alarm indication) in the
received DS3 signal. The RAIS will be set high when the AIS pattern has been detected
for 2.23 ms or 13.5 ms as programmed by software. When the AIS pattern is absent in
the DS3 signal for 2.23 ms or 13.5 ms the RAIS will be set low. RAIS is updated on the
falling edge of ROHCLK.
ROOF/RRED
Receive Out of
Frame/Receive
Red Alarm
24
H2
ROOF/RREF will be ROOF when the REDO bit in the Master Alarm Enable register is 0
and will indicate an receive out-of-frame error. When no out-of-frame errors exist the
ROOF will be low. ROOF will be high when there is an out-of-frame condition: 3 out of 16
(default) or 3 out of 8 consecutive F-bit errors are detected, or when more M-bit errors are
detected in 3 out of 4 consecutive M-frames. ROOF is updated on the falling edge of
ROHCLK. ROOF/RRED will be RRED when the REDO bit the Master Alarm Enable
register is 1 and will indicate an out-of-frame condition or a DS3 loss of signal condition. A
DS3 out-of-frame condition is considered when there are no transitions for 2.23 ms or
13.5 ms (software programmable) and RRED will be set high. RRED will be reset low
when the out-of-frame condition or loss of signal condition are absent for 2.23 or 13.5 ms.
RRED is updated on the falling edge of ROHCLK.
RFERF
Receive FarEnd
Receive Failure
O
O
23
31
H3
D4
The receive far end receive failure reflects the internal state of the internal FERF but the
RFERF state is delayed by two M-frames. FERF is set high when both X1 and X2 are 0 in
the M-frame. When X1 and X2 are both high in the M-frame, FERF is set low. Otherwise,
FERF remains in its previous state when X1 • X2 in the current frame. The RFERF
latency is used to provide better than 99.99% chance of freezing (holding FERF in its
previous state) upon a valid state value during an out-of-frame. RFERF is updated every
M-frame on the falling edge on ROHCLK.
RDLCLK/
RDLINT
Receive Data
Link Clock/
Receive Data
Link Interrupt
RDLCLK/RDLINT will be RDLCLK when the REXHDLC bit in the Master HDLC
Configuration Register is set to 1 and is used as the receive data link clock when an
external HDLC receiver is selected. The RDLCLK is the clock for the external processing
of the data link signal extracted by the DS3 framer. RDLCLK is nominally a 28.2 kHz
clock that is low for at least 1.9us per cycle and is updated 3 times per M-frame. RDLCLK
is updated on the falling edge of the ROHCLK. RDLCLK/RDLINT will be RDLINT when
the REXHDLC bit in the Master HDLC Configuration Register is set to 0 and is used as
the data link interrupt when an internal HDLC receiver is selected. When an HDLC
receiver event occurs the RDLINT will reflect a change in status. By reading the Interrupt
Enable/Status register, the interrupt will be cleared, both the register and the RDLINT pin.
RDLINT is updated on the falling edge of ROHCLK. RDLINT is a configurable active low
open-drain out or active high open-drain output. In the case where an external DMA
device is used, RDLINT would be directly connected, however if the interrupt is being
handled by a microprocessor, the RFDL may be wired-ORed with the INT output. In this
later case, RDLINT should be configured as a active-low open drain output.
PIN DESCRIPTION
6
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
RDLSIG/
RDLEOM
Receive Data
Link Signal/
Receive Data
Link End Of
Message
O
32
E4
RDLSIG/RDLEOM will be RDLSIG when the REXHDLC bit in the Master HDLC
Configuration Register is set to 1 and is used as the receive data link signal when an
external HDLC receiver is selected. The RDLSIG is the C-bit message used in C-bit parity
mode and transmits the three C-bits from the fifth M-subframe in the DS3 frame. RDLSIG
is updated on the falling edge of the RDLCLK. RDLSIG/RDLEOM will be RDLEOM when
the REXHDLC bit in the Master HDLC Configuration Register is set to 0 and is used as
the receive end of message signal when an internal HDLC receiver is selected. RDLEOM
is used to denote the last byte of a sequence that is read from the HDLC receiver or to
denote an overflow condition in the receive HDLC buffer. RDLEOM is updated on the fall-
ing edge of ROHCLK. In order to clear/deassert the RDLEOM the supervising micropro-
cessor must read the Interrupt Enable/Status Register. In the case where RDLEOM
would be connected to a supervising microprocessor, an external DMA is used. The
RDLEOM would be programmed to be active-low, open-drain and wired-ORed with the
INT to signal the microprocessor that the a complete message is ready.
RD1CLK1-28
Receive DS1
Clock
O
*See TQFP *See BGA RD1CLK1-28 are the receive DS1 clocks used in conjunction with the RD1DAT. These
table below tablebelow clocks are at the T1 nominal rate of 1.544MHz, but will have jitter due to the
for details.
for details, demultiplexing and destuffing processes. RD1DAT28-1 can be programmed to update on
either the rising or falling edge of RD1CLK. For G.747, the internal M12 multiplexers still
uses the RD1CLKs to clock RD1DAT out, however every fourth clock, RD1CLK4, 8, 12,
16, 20, 24, and 28 clocks, is unused and in turn output LOW. These clocks run at the
nominal rate of 2.048MHz but will have jitter due to the demultiplexing and destuffing
processes. If a DS2 is inserted into the M13, thereby bypassing the M12 multiplexer,
every fourth clock RD1CLK4, 8, 12, 16, 20, 24, and 28 can be used as a DS2 clock. In
this case the unused clocks for that group will output LOW. The DS2 clock has a nominal
rate of 6.312MHz.
RD1DAT1-28
TD1CLK1-28
Receive DS1
Data
O
*See TQFP *See BGA RD1DAT1-28 is the DS1 data demultiplexed from the incoming DS3 stream.
table below tablebelow RD1DAT1-28 are updated on either the rising or falling edge of the corresponding
for details.
for details
RD1CLK1-28. In G.747, where the M12 multiplexers mux E1 data, RD1DAT 4, 8, 12, 16,
20, 24, and 28 are held low, while the remaining streams operate at a nominal 2.048MHz
data rate. M12 multiplexers are bypassed and DS2 data is output the fourth stream of the
group is used to output data. The remaining three streams of the group will be held low.
Transmit DS1
Clock
I
*See TQFP *See BGA The transmit DS1 clock, TD1CLK1-28 is used to sample incoming data on TD1DAT1-28
table below tablebelow to be multiplexed into a DS3. The M13 expects a nominal 1.544MHz clocks and expects
for details.
for deatils
minimal jitter and wander of a standard DS1. TD1DAT1-28 are sampled on either the
rising or falling edge of TD1CLK1-28. In G.747 multiplexing not all TD1 inputs are used.
In this case, every fourth input (TD1CLK4, 8, 12, 16, 20, 24, and 28) is unused, ignored
and must be tied to GND. The remaining clocks should be running at a nominal rate of
2.048MHz and expects minimal jitter and wander of a standard DS1. When the internal
M12 multiplexers are bypassed, the M13 device will use every fourth clock (TD1CLK4, 8,
12, 16, 20, 24, and 28) as the DS2 input clock. In this case, the remaining clocks are
unused, ignored and the unused inputs must be tied to GND.
TD1DAT1-28
Transmit DS1
Data
I
*See TQFP *See BGA The transmit DS1 data TD1DAT is the input data that is multiplexed in to a DS3. Input
table below tablebelow data can be programmed to sample on either the rising or falling edges of TD1CLK1-28.
for details.
fo details
In G.747, where the M12 multiplexers mux E1 data, every fourth data stream (TD1DAT4,
8, 12, 16, 20, 24, and 28) is ignored and must be tied to GND. In cases where a DS2 is
inserted directly into the M23 stage, every fourth TD1DAT (TD1DAT4, 8, 12, 16, 20, 24,
and 28) can be used. In this case the remaining TD1DAT streams of the group are
ignored and must be tied to GND.
PIN DESCRIPTION
7
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
GD2CLK
Generated DS2
Clock
O
6
B2
In M13 and C-bit parity modes, this is the transmit generated DS2 clock. In M13 operation
this clock is nominally a 6.311993 MHz clock which translates to a 39.1% stuffing ratio. In
C-bit parity mode this clock is nominally a 6.3062723 MHz clock, which translates to a
stuffing rate of 100% (used for C-bit parity). The GD2CLK may be tied directly to the
TD2CLK clock.
TD2CLK
Transmit DS2
Clock
I
206
205
A2
C5
The TD2CLK is the transmit DS2 clock and is the clock used in the M12 multiplexer.
TD2CLK is nominally a 6.312 MHz, 50% duty cycle clock and can be derived from the
GD2CLK.
TDLSIG/
TDLUDR
Transmit Data
Link Signal/
Transmit Data
Underrun
O
The TDLSIG/TDLUDR will be transmit data link, TDLSIG, when the TEXHDLC bit in the
Master HDLC Configuration Register is a logic 1. When an external HDLC receiver is
selected, TDLSIG will carry the the three C-bits in M-subframe #5 in the DS3. When C-bit
parity mode is not enabled TDLSIG is ignored. TDLSIG is sampled on the rising edge of
TDLCLK.The TDLSIG/TDLUDR will be the transmit data link underrun, TDLUDR, when
the TEXHDLC bit in the Master HDLC Configuration Register is a logic 0. When an
internal HDLC receiver is selected, TDLUDR is asserted when an internal HDLC
transmitter underruns. TDLUDR can be cleared (deasserted) by writing to the XFDL
Interrupt Status Register. TDLUDR is a programmable polarity, open-drain output. On
reset, TDLSIG/TDLUDR is TDLSIG. The TEXHDLC register should be programmed
after reset to the appropriate mode. When an external DMA is used, TDLUDR will be
configured as an active-low output and wired-ORed with the INT output and routed to the
supervising microprocessor. In that way, in the case of a transmit buffer underrun the
supervising microprocessor will be notified.
TDLCLK/
TDLINT
Transmit Data
Link Clock/
Transmit Data
Link Interrupt
O
207
C4
The TDLCLK/TDLINT will be transmit data link clock, TDLCLK, when the TEXHDLC bit in
the Master HDLC Configuration Register is a logic 1. When an external HDLC receiver is
selected, TDLCLK will provide the timing for the external maintenance data link inserted
by the DS3. TDLCLK is nominally a 28.2 KHz clock which is low for at least 1.9us per
cycle. TDLCLK is updated on the falling edge of the TOHCLK and cycles three times per
M-frame (one for each C-bit). The TDLCLK/TDLINT will be the transmit data link interrupt,
TDLINT, when the TEXHDLC bit in the Master HDLC Configuration Register is a logic 0.
When an internal HDLC receiver is selected, TDLINT is asserted when the last data byte
is written to the internal HDLC transmitter. A write to the XFDL Configuration Register will
end the current message transmission while a write to the XFDL Transmit Data Register
will provide more data. TDLINT is a programmable polarity, open-drain output. On reset,
TDLCLK/TDLINT is TDLINT. The TEXHDLC register should be programmed after reset
to the appropriate mode. When an external DMA is used, TDLINT will be configured as
an active-low output and wired-ORed with the INT output and routed to the supervising
microprocessor. In that way, the supervising microprocessor will be notified and can
service the XFDL.
TDLEMOI
Transmit Data
Link End Of
Message Input
I
204
D5
The transmit data link end of message input, TDLEMOI, is an alternate method for an
external DMA controller to signal the end of the transmitted message to the HDLC
transmitter. As the TDLEMOI is an alternative to writing the XFDL configuration register,
appropriately the TDLEMOI will set the EOM bit in the XFD: Configuration register. The
TDLEMOI input may be asserted before or after the write of the last byte, but must be
asserted before the next byte (within 210 us of the last assertion of TDLINT or the INT bit
in the XFDL Status Register). If no data transmission is pending, TDLEMOI is ignored.
PIN DESCRIPTION
8
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
TICLK
Transmit Input
Clock
I
1
C2
B3
The transmit input clock, TICLK, provides the timing for the DS3 input. TICLK is nominally
a 44.736 MHz, 50% duty cycle clock. TIMFP is sampled on the rising edge of TICLK.
TIMFP
Transmit Input
M-frame Frame
Pulse
I
208
The transmit M-frame pulse, TIMFP, provides the timing/alignment of the M-frame within
the DS3 data, TDAT. The first bit (X1) of the M-frame on TDAT will occur within several
TICLK cycle and will be confirmed by the output on TMFP. TIMFP may be pulled low if
this kind of feedback is not required. TIMFP is sampled on the rising edge of TICLK.
TOH
Transmit
Overhead Data
I
I
17
18
F2
F3
The transmit overhead data, TOH, represents the overhead bits (C, F, M, P, and X) that
may be inserted into the transmitted DS3. TOH is sampled on the rising edge of
TOHCLK.
TOHEN
Transmit
Overhead
Enable
The transmit overhead insertion, TOHEN, is the enable signal that is used in conjunction
with the TOH, data input. When TOHEN is high the associated data on TOH will be
inserted in to the DS3. When the TOHEN is low, the internal DS3 framer generates and
inserts the DS3 overhead bits into the output DS3 stream. TOHEN is sampled on the
rising edge of TOHCLK.
TOHFP
Transmit
Overhead
Frame Pulse
O
O
15
14
E3
E2
The transmit overhead frame position, TOHFP, marks the beginning of the first M-frame,
and aligns the TOH data to the DS3 M-frame. TOHFP will be high during the X1 overhead
bit position. TOHFP is updated on the falling edge of TOHCLK.
TOHCLK
Transmit
Overhead Clock
The transmit overhead clock, TOHCLK, provides the timing transmit overhead bits.
TOHCLK is nominally a 526 KHz clock. TOHFP is updated on the falling edge of
TOHCLK. TOH and TOHEN are sampled on the rising edge of TOHCLK.
JCLK
Transmit DS3
Clock
O
O
2
3
A1
B1
The transmit clock, TCLK, provides timing for other circuitry to synchronize with the DS3
transmitter. TCLK is nominally a 44.736 MHz, 50% duty cycle clock.
TPOS/TDAT
Transmit DS3
Positive Pulse/
Transmit DS3
Data
In dual rail mode, TPOS/TDAT, is TPOS and represents the positive pulses of a
B3ZS-encoded line. TPOS is updated on the falling edge of TCLK by default but may be
configured to update on the rising edge of TCLK. In single rail mode, TPOS/TDAT, is
TDAT and represents the unipolar DS3 output data. Like the TPOS, TDAT is updated on
the falling edge of TCLK by default but may be configured to update on the rising edge of
TCLK.
TNEG/TMFP
Transmit DS3
Negative Pulse/
Transmit Multi-
frame Pulse
O
5
C1
In dual rail mode, TNEG/TMFP, is TNEG and represents the negative pulses of a
B3ZS-encoded line. TNEG is updated on the falling edge of TCLK by default but may be
configured to update on the rising edge of TCLK. In single rail mode, TNEG/TMFP, is
TMFP and represents the transmit multi-frame pulse. TMFP will be high during the first bit
of the DS3 multiframe output on TDAT. TMFP is updated on the falling edge of TCLK by
default but may be configured to update on the rising edge of TCLK.
INT
CS
Interrupt
O
I
33
45
K3
INT is the output interrupt pin. When an interrupt occurs in any of the TSBs, DS2 FRMR,
DS3 FRMR, MX12, MX23, PMON, or RBOC, INT will go low, unless the interrupt is
masked. In order to clear INT, all pending interrupt TSBs must be read and cleared, oth-
erwise INT will remain low. INT is an open drain output so it can be wired-ORed with
other active-low open-drain output pins of the device.
Chip Select
M2
This active LOW input is used by a microprocessor to activate the microprocessor port.
CS must go low for at least once after powerup. If CS is not used it must be tied to an
inverted version of RST.
RD
Microprocessor
Read
I
I
57
56
R3
T3
This active low input controls the direction of the data bus lines (D0-7) during a micropro-
cessor access. When RD is low, D0-7 are output.
WR
Microprocessor
Write
This active low input controls the direction of the data bus lines (D0-7) during a micropro-
cessor access. When WR is low, D0-7 are input.
PIN DESCRIPTION
9
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 1 — PIN DESCRIPTIONS
TQFP
BGA
SYMBOL
D0-7
NAME
I/O
DESCRIPTION
PIN NO. Pin No.
Microprocessor
Data
I/O *See TQFP *See BGA These pins are the data bits of the microprocessor port.
table below tablebelow
for details
for deatils
A0-8
RST
ALE
VCC
VCC
GND
Microprocessor
Address
I
I
I
I
I
I
*See TQFP *See BGA These address lines access all internal memories.
table below tablebelow
for details
for details
Reset
58
P3
This input puts the IDT82V8313 into a reset state that clears the device internal counters
and registers. The RESET pin must be held LOW for a minimum of 100ns to properly
reset the device. This pin has a weak internal pull-up resistor.
Address Latch
Enable
46
M1
The address latch enable is an active high input that will latch the A0-7 address bus. The
ALE is used in a multiplexed address/data microprocessor environment. The ALE has a
weak internal pull-up resistor.
VCC
*See TQFP *See BGA This is the +3.3 Volt power supply for the core of the device.
table below tablebelow
for details
for details
VCC
*See TQFP *See BGA This is the +3.3 Volt power supply for the i/o of the device.
table below tablebelow
for details
for details
Ground
*See TQFP *See BGA Ground Rail.
table below tablebelow
for details
for details
TDI
JTAG Test
Serial Data In
I
O
I
P5
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by
an internal pull-up when not driven.
TDO
TRST
JTAG Test
Serial Data Out
R7
T4
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-
impedance state when JTAG scan is not enabled.
JTAG Test
Reset
Asynchronously initializes the JTAG Test Access Port controller by putting it in the Test-
Logic-Reset state. This pin is pulled HIGH by an internal pull-up when not driven. This pin
should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V71660 is in
the normal functional mode.
TCLK
TMS
JTAG Test
Clock
I
I
P11
R9
Provides the clock to the JTAG test logic.
JTAG Test
Mode Select
JTAG signal that controls the state transitions of the Test Access Port controller. This pin
is pulled HIGH by an internal pull-up when not driven.
PIN DESCRIPTION
10
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TQFP PIN NUMBER TABLE
SYMBOL
NAME
I/O
PIN NUMBER
RD1CLK1-28
Receive DS1
Clock
O
198, 193, 186, 180, 175, 170, 166, 159, 155, 151, 146, 142, 137, 133, 127, 122, 116, 110, 106, 102, 98, 91, 87, 82, 76,
71, 66, 62.
RD1DAT1-28 Receive DS1
Data
O
I
202, 195, 188, 182, 177, 173, 168, 161, 157, 153, 149, 144, 139, 135, 129, 124, 118, 114, 108, 104, 100, 94, 89, 84, 78,
74, 69, 64.
TD1CLK1-28
TD1DAT1-28
D0-7
Transmit DS1
Clock
201, 194, 187, 181, 176, 172, 167, 160, 156, 152, 148, 143, 138, 134, 128, 123, 117, 112, 107, 103, 99, 92, 88, 83, 77,
72, 68, 63.
Transmit DS1
Data
I
203. 196, 190, 184, 179, 174, 169, 162, 158, 154, 150, 145, 141, 136, 130, 126, 120, 115, 109, 105, 101, 97, 90, 86, 81,
75, 70, 65.
Microprocessor
Data
I/O 34, 35, 37, 38, 39, 41, 42, 44.
A0-8
Microprocessor
Address
I
47, 48, 49, 50, 51, 52, 53, 54, 55.
Vcc
Vcc
I
I
9, 43, 60, 95, 121, 164, 189, 199.
GND
Ground
8, 11, 27, 36, 59, 80, 96, 111, 132, 163, 183, 185, 191, 192, 200.
BGA PIN NUMBER TABLE
SYMBOL
NAME
I/O
PIN DESCRIPTION
RD1CLK1-28 Receive DS1
Clock
O
A 5, C6, A8, A9, D11, D12, C13, A14, B15, D16, E16, F16, G16, H16, J16, L13, M13, N14, R16, R15, T13, T12, T11,
P10, R8, P6, R5, R4.
RD1DAT1-28 Receive DS1
Data
O
I
A4, A6, B7, C9, B10, B11, B12, A13, A16, C15, D14, E14, J14, K15, L15, M15, N16, J15, R14, P13, T10, P9, P7, T6,
N4.
TD1CLK1-28
Transmit DS1
Clock
B4, B6, C7, B9, A10, A11, A12, B14, B16, C14, D13, E13, F13, H16, J15, K16, L16, M16, P15, T15, P14, N13, N12,
R10, P8, T7, N5, P4.
TD1DAT1-28 Transmit DS1
Transmit
I
A3, B5, A7, C8, C10, C11, C12, B13, A15, C16, D15, E15, F15, G15, H14, K14, L14, M14, N15, R16, T14, R13, R12,
R11, T9, T8, R6, T5.
D0-7
Microprocessor
Data
I/O K2, K1, L4, L3, L2, L1, M4, M3.
A0-8
Microprocessor
Address
I
N3, N2, P2, P1, R1,T1, T2, R2.
Vcc
Vcc
I
I
G4, H4, J4, K4, N6, N7, N8, N9, N10, N11, K13, J13, K13, G13, D6, D7, D8, D9, D10.
B8, D6, G7-G10, H7-H10, J7-J10, K7-K10.
GND
Ground
PIN DESCRIPTION
11
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
PIN DESCRIPTION
12
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
REGISTER MEMORY MAP
TABLE 2 — REGISTER MEMORY MAP
Register
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
00H
R/W DS3RCACT DS3TCACT DS2TCACT
-
-
-
-
Reset
ID0
Master Reset/Clock
Status
01H
02H
03H
04H
05H
06H
R
ID7
ID6
ID5
ID4
BYP5
-
ID3
ID2
ID1
BYP2
Revision/Global
PMON Update
R/W
R/W
R/W
R/W
R/W
EXD2CLK
BYP7
BYP6
BYP4
BYP3
BYP1
Master Bypass
Configuration
REXHDLC TEXHDLC
-
-
REOMPOL TUDRPOL
RINTPOL
LLBE
TINTPOL Master HDLC
Configuration
-
-
LINEAIS1
TFALL
LINEAIS2
TUNI
DLBE
Master Loopback
Configuration
-
-
-
TINV
REDO
RINV
RFALL
Master Interface
Configuration
TNR
RNR
ALTFEBE
RED2ALME DS2ALME RED3ALME DS3ALME Master Alarm
Enable/Network
Requirement Bit
07H
08H
R/W
R
-
-
-
-
DBCTRL
-
HIZDATA
HIZIO
RBOC
Master Test
REG2
REG3
XFDLINT
MX23
DS3FRMR
RFDLINT
RFDLEOM
Master Interrupt
Source #1
09H
0AH
R
R
XFDLUDR DS2FRMR7 DS2FRMR6 DS2FRMR5 DS2FRMR4 DS2FRMR3 DS2FRMR2 DS2FRMR1 Master Interrupt
Source #2
DS3PMON
MX12 7
MX12 6
MX12 5
MX12 4
MX12 3
MX12 2
MX12 1
Master Interrupt
Source #3
0BH
0CH
-
-
-
-
-
-
-
-
-
-
-
Reserved
R/W
CBTRAN
AIS
IDL
FERF
SBOW
CBIT
DS3 TRAN
Configuration
0DH
R/W
-
DLOS
DLCV
-
DFERR
DMERR
DCPERR
-
DPERR
-
DFEBE
-
DS3 TRAN
Diagnostic
0EH -
11H
-
-
-
-
-
-
-
-
-
Reserved
11H
R/W
-
-
INTE
-
INTR
-
OVR
DS3 PMON Interrupt
Enable/Status
12H -
13H
-
-
-
-
-
Reserved
14H
15H
16H
17H
18H
R
LCV7
LCV15
FERR7
-
LCV6
LCV14
FERR6
-
LCV5
LCV13
FERR5
-
LCV4
LCV12
FERR4
-
LCV3
LCV11
FERR3
-
LCV2
LCV10
FERR2
-
LCV1
LCV9
FERR1
FERR9
EXZS1
LCV0
LCV8
DS3 PMON LCV
Count (LSB)
R
DS3 PMON LCV
Count (MSB)
R
FERR0
FERR8
EXZS0
DS3 PMON FERR
Count (LSB)
R
DS3 PMON FERR
Count (MSB)
R
EXZS7
EXZS6
EXZS5
EXZS4
EXZS3
EXZS2
DS3 PMON EXZS
Count (LSB)
REGISTER MEMORY MAP
13
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 2 — REGISTER MEMORY MAP
Register
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
19H
R
EXZS15
EXZS14
EXZS13
EXZS12
EXZS11
EXZS10
EXZS9
EXZS8
PERR0
PERR8
CPERR0
CPERR8
FEBE0
FEBE8
EN
DS3 PMON EXZS
Count (MSB)
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
R
R
PERR7
PERR6
PERR5
PERR13
CPERR5
CPERR13
FEBE5
FEBE13
-
PERR4
PERR12
CPERR4
CPERR12
FEBE4
FEBE12
EOM
PERR3
PERR11
CPERR3
CPERR11
FEBE3
FEBE11
INTE
PERR2
PERR10
CPERR2
CPERR10
FEBE2
FEBE10
ABT
PERR1
PERR9
CPERR1
CPERR9
FEBE1
FEBE9
CRC
DS3 PMON PERR
Count (LSB)
-
-
DS3 PMON PERR
Count (MSB)
R
CPERR7
CPERR6
DS3 PMON CPERR
Count (LSB)
R
-
-
DS3 PMON CPERR
Count (MSB)
R
FEBE7
FEBE6
DS3 PMON FEBE
Count (LSB)
R
-
-
-
-
DS3 PMON FEBE
Count (MSB)
R/W
R/W
R/W
XFDL TSB
Configuration
-
-
-
-
-
-
INT
UDR
XFDL TSB Interrupt
Status
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
XFDL TSB Transmit
Data
23H
24H
--
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
R/W
TR
EN
RFDL TSB
Configuration
25H
R/W
-
-
-
-
-
INTC1
INTC0
INT
RFDL Interrupt
Control/Status
26H
27H
R
R
FE
OVR
RD6
FLG
RD5
EOM
RD4
CRC
RD3
NVB2
RD2
NVB1
RD1
NVB0
RD0
RFDL TSB Status
RD7
RFDL TSB Receive
Data
28H
29H
R/W
R/W
-
-
-
-
-
LBCOD1
DAIS4
LBCODE0
DAIS3
CBE
INTE
MX23 Configuration
DAIS7
DAIS6
DAIS5
DAIS2
DAIS1
MX23 Demux AIS
Insert
2AH
2BH
R/W
R/W
-
-
MAIS7
LBA7
MAIS6
LBA6
MAIS5
LBA5
MAIS4
LBA4
MAIS3
LBA3
MAIS2
LBA2
MAIS1
LBA1
MX23 Mux AIS Insert
MX23 Loopback
Activate
2CH
2DH
2EH
R/W
R
0
-
ILBE7
ILBE6
LBRD6
LBRI6
-
ILBE5
LBRD5
LBRI5
-
ILBE4
LBRD4
LBRI4
-
ILBE3
LBRD3
LBRI3
-
ILBE23
LBRD2
LBRI2
-
ILBE1
LBRD1
LBRI1
-
MX23 Loopback
Request Insert
LBRD7
MX23 Loopback
Request Detect
R
-
LBRI7
MX23 Loopback
Request Interrupt
2FH -
30H
-
-
-
-
Reserved
31H
R/W
-
BC5
BC4
BC3
BC2
BC1
BC0
FEAC XBOC Code
June 3, 2004
REGISTER MEMORY MAP
14
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 2 — REGISTER MEMORY MAP
Register
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
32H
R/W
-
-
-
-
-
IDLE
AVC
BOCE
FEAC RBOC
Configuration/
Interrupt Enable
33H
34H
R
IDLEI
BOCI
FDET
BOC5
BOC4
M3O8
BOC3
UNI
BOC2
REFR
BOC1
AISC
BOC0
CBE
FEAC RBOC
Interrupt Status
R/W
R/W
AISPAT
MBDIS
DS3 FRMR
Configuration
35H
ACE=0
ACE=1
DS3 FRMR Interrupt
Enable/Additional
COFAE
-
REDE
-
CBITE
AISONES
FERFE
BPVO
IDLE
EXZSO
AISE
EXTYPE
OOFE
SALGO
LOSE
ALGOTYPE Configuration
36H
R
COFAI
REDI
CBITI
FERFI
IDLI
AISI
OOFI
LOSI
DS3 FRMR Interrupt
Status
37H
R/W
-
ACE
-
REDV
-
CBITV
-
FERFV
-
IDLV
-
AISV
-
OOFV
-
LOSV
-
DS3 FRMR Status
Reserved
38H -
3FH
40H
41H
42H
43H
44H
R/W
R/W
R
G747
-
-
-
-
-
WORD
REDE
REDI
REDV
-
M2O5
FERFE
FERFI
FERFV
-
MDBIS
RESE
RESI
RESV
-
REF
AISE
AISI
-
-
DS2 #1 FRMR PERR
Configuration
COFAE
OOFE
OOFI
OOFV
INTR
-
DS2 #1 FRMR PERR
Interrupt Enable
COFAI
-
-
DS2 #1 FRMR PERR
Interrupt Status
R
-
-
AISV
INTE
DS2 #1 FRMR PERR
Status
R/W
OVR
DS2 #1 FRMR
Monitor Interrupt
Enable/Status
45H
46H
47H
48H
R
R
FERR7
PERR7
-
FERR6
PERR6
-
FERR5
PERR5
-
FERR4
PERR4
PERR12
FINV
FERR3
PERR3
PERR11
ZAIS
FERR2
PERR2
PERR10
XFERF
FERR1
PERR1
PERR9
XRES
FERR0
PERR0
PERR8
INTE
DS2 #1 FRMR FERR
Count
DS2 #1 FRMR PERR
Count (LSB)
R
DS2 #1 FRMR PERR
Count (MSB)
R/W
G747
PINV
MINV
DS2 #1 MX12
Configuration and
Control
49H
R/W
-
-
-
-
-
-
LBCODE1
LBCODE0 DS2 #1 MX12
Loopback Code
Select
4AH
4BH
4CH
R/W
R/W
R
MAIS4
ILBR4
LBRI4
MAIS3
ILBR3
LBRI3
MAIS2
ILBR2
LBRI2
MAIS1
ILBR1
LBRI1
DAIS4
LBA4
DAIS3
LBA3
DAIS2
LBA2
DAIS1
DS2 #1 MX12 AIS
Insert
LBA1
DS2 #1 MX12
Loopback Active
LBRD4
LBRD3
LBRD2
LBRD1
DS2 #1 MX12
Loopback Interrupt
REGISTER MEMORY MAP
15
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 2 — REGISTER MEMORY MAP
Register
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
4DH
R/W
TXESEL4
TXESEL3
TXESEL2
TXESEL1
RXESEL4
RXESEL3
RXELES2
RXESEL2 DS1 #1 Transmit and
Receive Edge Select
50H -
57H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS2 #4 MX12
Registers
58H -
5DH
DS2 #2 MX12
Registers
60H -
67H
DS2 #3 FRMR
Registers
68H -
6DH
DS2 #3 MX12
Registers
70H -
77H
DS2 #4 FRMR
Registers
78H -
7DH
DS2 #4 MX12
Registers
80H -
87H
DS2 #5 FRMR
Registers
88H -
8DH
DS2 #5 MX12
Registers
90H -
97H
DS2 #6 FRMR
Registers
98H -
9DH
DS2 #6 MX12
Registers
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
G747
COFAE
COFAI
-
-
WORD
REDE
REDI
REDV
-
FERR5
PERR5
-
M2O5
FERFE
FERFI
FERFV
-
FERR4
PERR4
PERR12
MDBIS
RESE
RESI
RESV
-
FERR3
PERR3
PERR11
REF
AISE
AISI
AISV
INTE
FERR2
PERR2
PERR10
-
-
-
-
COFAE
OOFE
OFFI
OOFV
INTR
FERR1
PERR1
PERR9
-
-
-
R/W
R/W
-
DS2 #7 FRMR
Registers
-
OVR
FERR7
PERR7
-
FERR6
PERR6
-
FERR0
PERR0
PERR8
A8H
A9H
AAH
ABH
ACH
ADH
G747
-
MAIS4
ILBR4
LBR4
TXESEL4
PINV
-
MAIS3
ILBR3
LBR3
TXESEL3
MINV
-
MAIS2
ILBR2
LBR2
FINV
-
MAIS1
ILBR1
LBR1
XAIS
-
DAIS4
LBA4
LBDR4
RXESEL4
XFERF
-
DAIS3
LBA3
LBDR3
RXESEL3
XREF
LBCODE1
DAIS2
LBA2
LBDR2
INTE
LBCODE0
DAIS1
LBA1
LBDR1
RXESEL1
DS2 #7 MX12
Registers
TXESEL2
TXESEL1
RXESEL2
AEH -
FFH
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
Reserved
100H -
1FFH
-
-
-
-
-
Note:
All Reserved Registers should not be read/written
REGISTER MEMORY MAP
16
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
REGISTER DESCRIPTIONS
MASTER RESET/CLOCK STATUS
Read/Write Addresses: 00H
Reset Value:
00H
7
6
5
4
0
3
0
2
0
1
0
0
DS3RCACT DS3TCACT DS2TCACT
RESET
Bit
Name
DS3RCACT
Description
The DS3 Receive Clock Activity (DS3RCACT) bit indicates at least one LOW to HIGH transaction has occurred on the RCLK input
7
6
5
(DS3 Receive Clock since the last read of this register. The DS3RCACT bit is set to a logic 1 by a rising edge on the RCLK input and is cleared to a logic
Activity)
0 by a read of this register.
DS3TCACT
The DS3 Transmit Clock Activity (DS3TCACT) bit indicates at least one LOW to HIGH transaction has occurred on the TD2CLK input
(DS3 Transmit Clock since the last read of this register. The DS3TCACT bit is set to a logic 1 by a rising edge on the TICLK input and is cleared to a logic
Activity)
0 by a read of this register.
DS2TCACT
The DS2 Transmit Clock Activity (DS2TCACT) bit indicates at least one LOW to HIGH transaction has occurred on the TICLK input
(DS2 Transmit Clock since the last read of this register. The DS2TCACT bit is set to a logic 1 by a rising edge on the TD2CLK input and is cleared to a
Activity)
logic 0 by a read of this register. Note that if the TD2CLK signal is absent for a period of time (i.e., TD2CLK clock failure), the D3MX
must be reset once the TD2CLK signal is restored.
4-1 Unused
Must be zero for normal operation.
0
RESET
(Software Reset)
The RESET bit implements a software reset. If the RESET bit is a logic1, the entire D3MX is held in reset. This bit is not self-clearing;
therefore, a logic 0 must be written to bring the D3MX out of reset. Holding the D3MX in a reset clears the RESET bit, thus
deasserting the software reset.
REVISION/GLOBAL PMON UPDATE
Read/Write Addresses: 01H
Reset Value:
00H
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit
Name
Description
7-0 ID 7-0
The version identification bits ID 7-0, are set to a fixed value representing the version number of the D3MX. These bits can be read by
software to determine the version number. Writing to this register causes all performance monitor counters (DS3 and DS2/G.747) to
be updated simultaneously.
(Identification Bits)
REGISTER DESCRIPTION
17
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER BYPASS CONFIGURATION
Read/Write Addresses: 02H
Reset Value:
00H
7
6
5
4
3
2
1
0
EXD2CLK
BYP7
BYP6
BYP5
BYP4
BYP3
BYP2
BYP1
Bit
Name
EXD2CLK
Description
7
The EXD2CLK bit selects between an internally generated DS2 clock and the clock input on the TD2CLK pin. If EXD2CLK is a logic
0, the DS2 clock for the multiplexing side becomes the generated clock derived from the DS3 transmit TICLK clock. The generated
DS2 clock is nominally 6.306272 MHz while in C-bit parity mode and while in M23 mode, it is nominally 6.311993 MHz. If EXD2CLK
is a logic 1, the transmit DS2 clock becomes TD2CLK.
(External DS2 CLK)
6-0 BYP 7-1
(M12 Bypass)
The BYP 7-1bits allow for each of the seven MX12blocks to be individually bypassed so that the external DS2 may be multiplexed
and duplexed directly without the intermediate M12 multiplexing. If BYP[n] is a logic 1, the following applies:
1. A nominally 6.312 MHz clock is expected on TD1CLK(4n).
2. A data stream synchronous to TD1CLK(4n) is expected on TD1DAT(4n).
3. The clocks on TD1CLK(4n-1), TD1CLK(4n-2) and TD1CLK(4n-3) have no effect and should be tied to ground.
4. The data streams in TD1DAT(4n-1), TD1CLK(4n-2) and TD1CLK(4n-3) are ignored and should be tied to ground.
5. A nominally 6.312 MHz clock is presented on RD1CLK(4n).
6. A data stream synchronous to RD1CLK(4n) is presented on RD1DAT(4n).
7. The signals on RD1CLK(4n-1), RD1CLK(4n-2),RD1CLK(4n-3), RD1DAT(4n-1), RD1DAT(4n-2) and
RD1DAT(4n-3) are always LOW.
REGISTER DESCRIPTION
18
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER HDLC CONFIGURATION
Read/Write Addresses: 03H
Reset Value:
40H
7
6
5
0
4
0
3
2
1
0
REXHDLC
TEXHDLC
REOMPOL
TUDRPOL
RINTPOL
TINTPOL
Bit
Name
REXHDLC
(Receive External
HDLC)
Description
7
The state of the receive external HDLC (REXHDLC) bit determines weather the C-bit parity path maintenance data link is terminated
by the internal HDLC receiver or by an external HDLC receiver. When the REXHDLC bit is a logic 0, the internal HDLC receiver is
selected; the RDLCLK/RDLINT pin is configured to output the interrupt signal (RDLINT) from the internal HDLC receiver and the
RDLSIG/RDLEOM pin is configured to output the end-of-message signal (RDLEOM) from the internal HDLC receiver. When the
REXHDLC bit is a logic 1, the use of an external HDLC receiver is selected; the RDLSIG/RDLEOM pin is configured to output the
data stream (RDLSIG) and the RDLCLK/RDLINT pin is configured to output the data link clock signal (RDLCLK). The REXHDLC bit
is cleared to logic 0 upon reset.
6
TEXHDLC
(Transmit External
HDLC)
The state of the transmit external HDLC (TEXHDLC) bit determines weather the C-bit parity path maintenance data link is sourced by
the internal HDLC transmitter or by an external HDLC transmitter. When the TEXHDLC bit is a logic 0, the internal HDLC transmitter
is selected; the TDLCLK/TDLINT pin is configured as an output to present the interrupt signal (TDLINT) from the internal HDLC trans-
mitter and the TDLSIG/TDLUDR pin is configured to output the underrun signal (TDLUDR) from the internal HDLC transmitter.
When the TEXHDLC bit is a logic 1, the use of an external HDLC transmitter is selected; the TDLSIG/TDLUDR pin is configured to
output the data link data stream (TDLSIG) and the TDLCLK/TDLINT pin is configured to output the data link clock signal (TDLCLK).
The TEXHDLC bit is set to logic 1 upon reset.
5-4 Unused
Must be zero for normal operation.
3
2
1
0
REOMPOL
The Receive End-of-Message Polarity (REOMPOL) bit determines the assertion level of the RDLEOM output. If REOMPOL is a logic
(Receive End-of-Mes- 0, the RDLEOM output is an active LOW open-drain output. If REOMPOL is a logic 1, the RDLEOM output is asserted HIGH and
sage Polarity)
always has a strong drive. If the REXHDLC bit is a logic 1, this bit has no effect.
TUDRPOL
The Transmit Underflow Polarity (TUDRPOL) bit determines the assertion level of the TDLUDR output. If TUDRPOL is a logic 0, the
(Transmit Underflow TDLUDR output is an active LOW open-drain output. If TUDRPOL is a logic 1, the TDLUDR output is asserted HIGH and always has
Polarity)
a strong drive. If the TEXHDLC bit is a logic 1, this bit has no effect.
RINTPOL
(Receive Interrupt
Polarity)
The Receive Interrupt Polarity (RINTPOL) bit determines the assertion level of the RDLINT output. If RINTPOL is a logic 0, the
RDLINT output is an active LOW open-drain output. If RINTPOL is a logic 1, the RDLINT output is asserted HIGH and always has a
strong drive. If the REXHDLC bit is a logic 1, this bit has no effect.
TINTPOL
(Transmit Interrupt
Polarity)
The Transmit Interrupt Polarity (TINTPOL) bit determines the assertion level of the TDLINT output. If TINTPOL is a logic 0, the
TDLINT output is an active LOW open-drain output. If TINTPOL is a logic 1, the TDLINT output is asserted HIGH and always has a
strong drive. If the TEXHDLC bit is a logic 1, this bit has no effect.
REGISTER DESCRIPTION
19
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER LOOPBACK CONFIGURATION
Read/Write Addresses: 04H
Reset Value:
00H
7
6
0
5
0
4
0
3
2
1
0
0
LINEAIS1
LINEAIS2
LLBE
DLBE
Bit
Name
Description
7-4 Unused
Must be zero for normal operation.
3-2 LINEAIS 1-2
The line AIS (LINEAIS 1-0) bits allow the generation of various AIS patterns on the TDAT output when TUNI is set to logic 1, or on the
TPOS and TNEG outputs when TUNI is set to logic0, independent of the data stream being transmitted. The LINEAIS 1-0 option is
expected to be used when the diagnostic loopback is invoked, ensuring that only a valid DS3 stream enters the network. The LIN-
EAIS 1-0 bits select one of the following AIS patterns for transmission:
(Line Alarm Indica-
tion Signal)
LINEAIS 1-0 AIS Transmitted
00
01
10
11
none
Framed, repetitive 1010... pattern with C-bits forced to logic 0
Framed, repetitive 1111... pattern with C-bits forced to logic 0
Unframed, all-ones pattern
The LINEAIS 1-0=01 option is compatible with TR-TSY000009 Section 3.7 objectives.If the intention is to loopback the AIS, the AIS
bit in the DS3 TRAN Configuration Register should be written instead.
1
0
LLBE
The diagnostic loopback enable (LLBE) bit allows the looping back of the received DS3 into the transmitted DS3 path. If the LLBE bit
(Diagnostic loopback is a logic 1, the RPOS, RNEG, and RCLK signals are connected internally to replace the signals normally output on the TPOS,
Enable)
TNEG, and TCLK pins.
DLBE
(Diagnostic Loop-
back Enable)
The diagnostic loopback enable (DLBE) bit allows the looping back of the transmitted DS3 into the receive DS3 path for diagnostic
purposes. If the DLBE bit is a logic 1, the TPOS, TNEG, and TCLK signals are connected internally to replace the signals normally
input on the RPOS, RNEG, and RCLK pins.
REGISTER DESCRIPTION
20
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER INTERFACE CONFIGURATION
Read/Write Addresses: 05H
Reset Value:
00H
7
6
0
5
0
4
3
2
1
0
0
TINV
TRISE
TUNI
RINV
RFALL
Bit
Name
Description
7-5 Unused
Must be zero for normal operation.
The transmit invert (TINV) bit enables data inversion of the DS3 transmit interface. When TINV is a logic 1, the TPOS and TNEG
4
3
2
1
0
TINV
(DS3 Transmit Edge signals are active LOW. When TINV is a logic 0, the TPOS and TNEG signals are active HIGH. Inversion only takes place when the
Invert)
DS3 transmit interface is configured for dual rail operation.
TRISE
The transmit falling edge select (TRISE) bit configures the updating edge used on the DS3 transmit interface. When TRISE is a logic
(DS3 Transmit Edge 1, the DS3 transmit interface is updated on the rising edge of TCLK. When TRISE is a logic 0, the DS3 transmit interface is updated
Falling)
on the falling edge of TCLK.
TUNI
(DS3Transmit
Unipolar)
The transmit unipolar (TUNI) bit configures the DS3 transmit interface for unipolar or dual rail operation. When TUNI is a logic 1, the
DS3 transmit interface is configured as TDAT and TMFP. When TUNI is a logic 0, the DS3 transmit interface is configured as TPOS
and TNEG.
RINV
(DS3 Receive Edge
Invert)
The receive invert (RINV) bit enables data inversion of the DS3 receive interface. When RINV is a logic 1, the RPOS and RNEG
signals are active LOW. When RINV is a logic 0, the RPOS and RNEG signals are active HIGH. Inversion only takes place when the
DS3 receive interface is configured for dual rail operation.
RFALL
The receive falling edge select (RFALL) bit configures the sampling edge used on the DS3 receive interface. When RFALL is a logic
1, the DS3 receive interface is sampled on the falling edge of RCLK. When RFALL is a logic 0, the DS3 receive interface is sampled
on the rising edge of RCLK.
(DS3 Receive Edge
Falling)
REGISTER DESCRIPTION
21
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER ALARM ENABLE/NETWORK REQUIREMENT BIT
Read/Write Addresses: 06H
Reset Value:
80H
7
6
5
4
3
2
1
0
TNR
RNR
ALTFEBE
REDO
RED2ALME
DS2ALME
RED3ALME
DS3ALME
Bit
Name
Description
The Transmit Network Requirement (TNR) bit determines the value inserted into the Network Requirement (N ) bit transmitted in the
7
TNR
r
(Transmit Network
Requirement)
second C-bit in M-subframe 1 when in DS3 C-bit parity mode. A logic 1 in the TNR bit causes a one to be transmitted in the N
r
overhead bit timeslot. The TNR bit is set to a logic 1 upon either a hardware or software reset. If C-bit parity is not selected, the TNR
bit has no effect. Note that the serial control input, TOHEN, takes precedence over the effect of this bit when TOHEN is asserted
during the Network Requirement Bit position. While TOHEN is asserted at the second C-bit position of M-subframe 1, the data on the
TOH input is transmitted in the N , bit.
r
6
5
RNR
(Receive Network
Requirement)
The Receive Network Requirement (RNR) bit reflects the real time value of the Network Requirement (N ) bit presented in the second
r
C-bit in M-subframe 1 when in DS3 C-bit parity mode. The RNR bit is a logic 1 if a logic one occurs in the N overhead bit timeslot. If
r
C-bit parity is not selected, the value of RNR is meaningless and random.
ALTFEBE
(Alternate Far End
Block Error)
The Alternate Far End Block Error (ALTFEBE) bit selects the error conditions detected to define a FEBE indication. If ALTFEBE is a
logic 1, a FEBE indication is generated in the outgoing C-bit Parity DS3 transmit stream if a C-bit parity error occurred in the last
received M-frame. If no C-bit Parity error occurred, no FEBE is generated. If ALTFEBE is a logic 0, a FEBE indication is generated
if either one or more framing bit errors or a C-bit parity error has occurred in the last received M-frame. If no framing bit errors nor
C-bit parity errors have occurred, then no FEBE is generated.
4
3
REDO
The RED DS2 Alarm Output Enable (REDO) bit selects the type of signal output on the ROOF/RRED pin. If REDO is a logic 1, DS3
(RED DS2 Alarm Out- RED status signal is available on the ROOF/RRED output pin. If REDO is a logic O, DS3 OOF status signal is available on the
put Enable)
ROOF/RRED output pin.
RED2ALME
(RED DS2 Alarm
Enable)
The RED DS2 Alarm Enable (RED2ALME) bit works in conjunction with the DS2ALME and enables detection of DS2 RED condition
to be used in place of DS2/G.747 out-of-frame in the above criteria for demultiplexed AIS generation. When DS2ALME is set to logic
1 and RED2ALME is set to logic 1, the occurrence of OOF for 53 consecutive DS2/G.747 “M-frames” causes a DS2 RED alarm
condition and generates the DS1 AIS. When DS2ALME is set to logic 1 and RED2ALME is set to 0, any occurrence of OOF
generates the DS1 AIS. If DS3ALME is a logic 0, the RED3ALME bit is ignored.
2
DS2ALME
(DS2 Alarm Enable)
The DS2 Alarm Enable (DS2ALME) bit allows the automatic generation of AIS in the DS1s demultiplexed from a DS2 or G.747
stream which is in an alarm condition. If DS2ALME is a logic 1, a DS2 or G.747 out-of-frame (OOF) condition (i.e. immediately after
2-of-n F-bit errors where n is 4 or 5, or 3-of-4 M-frames containing M-bit errors for DS2, or immediately after 4 consecutive framing
word errors for G.747) or detection of DS2 or G.747 AIS causes each of the associated DS1s to be replaced by an unframed all ones
pattern immediately. If DS2ALME is a logic 0, AIS can still be generated in the demultiplexed DS1s under software control by setting
the bits in the appropriate MX12 AIS Insert Register. Note that the removal of the auto all-ones insertion is performed upon the first
DS2 M-frame or G.747 frame pulse after the DS2 FRMR has found frame alignment.
1
0
RED3ALME
(RED DS3 Alarm
Enable)
The RED DS3 Alarm Enable (RED3ALME) bit works in conjunction with the DS3ALME and enables detection of DS3 RED alarm
condition to be used in place of DS3 loss if signal and DS3 out-of-frame in the above criteria for demultiplexed AIS generation. When
DS3ALME is set to logic 1 and RED3ALME is set to logic 1, the occurrence of LOS or OOF for 127 consecutive M-frames (or 21
consecutive M-frames, if FDET is set to logic 1 in the DS3 FRMR configuration register) causes a DS3 RED alarm condition and
generates the DS2 AIS. When DS3ALME is set to logic 1 and RED3ALME is set to 0, any occurrence of LOS or OOF generates the
DS2 AIS. If DS3ALME is a logic 0, the RED3ALME bit is ignored.
DS3ALME
(DS3 Alarm Enable)
The DS3 Alarm Enable (DS3ALME) bit allows the automatic generation of AIS in all of the demultiplexed DS2s upon a DS3 alarm
condition. If DS3ALME is a logic 1, a DS3 loss of signal (>175 zeros), a DS3 out-of-frame (OOF) condition (i.e. immediately after
3-of-n F-bit errors where n is 8 or 16, or 3-of-4 M-frames containing M-bit errors). DS3 idle code detection or DS3 AIS detection
causes all of the DS2s to be replaced by an unframed all ones pattern immediately. Generation of AIS continues while the detected
alarm condition persists. If DS3ALME is a logic 0, AIS can still be generated in the demultiplexed DS2s under software control by
setting the bits in the MX23 Demux AIS Insert Register.
REGISTER DESCRIPTION
22
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER TEST
Read/Write Addresses: 07H
Reset Value:
00H
7
6
0
5
0
4
0
3
2
0
1
0
0
DBCTRL
HIZDATA
HIZIO
Bit
Name
Description
7-4 Unused
Must be zero for normal operation.
3
DBCTRL
The DBCTRL bit is used to pass control of the data bus to the CS pin. While the DBCTRL is set, holding the CS pin HIGH causes the
(Data Bus Control) D2MX to drive the data bus and holding the CS pin LOW tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBC-
TRL bit is used to measure the drive capability of the data bus driver pads.
2
Unused
Must be zero for normal operation.
1- 0 HIZDATA, HIZIO
(Hi-Z Data)
The HIZDATA and HIZIO bits control the tri-state modes of the D3MX. While the HIZIO bit is a logic 1, all output pins of the D3MX. While
the HIZIO bit is a logic 1, all output pins of the D3MX except the data bus are held in a HIGH-impedance state. The microprocessor inter-
face is sill active. While the HIZDATA bit is a logic 1, the data bus is also held in a HIGH-impedance state which inhibits microprocessor
read cycles.
(Hi-Z I/O)
REGISTER DESCRIPTION
23
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER INTERRUPT SOURCE #1
Read/Write Addresses: 08H
Reset Value:
00H
7
6
5
4
3
2
1
0
REG2
REG3
XFDLINT
MX23
DS3FRMR
RFDLINT
RFDLEOM
RBOC
Bit
Name
Description
7
6
5
REG2
(Red Alarm 2)
If REG2 bit is a logic 1, at least one bit in the Master Interrupt Source #2 Register is set, that is, at least one DS2 Farmer or the XFDL
is generating an interrupt.
REG3
(Red Alarm 3)
If REG3 bit is a logic 1, at least one bit in the Master Interrupt Source #3 Register is set, that is, at least one M12 Multiplexer is gen-
erating an interrupt.
XFDLINT
(Transmit Facility
Data Link Interrupt)
If XFDLINT bit is a logic 1, the XDFL TSB is generating an interrupt (also visible on the TDLINT output when configured for internal
HDLC, i.e. TEXHDLC=0)
4
3
2
MX23
(MX23 TX Interrupt)
If MX23 bit is a logic 1, the MX23 FRMR TSB is generating an interrupt due to the detection of a DS2 loopback request.
DS3FRMR
If DS3FRMR bit is a logic 1, the DS3 FRMR TSB is generating an interrupt. Register 36H should be read to determine which event in
(D3 Framer Interrupt) DS3 FRMR has caused to interrupt.
RFDLINT
If RFDLINT bit is a logic 1, the RFDL TSB is generating an interrupt (also visible on the RFDLINT output when configured for internal
(Receive FacilityData HDLC, i.e. REXHDLC=0).
Link Interrupt)
1
0
RFDLEOM
If RFDLEOM bit is a logic 1, the RFDL TSB is generating an interrupt due to an end of message occurrence (also visible on the
(Receive FacilityData RDLEOM output when configured for internal HDLC, i.e. REXHDLC=0).
Link End of Message
Interrupt)
RBOC
If RBOC bit is a logic 1, the FEAC RBOC TSB is generating an interrupt. Register 33H should be read to determine which event in
(Receive Bit Oriented RBOC has caused to interrupt.
Code Interrupt)
REGISTER DESCRIPTION
24
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MASTER INTERRUPT SOURCE #2
Read/Write Addresses: 09H
Reset Value:
00H
7
6
5
4
3
2
1
0
XFDLUDR DS2FRMR 7 DS2FRMR 6 DS2FRMR 5 DS2FRMR 4 DS2FRMR 3 DS2FRMR 2 DS2FRMR 1
Bit
Name
XFDLUDR
(Transmit Facility
Data Link Underrun
Interrupt)
Description
7
This bit allows software to determine whether the XFDL TSB produced an underrun condition.
If the XFDLUDR bit is a logic 1, the XFDL TSB is generating an interrupt due to an underrun of the transmit data buffer (also visible
on the TDLUDR output when configured for internal HDC, i.e. TEXHDLC=0).
Reading this register does not remove the interrupt indication; the corresponding TSB’s interrupt status register must be read to
remove the interrupt indication.
6-0 DS2FRMR 7-1
(DS2 Framer
These bits allow software to determine which of the seven DS2 framer TSBs produced the interrupt on the INTB output pin.
Reading this register does not remove the interrupt indication; the corresponding TSB’s interrupt status register must be read to
remove the interrupt indication.
Interrupt)
MASTER INTERRUPT SOURCE #3
Read/Write Addresses: 0AH
Reset Value:
00H
7
6
5
4
3
2
1
0
DS3PMON
MX12 7
MX12 6
MX12 5
MX12 4
MX12 3
MX12 2
MX12 1
Bit
Name
DS3PMON
Description
DS3 PMON TSB produced the interrupt on the INTB output pin.
7
(DS3 Performance
Monitor Interrupt)
6-0 M12 7-1
(M12 Performance
Monitor Interrupt)
These bits correspond to which M12 TSB produced an interrupt. Reading this register does not remove the interrupt indication; the
corresponding TSB’s interrupt status register must be read to remove the interrupt indication.
REGISTER DESCRIPTION
25
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 TRANSMIT CONFIGURATION
Read/Write Addresses: 0CH
Reset Value:
00H
7
6
5
4
3
2
0
1
0
0
CBTRAN
AIS
IDL
FERF
SBOW
CBIT
Bit
Name
CBTRAN
(DS3 C-Bit Transmit
Configuration)
Description
7
The CBTRAN bit controls the C-bits during AIS transmission. When CBTRAN is a logic 0, the C-bits are overwritten with zeros dur-
ing AIS transmission (as is currently specified in ANSI T1.107a Section 8.1.3.1). The only exception is the network requirement bit,
which is forced to the TNR register value. When CBTRAN is a logic 1 and the M23 application is enabled the C-bits pass through
transparently during AIS transmission. When CBTRAN is a logic 1, and the C-bit parity application is enabled, the C-bits are over-
written with the appropriate C-bit parity functions during AIS transmission.
6
5
4
3
AIS
The AIS bit enables transmission of the alarm indication signal. When AIS is a logic 1, the transmit DS3 payload (on the TDAT/
TPOS and TNEG outputs) is overwritten with the pattern 1010...
(DS3Alarm Indication
Signal Configuration)
IDL
The IDL bit enables transmission of the alarm indication signal and the idle signal. When IDL is a logic 1, the transmit DS3 payload
is overwritten with the pattern 1100...
(DS3 Idle Pattern
Configuration)
FERF
(DS3 Far End Receive
Failure Configuration)
The FERF bit enables transmission of far end receive failure in the outgoing DS3 stream. When FERF is a logic 1, the X1 and X2
overhead bit positions in the DS3 stream are set to logic 0. When FERF is a logic 0, the X1 and X2 overhead bit positions in the
DS3 stream are set to logic 1.
SBOW
The SBOW bit selects weather to insert the bit from the TOH input into the stuff opportunity bit or into the F4 bit. When SBOW is a
logic 1, the bit from the TOH input is inserted into the stuff opportunity bit. When SBOW is a logic 0, the bit from the TOH input is
inserted into the F4 bit.
(DS3 Stuff Bit
Opportunity Window
Configuration)
2-1 Unused
Must be zero for normal operation.
0
CBIT
(DS3 C-Bit parity
Configuration)
The CBIT bit enables the C-bit parity application. When CBIT is a logic 1, C-bit parity is enabled, and the associated functions are
inserted in the C-bit positions of the incoming DS3 stream. When CBIT is a logic 0, the M23 application is selected, and the C-bits
are passed transparently through the DS3 TRAN.
REGISTER DESCRIPTION
26
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 TRANSMIT DIAGNOSTIC
Read/Write Addresses: 0DH
Reset Value:
00H
7
6
5
0
4
3
2
1
0
DLOS
DLCV
DFERR
DMERR
DCPERR
DPERR
DFEBE
Bit
Name
Description
7
DLOS
(DS3 Loss of Signal)
The DLOS controls the insertion of loss of signal in the outgoing DS3 stream. When DLOS is set to a logic 1, the data on outputs
TPOS, TNEG, and TDAT are forced to continuous zeros.
6
DLCV
(DS3 Line Code Viola-
tion)
The DLCV controls the insertion of a single line code violation in the outgoing DS3 stream. When DLCV is set to a logic 1, a line
code violation is inserted by generating an incorrect polarity of violation in the next B3ZS signature. The data being transmitted
must therefore contain periods of three consecutive zeros in order for the line code violation to be inserted. For example line code
violations may not be inserted when transmitting AIS, but will be inserted when transmitting the idle signal. This bit is automatically
cleared upon insertion of the line code violation.
5
4
Unused
Must be zero for normal operation.
DFERR
(DS3 F-Bit Errors)
The DFERR controls the insertion of framing errors (F-bit errors) in the outgoing DS3 stream. When DFERR is set to a logic 1, and
the F-bits are inverted before insertion in the DS3 stream.
3
2
1
0
DMERR
(DS3 M-Bit Errors)
The DMERR controls the insertion of framing errors (M-bit errors) in the outgoing DS3 stream. When DMERR is set to a logic 1, and
the M-bits are inverted before insertion in the DS3 stream.
DCPERR
The DCPERR controls the insertion of C-bit parity errors in the outgoing DS3 stream. When DCPERR is set to a logic 1, and the C-
(DS3 C-Bit Parity Errors) bit parity application is enabled, the three C-bits in M-subframe 3 are inverted before insertion in the DS3 stream.
DPERR
(DS3 P-Bit Errors)
The DPERR controls the insertion of parity errors (P-bit errors) in the outgoing DS3 stream. When DPERR is set to a logic 1, and
the P-bits are inverted before insertion in the DS3 stream.
DFEBE
(DS3 Far End Block
Errors)
The DFEBE controls the insertion of far end block errors in the outgoing DS3 stream. When DFEBE is set to a logic 1, and the C-bit
parity application is enabled, the three C-bits in M-subframe 4 are set to a logic 0.
REGISTER DESCRIPTION
27
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 PMON INTERRUPT ENABLE/STATUS
Read/Write Addresses: 11H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
1
0
0
INTE
INTR
OVR
Bit
Name
Description
7-3 Unused
Must be zero for normal operation.
2
INTE
(DS3 Performance
A logic 1 in the INTE bit position enables the DS3 PMON to generate a microprocessor interrupt and assert the INTB output when
the counter values are transferred to the holding registers. A logic 0 in the INTE bit position disables the DS3 PMON from generat-
Monitor Interrupt Enable) ing an interrupt. When the TSB is reset, the INTE bit is set to logic 0, disabling the interrupt. The interrupt is cleared when this reg-
ister is read.
1
0
INTR
(DS3 Interrupt)
The interrupt (INTR) bit indicates the current status of the internal interrupt signal. A logic 1 in this bit position indicates that a trans-
fer of counter values to the holding registers has occurred; a logic 0 indicates that no transfer has occurred.
The INTR bit is set to logic 0 when this register is read. The value of the INTR bit is not affected by the value of the INTE bit.
OVR
(DS3 Overrun)
The overrun (OVR) bit indicates the overrun status of the holding registers. A logic 1 in this bit position indicates that a previous
interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have
been overwritten. A logic 0 indicates that no overrun has occurred. This bit is reset to logic 0 when this register is read.
DS3 LCV COUNT LSB
Read/Write Addresses: 14H
Reset Value:
00H
7
6
5
4
3
2
1
0
LCV7
LCV6
LCV5
LCV4
LCV3
LCV2
LCV1
LCV0
Bit
Name
Description
7-0 LCV 7-0
These bits indicate the number of DS3 Line Code Violation (LCV) events that occurred during the previous accumulation interval. A
transfer operation of all counter registers within the selected PMON can be triggered by writing to either LCV Count Register.
(DS3 Line Code
Violation)
REGISTER DESCRIPTION
28
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 LCV COUNT MSB
Read/Write Addresses: 15H
Reset Value:
00H
7
6
5
4
3
2
1
0
LCV15
LCV14
LCV13
LCV12
LCV11
LCV10
LCV9
LCV8
Bit
Name
Description
7-0 LCV 15-8
(DS3 Line Code
Violation)
These bits indicate the number of DS3 Line Code Violation (LCV) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either LCV Count Register.
DS3 FERR COUNT LSB
Read/Write Addresses: 16H
Reset Value:
00H
7
6
5
4
3
2
1
0
FERR7
FERR6
FERR5
FERR4
FERR3
FERR2
FERR1
FERR0
Bit
Name
Description
7-0 FERR 7-0
These bits indicate the number of DS3 framing error (FERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FERR Count Register.
(DS3 Far End Receive
Error)
DS3 FERR COUNT MSB
Read/Write Addresses: 17H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
0
1
0
0
FERR9
FERR8
Bit
Name
Description
7-2 Unused
Must be zero for normal operation.
1-0 FERR 9-8
These bits indicate the number of DS3 framing error (FERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FERR Count Register.
(DS3 Far End
Receive Error)
REGISTER DESCRIPTION
29
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 EXZS COUNT LSB
Read/Write Addresses: 18H
Reset Value:
00H
7
6
5
4
3
2
1
0
EXZS7
EXZS6
EXZS5
EXZS4
EXZS3
EXZS2
EXZS1
EXZS0
Bit
Name
Description
These registers indicate the number of summed Excessive Zeros (EXZS) that occurred during the previous accumulation interval.
7-0 EXZS 7-0
(DS3 Excessive Zero One or more excessive zeros occurrences within an 85 bit block is counted as one summed excessive zero.
Suppression) A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FERR Count Register.
DS3 EXZS COUNT MSB
Read/Write Addresses: 19H
Reset Value:
00H
7
6
5
4
3
2
1
0
EXZS15
EXZS14
EXZS13
EXZS12
EXZS11
EXZS10
EXZS9
EXZS8
Bit
Name
Description
These registers indicate the number of summed Excessive Zeros (EXZS) that occurred during the previous accumulation interval.
7-0 EXZS 7-0
(DS3 Excessive Zero One or more excessive zeros occurrences within an 85 bit block is counted as one summed excessive zero.
Suppression) A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FERR Count Register.
DS3 PERR COUNT LSB
Read/Write Addresses: 1AH
Reset Value:
00H
7
6
5
4
3
2
1
0
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
Bit
Name
Description
7-0 PERR 7-0
(DS3 Parity Error)
These bits indicate the number of P-bit parity error (PERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either EXZS Count Register or
writing to the Global PMON Update Register 0x01.
REGISTER DESCRIPTION
30
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 PERR COUNT MSB
Read/Write Addresses: 1BH
Reset Value:
00H
7
6
0
5
4
3
2
1
0
0
PERR13
PERR12
PERR11
PERR10
PERR9
PERR8
Bit
Name
Description
7-0 PERR 13-8
(DS3 Parity Error)
These bits indicate the number of P-bit parity error (PERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either EXZS Count Register.
DS3 CPERR COUNT LSB
Read/Write Addresses: 1CH
Reset Value:
00H
7
6
5
4
3
2
1
0
CPERR7
CPERR6
CPERR5
CPERR4
CPERR3
CPERR2
CPERR1
CPERR0
Bit
Name
Description
7-0 CPERR 7-0
(DS3 C-Bit Parity
Error)
These bits indicate the number of C-bit parity error (CPERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either CPERR Count Register.
DS3 CPERR COUNT MSB
Read/Write Addresses: 1DH
Reset Value:
00H
7
6
0
5
4
3
2
1
0
0
CPERR13
CPERR12
CPERR11
CPERR10
CPERR9
CPERR8
Bit
Name
Description
7-6 Unused
Must be zero for normal operation.
5-0 CPERR 13-8
These bits indicate the number of C-bit parity error (CPERR) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either CPERR Count Register.
(DS3 C-Bit Parity
Error)
REGISTER DESCRIPTION
31
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FEBE COUNT LSB
Read/Write Addresses: 1EH
Reset Value:
00H
7
6
5
4
3
2
1
0
FEBE7
FEBE6
FEBE5
FEBE4
FEBE3
FEBE2
FEBE1
FEBE0
Bit
Name
Description
7-0 FEBE 7-0
(DS3 Far End Bit
Error)
These bits indicate the number of far end block error (FEBE) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FEBE Count Register.
DS3 FEBE COUNT MSB
Read/Write Addresses: 1FH
Reset Value:
00H
7
6
0
5
4
3
2
1
0
0
FEBE13
FEBE12
FEBE11
FEBE10
FEBE9
FEBE8
Bit
Name
Description
7-0 FEBE 13-8
(DS3 Far End Bit
Error)
These bits indicate the number of far end block error (FEBE) events that occurred during the previous accumulation interval.
A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FEBE Count Register.
REGISTER DESCRIPTION
32
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
XFDL TSB CONFIGURATION
Read/Write Addresses: 20H
Reset Value:
00H
7
6
0
5
0
4
3
2
1
0
0
EOM
INTE
ABT
CRC
EN
Bit
Name
Description
7-5 Unused
Must be zero for normal operation.
4
EOM
The EOM bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the
(XFDL End of Message) CRC bit is set then the 16-bit FCS word is appended to the last data byte transmitted and a continuous stream of flags is gener-
ated. The EOM bit is automatically cleared before transmission of the next data packet begins. The EOM register bit value can be
set to logic 1 by pulsing the TDLEMOI input pin.
3
2
INTE
The INTE bit enables the generation of an interrupt via the TDLINT output. Setting the INTE bit to logic 1 enables the generation of
(XFDL Interrupt Enable) an interrupt by asserting the TDLINT output; setting INTE to logic 0 disables the generation of an interrupt.
ABT
The Abort (ABT) controls the sending of the 7 consecutive ones HDLC abort code. Setting the ABT bit to a logic 1 causes the
11111110 code to be transmitted after the last byte from the Transmit Data Register. Aborts are continuously sent until this bit is
reset to logic 0.
(XFDL Abort Code)
1
0
CRC
The CRC enable bit controls the generation of the CCITT-CRC frame check sequence (FCS). Setting the CRC bit to logic 1
enables the CCITT-CRC generator and the appends the 16 bit FCS to the end of each message. When the CRC bit is set to logic
0, the FCS is not appended to the end of the message. The CRC type used is the CCITT-CRC with generator polynomial =
x16+x12+x5+1. The HIGH order bit of the FCS word is transmitted first.
(XFDL Cyclical
Redundancy Check)
EN
The enable bit (EN) controls the overall operation of the XFDL TSB. When the EN bit is set to a logic 1, the XDFL TSB is enabled
and flag sequences are sent until data is written into the Transmit Data Register. When the EN bit is set to logic 0, the XFDL TBS
is disabled.
(XFDL Enable)
XFDL TSB INTERRUPT STATUS
Read/Write Addresses: 21H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
0
1
0
0
INT
UDR
Bit
Name
Description
7-2 Unused
Must be zero for normal operation.
1
INT
The INT bit indicates when the XFDL TSB is ready to accept a new data byte for transmission. The INT bit is set to a logic 1 when
the previous byte in the Transmit Data register has been loaded into the parallel to serial converter and a new byte can be written
into the Transmit Data register. The INT bit is set to a logic 0 while new data is in the Transmit Data register. The INT bit is not dis-
abled by the INTE bit in the configuration register.
(XFDL Interrupt)
0
UDR
(XFDL Underrun)
The UDR bit indicates when the XFDL TSB has underrun the data in the Transmit Data register. The UDR bit is set to a logic 1 if
the parallel to serial conversion of the last byte in the Transmit Data register has completed before the new byte was written into
the Transmit Data register. Once an underrun has occurred, the XFDL transmits an ABORT, followed by a flag, and waits to trans-
mit the next valid data byte. If the UDR bit is still set after the transmission of the flag the XFDL will continuously transmit the all-
ones idle pattern. The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in the register.
REGISTER DESCRIPTION
33
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
XFDL TSB TRANSMIT DATA
Read/Write Addresses: 22H
Reset Value:
00H
7
6
5
4
3
2
1
0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Bit
Name
Description
Data written to this register is serialized and transmitted on the path maintenance data lint least significant bit first. The XFDL
7-0 TD 7-0
(XFDL Transmit Data Byte) TSB signals when the next data byte is required by asserting the TDLINT output (if enabled) and by setting the INT bit in the
Status register high. When INT and/or TDLINT is set, the Transmit Data register must be written with the next message byte
within 4 data bit periods to prevent the occurrence of an underrun. At a nominal 28.2 kbit/sec link data rate the required write
interval is 110µsec.
RFDL TSB CONFIGURATION
Read/Write Addresses:24H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
0
1
0
0
TR
EN
Bit
Name
Description
7-2 Unused
Must be zero for normal operation.
1
TR
Setting the terminate reception bit (TR) forces the RFDL TSB to immediately terminate the reception of the current LAPD
frame, empty the FIFO, clear the interrupts, and begin searching for a new flag sequence. The RFDL handles the TR input in
the same manner as if the EN bit had been cleared and then set. The TR bit in the Configuration register will reset itself after a
rising and falling edge have occurred on the CLK input to the RFDL TSB once the write to this register has completed and WEB
goes inactive. If the Configuration register is read after this time, the TR value returned will be zero. The RFDL TSB handles the
TR input in the same manner as clearing and setting the EN bit, therefore, the RFDL state machine will begin searching for
flags and an interrupt will be generated when the first flag is detected.
(RDFL Terminate
Reception)
0
EN
The enable bit (EN) controls the overall operation of the RFDL TSB. When set, the RDFL TSB is enabled; When reset, the
RDFL TSB is disabled. When the TSB is disabled, the FIFO and interrupts are all cleared, however, the programming of the
Interrupt Control/Status Register is not affected. When the TSB is enabled, it will immediately begin looking for flags.
(RFDL Enable)
REGISTER DESCRIPTION
34
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RFDL TSB INTERRUPT CONTROL/STATUS
Read/Write Addresses: 25H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
1
0
0
INTC1
INTC0
INT
Bit
Name
Description
7-3 Unused
Must be zero for normal operation.
The INTC1 and INTC0 bits control when an interrupt is asserted based on the number of received data bytes in the FIFO as follows:
2, 1 INTC1, INTC0
(RDFL Interrupt
Control Bits)
INTC1
INTC0
Description
0
0
1
1
0
1
0
1
Disable interrupts (All sources)
Enable interrupt when FIFO receives data
Enable interrupt when FIFO has 2 bytes of data
Enable interrupt when FIFO has 3 bytes of data
0
INT
The INT bit reflects the Status of the external RDLINT interrupt unless the INTC1 and INTC0 bits are set to disable interrupts, In that
case, the RDLINT output is forced to 0 and the INT bit of the Interrupt Control/Status register will reflect the state of the internal inter-
rupt latch.
(RDFL Interrupt
Status)
REGISTER DESCRIPTION
35
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RFDL TSB STATUS
Read/Write Addresses:26H
Reset Value:
00H
7
6
5
4
3
2
1
0
FE
OVR
FLG
EOM
CRC
NVB2
NVB1
NVB0
Bit
Name
Description
7
FE
The FIFO Empty bit (FE) is HIGH when the last FIFO entry is read and goes LOW when the FIFO is loaded with new data.
(RDFL FIFO Empty)
6
OVR
(RDFL Overrun)
The Receiver Overrun bit (OVR) is set when data is written over unread data in the FIFO. This bit is not reset until after the Status
register is read. While OVR is HIGH, the RFDL and FIFO are held in the reset state, causing the FLG and EOM bits in the status reg-
ister to be reset also.
5
4
FLG
(RDFL Flag)
The flag bit (FLG) is set if the RFDL TSB has detected the presence of the LAPD flag sequence (01111110) in the data. FLG is reset
only when the LAPD abort sequence (01111111) is detected in the data or when the RFDL TSB is disabled. This bit is passed
through the FIFO with the Data so that the status will correspond to the Data just read from the FIFO. The reception of bit oriented
codes over the data link will also force an abort due to its eight ones pattern.
EOM
The End of Message bit (EOM) follows the RDLEOM output. It is set when:
(RFDL End of Mes-
sage)
1. The last byte in the LAPD frame (EOM) is being read from the Receive Data Register.
2. An abort sequence is detected while not in the receiving all-ones state and the byte, written to the FIFO due to
the detection of the abort sequence, is being read from the FIFO,
3. Immediately on detection of FIFO overrun.
The EOM bit is passed through the FIFO with the Data so that the Status will correspond to the Data just read from the FIFO.
3
CRC
The CRC bit is set if a CRC error was detected in the last received LAPD frame. The CRC bit is only valid when EOM is logic 1 and
FLG is a logic 1 and OVR is a logic 0.
(RFDL Cyclical
Redundancy Check)
2-0 NVB 2-0
(RFDL Number of
Valid Bits)
The NVB 2-0 bit positions indicate the number of valid bits in the Receive Data Register byte. It is possible that not all of the bits in the
Receive Data Register are valid when the last data byte is read since the data frame can be any number of bits in length and not nec-
essarily an integral number of bytes. The receive Data Register is filled from the MSB to the LSB bit position, with one to eight data
bits being valid. The number of valid bits is equal to 1 plus the value of NVB 2-0 value of 000 binary indicates that only the MSB in the
register is valid. NVB 2-0 is only valid when the EOM bit is a logic 1 and the FLG bit is a logic 1 and the OVR bit is a logic 0.
RFDL TSB RECIVE DATA
Read/Write Addresses: 27H
Reset Value:
00H
7
6
5
4
3
2
1
0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Bit
Name
Description
RD0 corresponds to the first bit of the serial byte received by the RFDL.
7-0 RD 7-0
(RFDL Receive Byte)
REGISTER DESCRIPTION
36
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX23 CONFIGURATION
Read/Write Addresses: 28H
Reset Value:
00H
7
6
0
5
0
4
0
3
2
1
0
0
LBCODE1
LBCODE0
CBE
INTE
Bit
Name
Description
7-4 Unused
Must be zero for normal operation.
3-2 LBCODE 1-0
The LBCODE 1-0 bits select the valid state for a loopback request coded in the C-bits of the DS3 signals. Transmit and receive are not
independent; the same code is expected in the receive DS3 as is inserted in the transmitted DS3. The following table gives the corre-
spondence between LBCODE 1-0 bits and the valid codes:
(Loopback Code)
LBCODE1:0] Loopback Code
00
01
10
11
C1 = C2 and C1 = C3
C1 = C3 and C1 = C2
C2 = C3 and C1 = C2
C1 = C2 and C1 = C3
If LDCODE 1-0 is ‘b00 or ‘b11, the loopback code is as per ANSI T1.107a Section 8.2.1 and TR-TDY-000009 Section 3.7. Because
TR-TSY 000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command
possibilities are also supported
The LBCODE 1-0 bits become logical 0 upon either a hardware or software reset.
1
0
CBE
When set HIGH, the CBE bit enables C-bit parity operation. When CBE is LOW, M23 operation is enabled. While in C-bit parity mode,
(C-Bit Parity Enable) loopback request insertion are disabled. The generated DS2 clock, GD2CLK, is nominally 6.3062723 MHz while in C-bit parity mode,
received C bits are ignored, and transmitted C bits are set to 1. While in M23 mode, the generated DS2 clock, GD2CLK, is nominally
6.311993 MHz and C bit decoding and encoding is fully operational.
INTE
When set HIGH, the INTE bit enables the MX23 to activate the interrupt output, INTB, whenever any of the LBRI 7-1 bits are set HIGH
(M23 Interrupt Enable) in the MX23 Loopback Request Interrupt register. MX23 interrupts are masked when INTE is cleared LOW.
REGISTER DESCRIPTION
37
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DEMUX AIS INSERT REGISTER
Read/Write Addresses: 2AH
Reset Value:
00H
7
0
6
5
4
3
2
1
0
DAIS7
DAIS6
DAIS5
DAIS4
DAIS3
DAIS2
DAIS1
Bit
Name
Unused
6-0 DAIS 7-1
Description
7
Must be zero for normal operation.
Setting any of the DAIS7-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding DS2 stream demul-
tiplexed from the DS3 signal input on RDAT. Demux AIS Insertion takes place after the point where per DS2 loopback may be
invoked using the Loopback Activate register thus allowing demux AIS to be inserted into the through path while a DS2 loopback is
activated, if desired.
(Demux Alarm
Indication Signal)
MX23 MUX AIS INSERT REGISTER
Read/Write Addresses: 2AH
Reset Value:
00H
7
0
6
5
4
3
2
1
0
MAIS7
MAIS6
MAIS5
MAIS4
MAIS3
MAIS2
MAIS1
Bit
Name
Unused
6-0 MAIS 7-1
Description
7
Must be zero for normal operation.
Setting any of the MAIS 7-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding DS2 stream
multiplexed into the DS3 signal output on TDAT. Mux AIS Insertion takes place before the point where per DS2 loopback may be
invoked using the Loopback Activate register and thus mux AIS cannot be inserted while a DS2 loopback is activated.
(Multiplexed Alarm
Indication Signal)
REGISTER DESCRIPTION
38
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX23 LOOPBACK ACTIVATE REGISTER
Read/Write Addresses: 2BH
Reset Value:
00H
7
0
6
5
4
3
2
1
0
LBA7
LBA6
LBA5
LBA4
LBA3
LBA2
LBA1
Bit
Name
Unused
6-0 LBA 7-1
Description
7
Must be zero for normal operation.
Setting any of the LBA 7-1 bits activates loopback of the corresponding DS2 stream from the input DS3 signal to the output DS3
(DS2 Loopback)
signal.
The demultiplexed DS2 signals continue to present valid payloads while loopbacks are activated. The MX23 Demux AIS Insert
Register allows insertion of DS2 AIS if required.
MX23 LOOPBACK REQUEST INSERT REGISTER
Read/Write Addresses: 2CH
Reset Value:
00H
7
0
6
5
4
3
2
1
0
ILBR7
ILBR6
ILBR5
ILBR4
ILBR3
ILBR2
ILBR1
Bit
Name
Unused
6-0 ILBR 7-1
Description
7
Must be zero for normal operation.
Setting any of the ILBR 7-1 bits enables the insertion of a loopback request in corresponding DS2 stream in the output DS3 signal.
The format of the loopback request is determined by the LBCODE 1-0 bits in the MX23 Configuration Register.
(MX23 Insertion
Loopback Request)
REGISTER DESCRIPTION
39
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX23 LOOPBACK REQUEST DETECT REGISTER
Read/Write Addresses: 2DH
Reset Value:
00H
7
6
5
4
3
2
1
0
0
LBRD7
LBRD6
LBRD5
LBRD4
LBRD3
LBRD2
LBRD1
Bit
Name
Unused
6-0 LBRD 7-1
Description
7
Must be zero for normal operation.
The LBRD 7-1 bits are set HIGH while a loopback request is detected for the corresponding DS2 stream in the input DS3 signal. The
LBRD 7-1 bits are set LOW otherwise.
The format of the loopback request expected is determined by the LBCODE 1-0 bits in the MX23 Configuration Register. As per
TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection.
Removal of the loopback request is declared when it has be absent for five successive M-frames.
(MX23 Loopback
Request Detector)
MX23 LOOPBACK REQUEST INTERRUPT REGISTER
Read/Write Addresses: 2EH
Reset Value:
00H
7
6
5
4
3
2
1
0
0
LBRI7
LBRI6
LBRI5
LBRI4
LBRI3
LBRI2
LBRI1
Bit
Name
Unused
6-0 LBRI 7-1
Description
7
Must be zero for normal operation.
The LBRI 7-1 bits are set HIGH while a loopback request is asserted or deasserted for the corresponding DS2 stream in the input
DS3 signal. The LBRI 7-1 bits are set HIGH whenever the corresponding LBRI 7-1 bits change state. If interrupts are enabled using
the INTE bit in the Configuration register then the interrupt output, INTB is activated. The LBRI 7-1 bits are to logic 0 immediately
following a read of the register, acknowledging the interrupt and deactivating the INTB output.
(MX23 Loopback
Request Interrupt)
REGISTER DESCRIPTION
40
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
FEAC XBOC TSB CODE
Read/Write Addresses: 31H
Reset Value:
3FH
7
6
0
5
4
3
2
1
0
0
BC5
BC4
BC3
BC2
BC1
BC0
Bit
Name
Description
7-6 Unused
5-0 BC 5-0
Must be zero for normal operation.
This register enables the XBOC TSB to generate a bit oriented code and selects the 6-bit code to be transmitted.
When this register is written with any 6-bit code other than 111111, that code will be transmitted repeatedly in the far-end alarm and
control (FEAC) channel with the format 111111110[BC0][BC1][BC2][BC3][BC4][BC5]0. When the register is written with 111111, the
XBOC TSB is disabled.
RBOC CONFIGURATION/INTERRUPT ENABLE
Read/Write Addresses: 32H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
1
0
0
IDLE
AVC
BOCE
Bit
Name
Description
7-3 Unused
Must be zero for normal operation.
2
IDLE
(Idle)
The IDLE bit position enables or disables the generation of an interrupt when there is a transition from a validated BOC to idle code.
A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation.
1
AVC
The AVC bit position selects the validation criterion used in determining a valid BOC. A logic 0 selects the 8 out of 10 matching BOC
(Alternative Validation criterion; a logic 1 in the AVC bit position selects the “alternative” validation criterion of 4 out of 5 matching BOCs.
Criterion)
0
BOCE
(Bit Oriented Code
Enable)
The BOCE bit position enables or disables the generation of an interrupt when a valid BOC is detected. A logic 1 in this bit position
enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. When the D3MX is reset, BOCE is reset
to logic 0; therefore, interrupt generation is disabled.
REGISTER DESCRIPTION
41
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RBOC INTERRUPT STATUS
Read/Write Addresses: 33H
Reset Value:
00H
7
6
5
4
3
2
1
0
IDLEI
BOCI
BOC5
BOC4
BOC3
BOC2
BOC1
BOC0
Bit
Name
Description
7
IDLEI
(Idle Interrupt)
The IDLEI bit indicates whether an interrupt was generated by the detection of the transition from a valid BOC to idle code. A logic 1 in
the IDLEI bit position indicates that a transition from a valid BOC to idle code has generated an interrupt; a logic 0 in the IDLEI bit
position indicates that no transition from a valid BOC to idle code has been detected. IDLEI is cleared to logic 0 when the register is
read.
6
BOCI
(Bit Oriented Code
Interrupt)
Indicates a logic 1 in the BOCI bit position indicates that a validated BOC code has generated an interrupt; a logic 0 in the BOCI bit
position indicates that no BOC has been detected. Since the bit-oriented code “111111” is not recognized by the RBOC, the BOC 5-0
bits are set to all ones (“111111”) if no valid code has been detected. The BOCI bit position is cleared to logic 0 and the interrupt is
deasserted when this register is read.
5-0 BOC 5-0
(Bit Oriented Code)
The bit positions BOC 5-0 contain the received bit-oriented codes. A logic 1 in the BOCI bit position indicates that a validated BOC
code has generated an interrupt; a logic 0 in the BOCI bit position indicates that no BOC has been detected. Since the bit-oriented
code “111111” is not recognized by the RBOC, the BOC 5-0 bits are set to all ones (“111111”) if no valid code has been detected. The
BOCI bit position is cleared to logic 0 and the interrupt is deasserted when this register is read.
REGISTER DESCRIPTION
42
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FRMR CONFIGURATION
Read/Write Addresses: 34H
Reset Value:
80H
7
6
5
4
3
2
1
0
AISPAT
FDET
MBDIS
M3O8
UNI
REFR
AISC
CBE
Bit
Name
AISPAT
Description
The AISPAT bit controls the pattern used to detect the alarm indication signal (AIS). When a logic 1 is written to AISPAT, the AIS
7
(DS3 Alarm Indication detection algorithm checks that a framed DS3 signal containing the repeating pattern 1010...is present. The C-bits are checked for
Pattern)
the value specified by the AISC bit setting. When a logic 0 is written to AISPAT, the AIS detection algorithm is determined solely by
the settings of AISC and AISONES register bits (see bit mapping table in the Additional Configuration Register description).
6
5
FDET
The FDET bit selects the fast detection timing for AIS, IDLE and RED. When FDET is set to logic 1, the AIS, IDLE, and RED detec-
(DS3 Fast Detection) tion time is 2.23 ms; when FDET is set to logic 0, the detection time is 13.5 ms.
MBDIS The MBDIS bit disables the use of M-bit errors as a criteria for losing frame alignment. When MBDIS is set to logic 1, M-bit errors are
(DS3 M-Bit Error Dis- disabled from causing an OOF; the loss of frame criteria is based solely on the number of F-bit errors selected by the M3O8 bit.
able)
When MBDIS is logic 0, an OOF can occur when one or more M-bit errors occur in 3 out of 4 consecutive M-frames, or when the F-
bit error ratio selected by the M3O8 bit is exceeded.
4
3
2
1
M3O8
The M3O8 bit configures the out of frame decision criteria. If M3O8 is a logic 1, out of frame is declared if at least 3 of 8 framing bits
(DS3 M-Bit 3 out of 8 are in error. If M3O8 is a logic 0, the standard 3 of 16 bits in error criteria is used.
Framing Error)
UNI
The UNI bit is used to configure the FRMR to accept either unipolar or bipolar data streams. When a logic 1 is written to UNI, the
(DS3 Unipolar Select) FRMR accepts unipolar data and line code violation indication on its inputs. When a logic 0 is written to UNI, the FRMR accepts bipo-
lar data on its inputs and performs B3ZS decoding and line code violation reporting.
REFR
(DS3 Re-Framing)
The REFR bit is used to trigger reframing. If a logic 1 is written to REFR when it was previously logic 0, the FRMR is forced out-of-
frame, and a new search for frame alignment is initiated. Note that only a LOW to HIGH transition of the REFR bit triggers reframing;
multiple write operations are required to ensure such a transitions
AISC
The AISC bit controls the algorithm used to detect the alarm indication signal (AIS). When a logic 1 is written to AISC, the algorithm
checks that a framed DS3 signal with all C-bits set to logic 0 is observed for a period of time before declaring AIS. The payload con-
tents are checked to the pattern selected by the AISPAT bit. When a logic 0 is written to AISC, the AIS detection algorithm is deter-
mined solely by the settings of AISPAT and AISONES register bits (see bit mapping table in the Additional Configuration Register
description).
(DS3 Alarm
IndicationSignal
Configuration)
0
CBE
(DS3 C-Bit Parity
Enable)
The CBE bit selects whether the C-bit parity application is enabled. When a logic 1 is written to CBE, C-bit parity mode is enabled.
When a logic 0 is written, C-bit parity mode is disabled.
REGISTER DESCRIPTION
43
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FRMR INTERRUPT ENABLE (ACE=0)
Read/Write Addresses: 35H
Reset Value:
00H
7
6
5
4
3
2
1
0
COFAE
REDE
CBITE
FERFE
IDLE
AISE
OOFE
LOSE
Bit
Name
COFAE
(DS3 Change of
Frame Alignment
Enable)
Description
7
The COFAE bit enables an interrupt to be generated when a change of frame alignment (i.e. a COFA event) occurs. When COFAE is
set to logic 1, the interrupt output, INTB, is set LOW when the COFA event occurs.
6
REDE
(DS3 RED Alarm
Enable)
The REDE bit enables an interrupt to be generated when a change of state of the DS3 RED indication occurs. The DS3 RED
indication is visible in the REDV bit location in the DS3 FRMR Status register and on the ROOF/RRED pin when the REDO bit in the
Master Alarm Enable register (register 06Hex) is set to logic 1. When REDE is set to logic 1, the interrupt output, INTB, is set LOW
when the state of the RED indication changes.
5
4
CBITE
(DS3 C-Bit
Identification Enable) changes.
The CBITE bit enables an interrupt to be generated when a change of state in the C-bit Identification indication internal to the DS3
FRMR occurs. When CBITE is set to logic 1, the interrupt output, INTB, is set LOW when the state of the C-bit Identification indication
FERFE
The FERFE bit enables an interrupt to be generated when a change of state of the FERF indication occurs. The FERF indication is
(DS3 Far End
Receive Failure
Enable)
visible in the FERFV bit location in the DS3 FRMR Status register and on the RFERF pin. When FERFE is set to logic 1, the interrupt
output, INTB, is set LOW when the state of the FERF output changes.
3
2
IDLE
(DS3 Idle Enable)
The IDLE bit enables an interrupt to be generated when a change of state of the DS3 AIS signal detector occurs. When IDLE is set to
logic 1, the interrupt output, INTB, is set LOW when the state of the IDLE detector changes.
AISE
The AISE bit enables an interrupt to be generated when a change of state of the DS3 AIS signal detector occurs. The state of the AIS
(DS3 Alarm Indication detector is visible in the AISV bit location in the DS3 FRMR Status register and on the RAIS pin. When AISE is set to logic 1, the
Signal Enable)
interrupt output, INTB, is set LOW when the state of the AIS detector changes.
1
OOFE
(DS3 Out of Frame
Enable)
The OOFE bit enables an interrupt to be generated when a change of state of the DS3 FRMR frame alignment acquisition circuitry
occurs. The state of the frame alignment acquisition circuitry occurs. The state of the frame alignment acquisition circuitry is visible in
the OOFV bit location in the DS3 FRMR Status register and on the ROOF/RRED pin when the REDO bit in the Master Alarm Enable
register is logic 0. When the circuitry has lost frame aliment and is searching for the new alignment, and out frame is indicated and
the OOFV bit and ROOF pin are set to logic 1. When the circuitry has found frame alignment, the OOFV bit and ROOF pin are set to
logic 0. When OOFE is set to logic 1, the interrupt output, INTB, is set LOW when the state of the OOF indication changes.
0
LOSE
(DS3 Loss of Signal
Enable)
The LOSE bit enables an interrupt to be generated when a change of state of the loss of signal detector occurs. The state of the
detector is visible in the LOSV bit position in the DS3 FRMR Status register and on the RLOS pin. When LOSE is set to logic 1, the
interrupt output, INTB, is set LOW when the state of the LOS indication changes.
REGISTER DESCRIPTION
44
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FRMR ADDITIONAL CONFIGURATION REGISTER (ACE=1)
Read/Write Addresses: 35H
Reset Value:
00H
7
6
0
5
4
3
2
1
0
0
AISONES
BPVO
EXZSO
EXTYPE
SALGO
ALGOTYPE
Bit
Name
Description
7-6 Unused
Must be zero for normal operation.
5
AISONES
(DS3 Alarm
Indication Signal)
The AISONES bit controls the pattern used to detect the alarm indication signal (AIS) when both AISPAT and AISC bits in DS3
FRMR Configuration register (34H) are logic 0; if either AISPAT or AISC are logic 1, the AISONES bit is ignored. When a logic 0 is
written to AISONES, the algorithm checks that a framed all-ones payload pattern (1111...) signal is observed for a period of time
before declaring AIS. Only the payload bits are observed to follow an all-ones pattern, the overhead bits (X, P, M, F, C) are ignored.
When a logic 1 is written to AISONES, the algorithm checks that an unframed all-ones pattern (1111...) signal is observed for a period
of time before declaring AIS. In this case all the bits, including the overhead, are observed to follow an all-ones pattern. The valid
combinations of AISPAT, AISC, and AISONES bits are summarized below:
AISPAT AISC AISONES AIS Detected
1
0
1
0
0
0
1
1
0
0
X
X
X
0
Framed DS3 stream containing repeating 1010... pattern; overhead bits ignored.
Framed DS3 stream containing C-bits all logic 0; payload bits ignored.
Framed DS3 stream containing repeating 1010... pattern and C-bits all logic 0.
Framed DS3 stream containing all-ones payload pattern; overhead bits ignored.
Unframed all-ones DS3 stream.
1
4
3
BPVO
(DS3 Bipolar
Violations)
The BPVO bit enables only bipolar violations to indicate line code violates and be accumulated in the PMON LCV Count Registers.
When BPVO is set to logic 1, only BPVs not part of a valid B3ZS signature generate an LCV indication and increment the PMON LCV
counter. When BPVO is set to logic 0, both BPVs not part of a valid B3ZS signature, and either 3 consecutive zeros or excessive
zeros generate an LCV indication and increment the PMON LCV counter.
EXZSO
The EXZSO bit enables only summed zero occurrences to be accumulated in the PMON EXZS Count Registers. When EXZSO is set
(DS3 Excessive Zero to logic 1, any excessive zero occurrences over an 85 bit period increments the PMON EXZS counter by one. When EXZSO is set to
Occurrences)
logic 0, summed LCVs are accumulated in the PMON EXZS Count Registers. A summed LCV is defined as the occurrence of either
BPVs not part of a valid B3ZS signature or 3 consecutive zeros (or excessive zeros if EXZDET=1) occurring over an 85 bit period;
each summed LCV occurrence increment the PMON EXZS counter by one.
2
EXTYPE
The EXTYPE bit determines the type of zero occurrences to be included in the LCV indication. When EXTYPE is set to logic 1, the
(DS3 Excessive Zero occurrence of an excessive zero generates a single pulse indication that is used to indicate an LCV.When EXTYPE is set to logic 0,
Type)
every occurrence of 3 consecutive zeros generates a pulse indication that is used to indicate an LCV. For example, if a sequence of
15 consecutive zeros were received, with EXTYPE=1 only a single LCV would be indicated for this string of excessive zeros; with
EXTYPE=0, five LCVs would be indicated for this string (i.e. one LCV for every 3 consecutive zeros).
1
0
SALGO
(DS3 Signature
Algorithm)
The SALGO bit determines the criteria used to establish a valid B3ZS signature used to map BPVs to line code violation indications.
Any BPV that is not part of a valid B3ZS signature is indicated as an LCV. When the SALGO bit is set to logic 1, a valid B3ZS signa-
ture is declared whenever a zero followed by a bipolar violation is observed. When SALGO is set to logic 0, a valid B3ZS signature is
declared whenever a zero followed by a bipolar violation of the opposite polarity to the last observed BPV is seen.
ALGOTYPE
The ALGOTYPE bit determines the criteria used to decode a valid B3ZS signature. When the ALGOTYPE is set to logic 1, a valid
(DS3 Algorithm Type) B3ZS signature is declared and 3 zeros substituted whenever a zero followed by a bipolar violation of the opposite polarity to the last
observed BPV is seen. When the ALGOTYPE bit is set to logic 0, a valid B3ZS signature is declared and the 3 zeros are substituted
whenever a zero followed by a bipolar violation is observed.
REGISTER DESCRIPTION
45
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FRMR INTERRUPT STATUS
Read/Write Addresses: 36H
Reset Value:
00H
7
6
5
4
3
2
1
0
COFAI
REDI
CBITI
FERFI
IDLI
AISI
OOFI
LOSI
Bit
Name
COFAI
(DS3 Change of
Frame Alignment
Indication)
Description
7
The COFAI bit indicates that a change of frame alignment (i.e. a COFA event) signal detector has occurred.
When the COFAI bit is a logic 1, the frame alignment acquisition circuitry has detected that the new alignment differs from the previ-
ous frame alignment. When the COFAI bit is logic 0, there was no difference from the current frame alignment and the previous frame
alignment.
6
REDI
The REDI bit indicates that a change of state of the DS3 RED indication has occurred. The DS3 RED indication is visible in the REDV
(DS3 RED Indication) bit location of the DS3 FRMR Status register and on the ROOF/RRED pin when the REDO bit in the Master Alarm Enable register
(register 06Hex) is set to logic 1.
When the REDI bit is a logic 1, a change in the RED state has occurred. When the REDI bit is logic 0, no change in the RED state
has occurred.
5
4
3
2
1
CBITI
(DS3 C-Bit
Identification)
The CBITI bit indicates that a change of state in the C-bit identification indication internal to the DS3 FRMR has occurred.
When the CBITI bit is a logic 1, a change in the internal CBIT state has occurred. When the CBITI bit is logic 0, no change in the
CBIT state has occurred.
FERFI
(DS3 FERF
Indication)
The FERFI bit indicates that a change of state of the FERF indication has occurred. The FERF indication is visible in the FERFV bit
location of the DS3 FRMR Status register and on the RFERF pin. When the FERFI bit is a logic 1, a change in the FERF state has
occurred. When the FERFI bit is logic 0, no change in the FERF state has occurred.
IDLI
The IDLI bit indicates that a change of state of the DS3 IDLE signal detector has occurred. When the IDLI bit is a logic 1, a change in
the IDLE detector state has occurred. When the IDLI bit is logic 0, no change in the IDLE signal detector state has occurred.
(DS3 IDLE Signal
Detector)
AISI
(DS3 AIS Signal
Detector)
The AISI bit indicates that a change of state of the DS3 AIS signal detector has occurred. The state of the AIS detector is visible in the
AISV bit location in the DS3 FRMR Status register and on the RAIS pin. When the AISI bit is a logic 1, a change in the AIS detector
state has occurred. When the AISI bit is logic 0, no change in the AIS detector state has occurred.
OOFI
(DS3 FRMR Status)
The OOFI bit indicates that a change of state of the DS3 FRMR Status frame alignment acquisition circuitry has occurred. The state
of the frame alignment acquisition circuitry is visible in the OOFV bit location in the DS3 FRMR Status register and on the ROOF/
RRED pin when the REDO bit in the Master Alarm Enable register is logic 0. When the circuitry has lost frame alignment and is
searching for the new alignment, an out frame is indicated and the OOFV bit and ROOF pin are set to logic 1. When the circuitry has
found frame alignment, the OOFI bit and ROOF pin are set to logic 0.
When the OOFV bit is a logic 1, a change in the OOF state has occurred. When the OOFV bit is logic 0, no change in the OOF state
has occurred.
0
LOSI
The LOSI bit indicates that a change of state of loss of signal detector has occurred. The state of the detector is visible in the LOSV
(DS3 Loss of Signal) bit position in the DS3 FRMR Status register and on the RLOS pin. When the LOSI bit is a logic 1, a change in the LOS state has
occurred. When the LOSI bit is logic 0, no change in the LOS state has occurred.
REGISTER DESCRIPTION
46
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 FRMR STATUS
Read/Write Addresses: 37H
Reset Value:
00H
7
6
5
4
3
2
1
0
ACE
REDV
CBITV
FERFV
IDLV
AISV
OOFV
LOSV
Bit
Name
Description
7
6
5
ACE
(DS3 Additional
Configuration Enable)
The ACE bit selects the Additional Configuration Register. This register is located at address 35H, and is only accessible when the
ACE bit is to logic 1. When ACE is set to logic 0, the Interrupt Enable register is accessible at address 35H.
REDV
(DS3 Red Alarm
Violation)
The REDV bit indicates the current state of the DS3 RED indication. When the REDV bit is a logic 1, the DS3 FRMR alignment acqui-
sition circuitry has been out of frame for 2.23ms (or for 13.5ms when FDET is logic 0). When the REDV bit is logic 0, the frame align-
ment circuitry has found frame (i.e. OODFV=0) for 2.23ms (or 13.4ms if FDET=0)
CBITV
The CBITV bit indicates the current state in the C-bit Identification indication. When the CBITV bit is a logic 1, the first C-bit or M sub-
(DS3 C-Bit Violation) frame 1 has been observed to be logic 1 for 63 consecutive occasions. When the CBITV bit is logic, the first C-bit of sub-frame 1 has
either not been logic 1 for 63 consecutive occasions or, if CBITV was previously logic 1, the first C-bit of sub-frame 1 has been
observed to be logic 0 for 2 or more times within 15 consecutive occasions.
4
3
2
1
0
FERFV
The FERFV bit indicates the current state of the FERF indication. When the FERFV bit is a logic 1, the FRMR detects that the second
(DS3 Far End Enable to last M-frame’s X2=X1=0. When the FERFV bit is logic 0, the second to last M-frame’s X2=X1=1.
Error Violation)
IDLV
(DS3 Idle Violation)
The IDLV bit indicates the current state of the DS3 IDLE signal detector. When the IDLV bit is a logic 1, the DS3 IDLE pattern has
been received for 2.23ms (or for 13.5ms when FDET is logic 0). When the IDLV bit is logic 0, the DS3 IDLE pattern has not been
received for either 2.23ms or 13.5ms.
AISV
The AISV bit indicates the current state of the DS3 AIS signal detector. When the AISV bit is a logic 1, the DS3 AIS pattern has been
(DS3 Alarm Indication received for 2.23ms (or for 13.5ms when FDET is logic 0). When the AISV bit is logic 0, the DS3 AIS pattern has not been received
Violation)
for either 2.23ms or 13.5ms.
OOFV
(DS3 Out of Frame
Violation)
The OOFV bit indicates the current state of the DS23 FRMR frame alignment acquisition circuitry. When the circuitry has lost frame
alignment and is searching for the new alignment, an out of frame is indicated and the OOFV bit is set to logic 1. When the circuitry
has found frame alignment, the OOFV bit is set to logic 0.
LOSV
(DS3 Los of Signal
Violation)
The LOSV bit indicates the current state of the loss of signal detector. When the LOSV bit is a logic 1, a sequence of 175 consecutive
zeros was detected on the dual-rail RPOS and RNEG DS3 inputs. When the LOSV bit is logic 0, a valid DS3 signal with a ones’ den-
sity greater than 33% for 175 ± 1 bit periods was detected on the dual-rail inputs.
REGISTER DESCRIPTION
47
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRMR CONFIGURATION
Read/Write Addresses: 40H, 50H, 60H, 70H, 80H, 90H, A0H
Reset Value:
00H
7
6
0
5
4
3
2
1
0
0
0
G747
WORD
M2O5
MDBIS
REF
Bit
Name
Description
7
G747
(DS2 G.747
Enable)
The G747 bit configures the FRMR for G.747 operation. If the G747 bit is a logic 1, the FRMR will process a G.747 signal. If the G747 bit is
a logic 0, the FRMR will process a DS2 signal as defined in ANSTI T1.107 Section 7.
6
5
Unused
Must be zero for normal operation.
WORD
The WORD bit determines the method of accumulating G.747 framing errors. If the WORD bit is a logic 0, each frame alignment signal (FAS)
bit error results in a single FERR count. If the WORD bit is a logic 1, one or more bit errors in a FAS word result in a single FERR count.
(DS2 Frame
Alignment
Signal Errors
Method)
4
M2O5
The M2O5 bit selects the error ratio for declaring out-of-frame (OOF) when in DS2 mode only. When a 1 is written to M2O5, the framer
(DS2 M-bit 2 out declares OOF when 2 F-bit errors out of 5 consecutive F-bits are observed. When a 0 is written, the framer declares OOF when 2 F-bit errors
of 5)
out of 4 consecutive F-bits are observed. (These two ratios are recommended in T-TSY000009 Section 4.1.2). When the FRMR is config-
ured for G.747 operation (the G747 bit is set to logic 1), the OOF status is declared when 4 consecutive framing word errors occur (as per
CCITT Rec. G747 Section 4), regardless of the M2O5 bit setting.
3
2
MBDIS
(DS2 M-bit
The MBDIS bit disables the declaration of out-of-frame upon excessive M-bit errors. If MBDIS is a logic 0, out-of-frame is declared when one
or more M-bit errors are detected in 3 out of 4 consecutive M-frames. If MBDIS is a logic 1, the state of the M-bits is ignored once in frame.
Error Disable) Regardless of the state of the MBDIS bit, the F-bits are always monitored for invalid framing.
REF
(DS2
Reframing
Mode)
The REF bit is used to trigger reframing. If a logic 1 is written to REF when it was previously logic 0, the FRMR is forced out-of-frame, and a
new search for frame alignment is initiated. Note that only a LOW-to-HIGH transition of the REF bit triggers reframing; multiple write opera-
tions are required to ensure such a transition.
1-0 Unused
Must be zero for normal operation.
REGISTER DESCRIPTION
48
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRMR INTERRUPT ENABLE
Read/Write Addresses: 41H, 51H, 61H, 71H, 81H, 91H, A1H
Reset Value:
00H
7
6
0
5
4
3
2
1
0
COFAE
REDE
FERFE
RESE
AISE
OOFE
0
Bit
Name
COFAE
(DS2 Change of
Frame Alignment
Enable)
Description
7
The COFAE bit is an interrupt enable. A change of frame alignment (COFA) event causes the interrupt output to be set HIGH when
the COFAE bit is written with a logic 1.
6
5
Unused
Must be zero for normal operation.
REDE
(DS2 Red Alarm
Enable)
The REDE bit is a interrupt enable. A change of state on a corresponding DS2 FRMR status causes the interrupt output INTB, to be
asserted low when the corresponding interrupt enable bit is written with a logic 1.
4
3
FERFE
(DS2 Far End
Receive Error Enable)
The FERFE bit is a interrupt enable. A change of state on a corresponding DS2 FRMR status causes the interrupt output INTB, to be
asserted low when the corresponding interrupt enable bit is written with a logic 1.
RESE
The RESE bit is an interrupt enable. A change in the debounced value of the reserved bit in Set II when in G.747 mode causes the
(Reserved Bit Enable) interrupt output to be set HIGH when the RESE bit is written with a logic 1. The debounced value of the reserved bit only changes
when the reserved bit is the same for two consecutive frames. The RESE bit has no effect in DS2 mode The interrupt output, INTBm
is deasserted when the Interrupt Status Register is read if its assertion was a result an OOF, AIS, FERF, RED, RES, or COFA event.
2
AISE
The AISE bit is a interrupt enable. A change of state on a corresponding DS2 FRMR status causes the interrupt output INTB, to be
asserted low when the corresponding interrupt enable bit is written with a logic 1.
(DS2 Alarm
Indication Signal
Interrupt Enable)
1
0
OOFE
(DS2 Out of Frame
Interrupt Enable)
The OOFE bit is a interrupt enable. A change of state on a corresponding DS2 FRMR status causes the interrupt output INTB, to be
asserted low when the corresponding interrupt enable bit is written with a logic 1.
Unused
Must be zero for normal operation.
REGISTER DESCRIPTION
49
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRAMER INTERRUPT STATUS
Read/Write Addresses: 42H, 52H, 62H, 72H, 82H, 92H, A2H
Reset Value:
00H
7
6
0
5
4
3
2
1
0
COFAI
REDI
FERFI
RESI
AISI
OOFI
0
Bit
Name
COFAI
(DS2 Change of
Frame Alignment
Indication)
Description
7
The COFAI bit is an interrupt status indicator. As per TR-TSY-000820, the Change of Frame Alignment (COFA) interrupt is only
asserted if a frame search results in a frame alignment which is different from the prior frame alignment.
6
5
Unused
Must be zero for normal operation.
REDI
(DS2 Red Alarm
Interrupt Indication)
The REDI bit is a interrupt status indicator. A change of state on the corresponding DS2 FRMR status causes the corresponding
interrupt status bit to be set to logic 1.
4
FERFI
The FERFI bit is a interrupt status indicator. A change of state on the corresponding DS2 FRMR status causes the corresponding
interrupt status bit to be set to logic 1.
(DS2 Far End
Receive Frame
Interrupt Indication)
3
2
RESI
(DS2 Reserved Bit
Indication)
The RESI bit is an interrupt status indicator. A change in the debounced value of the reserved bit in Set II when in G.747 mode
causes this bit to be set to logic 1. The debounced value of the reserved bit only changes when the reserved bit is the same for two
consecutive frames, This bit has no effect in DS2 mode.
AISI
The AISI bit is a interrupt status indicator. A change of state on the corresponding DS2 FRMR status causes the corresponding inter-
(DS2 Alarm Indication rupt status bit to be set to logic 1.
Signal Interrupt
Indication)
1
0
OOFI
The OOFI bit is a interrupt status indicator. A change of state on the corresponding DS2 FRMR status causes the corresponding
interrupt status bit to be set to logic 1.
(DS2 Out of Frame
Violation Interrupt
Indication.
Unused
Must be zero for normal operation.
REGISTER DESCRIPTION
50
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRAMER STATUS
Read/Write Addresses: 43H, 53H, 63H, 73H, 83H, 93H, A3H
Reset Value:
00H
7
0
6
0
5
4
3
2
1
0
REDV
FERFV
RESV
AISV
OOFV
0
Bit
Name
Description
7-6 Unused
Must be zero for normal operation.
5
4
REDV
(DS2 Red Alarm
Violation)
The REDV bit is a logic 1 if an out-of-frame condition has persisted for 9.9ms (6.9ms in G.747 mode). This is less than 1.5 times the
maximum average reframe time allowed. The REDV status will remain asserted for 9.9ms (6.6ms in G.747 mode) after frame align-
ment has been declare and then become logic 0.
FERFV
The FERFV bit in this register reflects the status of the corresponding DS2 FRMR value. In DS2 mode, the FERFV bit reflects the
debounced state of the X bit (first bit of the M4-Subframe). If the X-bit has been a ZERO for two consecutive M-frames, the FERFV bit
becomes a logic 1. If the X-bit has been a one for two consecutive M-frames, the FERFV bit becomes a logic 0.
In G.747 mode, FERFV bit reflects the debounced state of the Remote Alarm Indication (RAI, bit 1 of Set II) bit. If the RAI bit has
been a one for two consecutive frames, the FERFV bit becomes logic 1. If the RAI bit has been a zero for two consecutive frames,
the FERFV bit becomes a logic 0.
(DS2 Far End
Receive Frame
Violation)
A six frame latency of the FERFV status ensures a virtually 100% probability of freezing correctly in DS2 mode upon an out-of-frame
condition and a better than 99.9% probability of freezing correctly in G.747 mode.
3
2
1
0
RESV
(DS2 Reserved Bit
Violation)
The RESV bit reflects the debounced state of the reserved bit in Set II when in G.747 mode. The debounced value of the reserved bit
only changes when the reserved bit is the same for two consecutive frames.
AISV
The AISV bit in this register reflects the status of the corresponding DS2 FRMR value. The AISV bit is a logic 1 if AIS has been
(DS2 Alarm Indication declared.
Signal Violation)
OOFV
(DS2 Out of Frame
Violation)
The OOFV bit in this register reflects the status of the corresponding DS2 FRMR value. The OOFV bit is a logic 1 if the DS2 framer is
presently out-of-frame.
Unused
Must be zero for normal operation.
REGISTER DESCRIPTION
51
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRAMER MONITOR INTERRRUP ENABLE/STATUS
Read/Write Addresses: 44H, 54H, 64H, 74H, 84H, 94H, A4H
Reset Value
00H
7
6
0
5
0
4
0
3
0
2
1
0
0
INTE
INTR
OVR
Bit
Name
Description
7-3 Unused
Must be zero for normal operation.
2
INTE
(DS2 Interrupt
Enable)
The interrupt enable (INTE) bit allows the DS2 FRMR to assert the INTB output upon register transfers. A logic 1 in the INTE bit posi-
tion enables the DS2 to generate a microprocessor interrupt when the counter values are transferred to a Holding Registers. A logic
0 in the INTE bit position disables the DS2 FRMR from generating an interrupt. When the TSB is reset, the INTE bit is set to logic 0,
disabling the interrupt. The interrupt is cleared when this register is read if its assertion was a result a transfer operation.
1
0
INTR
(DS2 Interrupt)
The interrupt (INTR) bit indicated the current status of the internal interrupt signal. A logic 1 in this bit position indicates that a transfer
of counter values to the Holding Registers has occurred; a logic 0 indicates that no transfer has occurred. This bit is set to logic 0
when this register is read. The value of the INTR bit is not affected by the value of the INTE bit.
OVR
(DS2 Overrun)
The overrun (OVR) bit indicates the overrun status of the Holding Registers. A logic 1 in this bit position indicates that a previous
interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the Holding Registers have
been overwritten. A logic 0 indicates that no overrun has occurred. This bit is reset to logic 0 when this register is read. To generate a
transfer of the counters to the holding registers, a microprocessor write to the Global PMON Update Register is required.
DS2 FRMR FERR COUNT
Read/Write Addresses: 45H, 55H, 65H, 75H, 85H, 95H, A5H
Reset Value:
00H
7
6
5
4
3
2
1
0
FERR7
FERR6
FERR5
FERR4
FERR3
FERR2
FERR1
FERR0
Bit
Name
Description
7-0 FERR7-0
(DS2 Framing Bit
Error)
This register indicates the number of DS2 framing bit error events or G.747 framing word errors that occurred during the previous
accumulation interval. A DS2 framing bit error event is either an M-bit or and F-bit error. One or more bit errors in a G.747 frame
alignment signal results in a single framing word error. A transfer operation can be triggered by writing to the Global PMON Update
Register.
REGISTER DESCRIPTION
52
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2 FRMR PERR COUNT (LSB)
Read/Write Addresses: 46H, 56H, 66H, 76H, 86H, 96H, A6H
Reset Value:
00H
7
6
5
4
3
2
1
0
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
Bit
Name
Description
These registers indicate the number of G.747 parity events that occurred during the pervious accumulation interval.
7-0 PERR 7-0
(DS2 Parity Bit Error) A transfer operation can be triggered by writing to the Global PMON Update Register
DS2 FRMR PERR COUNT (MSB)
Read/Write Addresses: 47H, 57H, 67H, 77H, 87H, 97H, A7H
Reset Value:
00H
7
6
0
5
0
4
3
2
1
0
0
PERR12
PERR11
PERR10
PERR9
PERR8
Bit
Name
Description
7-5 Unused
Must be zero for normal operation.
4-0 PERR 12-8
(DS2 Parity Bit Error)
These registers indicate the number of G.747 parity events that occurred during the pervious accumulation interval.
A transfer operation can be triggered by writing to the Global PMON Update Register
REGISTER DESCRIPTION
53
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX12 CONFIGURATION AND CONTROL
Read/Write Addresses: 48H, 58H, 68H, 78H, 88H, 98H, A8H
Reset Value:
00H
7
6
5
4
3
2
1
0
G747
PINV
MINV
FINV
XAIS
XFERF
XRES
INTE
Bit
Name
Description
7
G747
When G747 is HIGH, the MX12 supports CCITT Recommendation G.747. In this mode, three 2048b/bits tributaries are multiplexed
(G747 Configuration)
into and demultiplex out of a 840 bit frame. If G747 is LOW, the frame is compatible with DS2 as specified in the ANSI T1.107 Stan-
dard.
6
5
4
PINV
When PINV is set HIGH, the transmitted parity bit in the G.747 formatted output stream is inverted for diagnostic purposes. This
(G747 Parity Inversion) only has effect when the G747 bit is HIGH.
MINV
When MINV is set HIGH, the transmitted M bits in the DS2 output stream are inverted for diagnostic purposes. This only has effect
(G747 M-Bit Inversion) when the G747 bit is LOW.
FINV
When FINV is set HIGH and G747 is LOW, all the transmitted F bits in the DS2 output stream are logically inverted for diagnostic
(G747 F-Bit Inversion)
purposes. If G.747 is HIGH when FINV is set HIGH, the nine bit frame alignment signal (111010000) is logically inverted (i.e.
000101111).
3
2
XAIS
(Transmit AIS)
When set HIGH, the XAIS bit enables the transmission of the alarm indication signal (AIS) in the 6312kbit/s output stream. When
XAIS is set HIGH, the transmitted data is set to all ones; otherwise the transmitted data is not affected.
XFERF
(Transmit Far End
Receive Failure)
When set HIGH, the XFERF bit enables the transmission of the far end receive failure (FERF0 signal in the DS2 output stream
when in DS2 mode (i.e.G747 bit LOW). When XFERF is set HIGH, the transmitted X bit is set to 0, provided that AIS is not being
transmitted; otherwise the transmitted X bit is set to 1. When in G.747 mode (i.e. G747 bit HIGH), the remote alarm indication (RAI)
is set to 1 when XFERF is set HIGH; otherwise, the transmitted RAI bit is set to 0 unless AIS is being transmitted.
1
0
XRES
The XRES bit only has effect in G.747 mode. When XRES is set HIGH and AIS is not being transmitted, the reserved bit (Set II, bit
(Transmit Reserved Bit) 3) is set to 0; otherwise, the transmitted reserved bit is set to 1.
INTE
When set HIGH, the INTE bit enables the activation of the interrupt output, INTB, whenever any of the LBRI 4-1 bits are set HIGH
(LoopbackRequirement in the Loopback Request Interrupt register. Interrupts are masked when INTE is cleared LOW.
Interrupt Enable)
REGISTER DESCRIPTION
54
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX12 LOOPBACK CODE SELECT REGISTER
Read/Write Addresses: 49H, 59H, 69H, 79H, 89H, 99H, A9H
Reset Value:
00H
7
6
0
5
0
4
0
3
0
2
0
1
0
0
LBCODE1
LBCODE0
Bit
Name
Description
7-2 Unused
Must be zero for normal operation.
1-0 LBCODE1-0
The LBCODE 1-0 bits select the valid state for a loopback request coded in the C-bits of the DS2 signals. Transmit and receive are
not independent; the same code is expected in the demultiplexed DS2 as is inserted in the DS2 to be multiplexed. The following table
gives the correspondence between LBCODE 1-0 bits and the valid codes:
(Loopback Code)
LBCODE 1-0
Loopback Code
00
01
10
11
C1 = C2 and C1 = C3
C1 = C3 and C1 = C2
C1 = C3 and C1 = C2
C1 = C2 and C1 = C3
If LBCODE 1-0 is ‘b00 or ‘b11, the loopback code is as per ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7. Because
TR-TSY-000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback com-
mand possibilities are also supported. The LBCODE 1-0 bits will also select the valid state for a loopback request coded in the C-bits
of the G.747 formatted signal. Again, the transmit and receive are not independents; the same code is expected in the demultiplexed
G.747 stream as is inserted in the G.747 stream to be multiplexed. The valid codes are the same as those for the DS2 formatted
stream given in the table above. The LBCODE 1-0 bits become logical 0 upon either a hardware or software reset.
REGISTER DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX12 AIS INSERT REGISTER
Read/Write Addresses: 4AH, 5AH, 6AH, 7AH, 8AH, 9AH, AAH
Reset Value:
00H
7
6
5
4
3
2
1
0
MAIS4
MAIS3
MAIS2
MAIS1
DAIS4
DAIS3
DAIS2
DAIS1
Bit
Name
Description
7-4 MAIS4-1
(M12 MUX Alarm
Indication Signal)
Setting any of the MAIS [4:1] bits activate insertion of the alarm indication signal (all ones) into the corresponding LOW speed stream
multiplexed into the 6312kbits HIGH speed output signal. Mux AIS insertions takes place before the point where remote loopback
may be invoked using the Loopback Activate register and thus mux AIS cannot be inserted while a loopback is activated.
3-0 DAIS4-1
Setting any of the DAIS 4-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding LOW speed stream
demultiplexed from the 6312kbits HIGH speed input signal. Demux AIS insertion takes place after the point where remote loopback
may be invoked using the Loopback Activate register thus demux AIS to be inserted into the through path while a loopback is acti-
vated, if desired.
(M12 DeMux Alarm
Indication Signal)
MX12 LOOPBACK ACTIVATE REGISTER
Read/Write Addresses: 4BH, 5BH, 6BH, 7BH, 8BH, 9BH, ABH
Reset Value:
00H
7
6
5
4
3
2
1
0
ILBR4
ILBR3
ILBR2
ILBR1
LBA4
LBA3
LBA2
LBA1
Bit
Name
Description
7-4 ILBR 4-1
In DS2 mode, setting any of the ILBR 4-1 bits enable the insertion of a loopback request in the corresponding DS1 stream in the DS2
output signal. The format of the loopback request is determined by the LBCODE 1-0 bits in the Loopback Code Select MX12 Regis-
ter. In G.747 mode, ILBR[j] inverts bit Cj1, Cj2, or Cj3 in the G.747 frame in an analogous fashion.
(Insertion Loopback
Request)
3-0 LBA 4-1
Setting any of the LBA 4-1 bits activates loopback of the corresponding LOW speed stream from the HIGH speed input signal to the
(Loopback Activation) HIGH speed output signal. LBA4 has no effect in G.747 mode, but LBA 3-1 activates the loopback of the corresponding 2048kbits
signals. The demultiplexed DS1 signals continue to present valid payloads while loopbacks are activated. The MX12 AIS Insert Reg-
ister allows insertion of DS1 AIS if required.
REGISTER DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MX12 LOOPBACK INTERRUPT REGISTER
Read/Write Addresses: 4CH, 5CH, 6CH, 7CH, 8CH, 9CH, ACH
Reset Value:
00H
7
6
5
4
3
2
1
0
LBRI4
LBRI3
LBRI2
LBRI1
LBRD4
LBDR3
LBDR2
LBDR1
Bit
Name
Description
7-4 LBRI4-1
The LBR 4-1 bits are set HIGH when a loopback request is asserted or deasserted for the corresponding LOW speed stream in the
HIGH speed input signal. The LBR 4-1 bits are set HIGH whenever the corresponding LBRD 4-1 bits change state. If interrupts are
enabled using the INTE bit in the Configuration register then the interrupt output, INTB is activated. The LBRI 4-1 bits are cleared
LOW immediately following a read of the register, acknowledging the interrupt and deactivating the INTB output.
(Loopback Request
Interrupt)
3-0 LBRD4-1
The LBRD 4-1 bits are set HIGH while a loopback request is detected for the corresponding LOW speed stream in the HIGH speed
input signal. The LBRD 4-1 bits are set LOW otherwise. The format of the loopback request expected is determined by the LBCODE
1-0 bits in the MX12 Loopback Code Select Register. As per TR-TSY000009 Section 3.7, the loopback request must be present for
five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for
five successive M-frames.
(Loopback Request
Detached)
DS1 TRANSMIT AND RECEIVE EDGE SELECT
Read/Write Addresses: 4DH, 5DH, 6DH, 7DH, 8DH, 9DH, ADH
Reset Value:
00H
7
6
5
4
3
2
1
0
TXESEL4
TXESEL3
TXESEL2
TXESEL1
RXESEL4
RXESEL3
RXESEL2
RXESEL1
Bit
Name
Description
Transmit Edge Select when 0 the DS1 data will be transmitted on the rising edge of TD1CLK. When 1 the DS1 data will be transmit-
7-4 TXESEL4-0
(DS1 Transmit Edge ted on the falling edge of TD1CLK.
Select)
3-0 RXESEL4-0
(DS1 Receive Edge
Select)
Receive Edge Select when 1 the DS1 data will be sampled on the rising edge of RD1CLK. When 0 the DS1 data will be sampled on
the falling edge of RD1CLK.
REGISTER DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
REGISTER DESCRIPTION
58
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1 DS3 Framer
The nominal DS3 interface is 44.736 Mb/s ± 20ppm (± 895 b/s).
The DS3 frame contains a total of 4,760 bits of which there are 4,704
payload bits and 56 overhead bits. The total period of a DS3 frame is
106.4µs (44.736E-6 x 4,760).
A DS3 M-frame (Multiframe) is composed of seven DS3
M-subframes. Each M-subframe contains eight blocks of 84 payload bits
(bit-interleaved from the seven DS2 or 28 DS1 streams) plus one
overhead bit (the seven subframes do not represent each separate DS2
signals).
External OH
FIFO
FIFO
DS2
DS2
OH Stuffing
B3ZS
Encoder
1:7
TDAT
DS3 Framer
M23 / C-bit Mode
DS2
DS2
B3ZS
Decoder
RDAT
DS3 Framer
1:7
External
OH
Status
6143 drw 31a
Figure 1 DS3 Framer Block
Nominal DS2 rate 6,312kbits/sec and multiplexing four tributaries @1,544kbit/s (6,176kbit/s)
Nominal DS3 rate 44.736Mb/s and Multiplexing seven tributaries @ 6,312kbits/sec
680 Bits
C2
X1
X2
P1
P2
84-Bits
84-Bits
84-Bits
84-Bits
F1
F1
F1
F1
84-Bits
84-Bits
84-Bits
84-Bits
C1
C1
C1
C1
84-Bits
84-Bits
84-Bits
84-Bits
F2
F2
F2
F2
84-Bits
84-Bits
84-Bits
84-Bits
84-Bits
84-Bits
84-Bits
84-Bits
F3
84-Bits
C3
C3
C3
C3
84-Bits
84-Bits
84-Bits
84-Bits
F4
F4
F4
F4
84-Bits
84-Bits
84-Bits
84-Bits
M Sub-Frame
C2
C2
C2
F3
F3
F3
84-Bits
84-Bits
84-Bits
M Frame
M1
M2
M3
84-Bits
84-Bits
84-Bits
F1
F1
F1
84-Bits
84-Bits
84-Bits
C1
C1
C1
84-Bits
84-Bits
84-Bits
F2
F2
F2
84-Bits
84-Bits
84-Bits
C2
C2
C2
84-Bits
84-Bits
84-Bits
F3
F3
F3
84-Bits
84-Bits
84-Bits
C3
C3
C3
84-Bits
84-Bits
84-Bits
F4
F4
F4
84-Bits
84-Bits
84-Bits
Stuff Block
6143 drw19
Figure 2 DS3 Frame
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Framing is declared if the M-bits are correct for three consecutive
M-frames (and no F-bits error is detected).
1.1.1 Framing modes
1.1.1.1 M23 Mode
X-bits and P-bits are ignored
In M23 Mode the three C-bits per DS3 M-subframe indicate the
nature of stuff opportunity bit in the last block of the M-subframe. Stuffing
is further explained in the M23 section.
1.1.2.2 Max Time
The MART, maximum average reframing time (the average time
necessary when processing all the bits in the M-frame), is 1.5ms.
Framing goes from DS3 framing to DS2 framing.
1.1.1.2 C-bit Parity Mode
In C-bit parity mode the DS2s operate at the nominal DS2 rate and
thus no stuffing is required. As such all the stuff opportunity bits contain
stuffing (null bit) and the C-bits are used to carry performance
monitoring, alarm, control and Data Link channel.
1.1.3 Errors and Alarms
1.1.3.1 Line Management
All the alarms and errors associated with line management must be
processed if the coding/decoding function is implemented. The 82V8313
will manage the DS3 LIU (counting and reporting errors). But the DS3
LIU has to control the DS3 line (encoding / decoding and errors detec-
tion).
1.1.1.3 Transparent Mode
1.1.2 Reframing
1.1.2.1 Procedure
The search of frame alignment (based on F-bits and M-bits) will
happen in two cases:
1.1.3.1.1 BnZS coding overview
BnZS corresponds to an AMI line code with the substitution of a
unique code to replace occurrences of n consecutive zero signal
elements. For DS3 lines, a B3ZS code (three-zero substitution) is used.
In the B3ZS format, each block of three consecutive zeros is removed
and replaced by a B0V or 00V code:
After a reset.
After an internal out of frame (OOF) declaration.
When the microprocessor forces the reframing process.
The algorithm of reframing is based on the following steps:
B represents a pulse conforming to the bipolar rule.
The DS3 framer will search for the F-bits in order to find one
potential M-subframe alignment.
0 is a zero (no pulse).
V represents a pulse violating the bipolar rule.
Then the DS3 framer will process the M-bits to detect the M-Frame
structure (X-bits and P-bits are ignored during the reframing
operation).
The choice of B0V or 00V is made so that the number of B pulses
between consecutive V pulses is odd. For DS1 lines, a B8ZS code is
used (no more than seven consecutive zeros on a DS1 line).
1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0
E
E
O
B
V
B
V
O
O
V
E
O
V
6143 drw53
Figure 3 B3ZS Coding
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1.3.1.2 Bipolar Violation description
Indicate to the receiving equipment that there is a transmission
interruption located either at the equipment originating the AIS
signal or upstream of that equipment (AIS is sent downstream until
the incoming signal becomes correct again).
Bipolar Violation Error (BPV) is declared when a pulse presents the
same polarity as the previous “1” while also not following the B3ZS
coding. This is the mechanism used to determine if there is a true line
code violation or if there is a substitution. For each DS3 Line Code Viola-
tion the 82V8313 will increment the DS3LCV Count Register (0x14 and
0x15).
Different events can be declared as AIS:
Incoming signal with valid framing (M and F-bits), valid parity, all
DS3 stuff indicators C-bits set to 0, X-bits set to 1 and repeated
information pattern 1010... (A 1 immediately following any of the
control bit position) shall be identified as being DS3 AIS.
1.1.3.1.3 Excessive zeros error description
EXZ is declared on occurrence of more than n consecutive zeros for
BnZS coded signal. For each EXZ violation the 82V8313 will increment
the DS3 EXZS Count Register (0x18 and 0x19).
Unframed all-ones signal = Blue code.
Framed DS3 signal with the repeated payload pattern 1010.
Framed DS3 arbitrary pattern with all DS3 stuff indicators C-bits set
to 0.
1.1.3.1.4 LOS description
Framed DS3 1010 pattern with all DS3 stuff indicators C-bits set to
0.
A LOS defect occurs when there are 175 ± 75 contiguous pulse posi-
tions shifted in the device with no pulses of either positive or negative
polarity at the line interface. A LOS defect is ended when there is a
detection of an average pulse density of at least 33% (for T3 Line) over
a same period (12.5% for T1 Line). LOS failure is declared when LOS
defect persists for 2.5 ± 0.5s. LOS failure is cleared when LOS defect is
absent for 10 ± 0.5 seconds for T3 Line (20 seconds or less for T1 Line).
A LOS is indicated in the DS3 Framer Interrupt Status Register (0x36)
and the DS3 Framer Status (0x37).
Framed all-ones signal (the overhead bits are ignored).
OOF detection implies to insert AIS downstream in 2.25 to 3ms. LOS
or incoming AIS implies to send AIS downstream in maximum 0.15ms
(0.1 MART). AIS defect occurs upon detection of AIS in contiguous
M-frames for a time T, 0.2ms ≤T≤100ms. This defect must be detected
and cleared properly in the presence of a random BER 10-3.
In GR-499-CORE, it is specified that AIS defect detection and termi-
nation must be done in 2.3ms (1.5 x MART) and maximum removal time
is 0.15ms (0.1 x MART).
1.1.3.2 OOF (Out of Frame)
OOF shall be declared when there is a significant ratio of frame align-
ment, F-bit, errors. The typical ratio is three (or more) errors out of 16 (or
fewer) consecutive framing F-bits—a sliding window methodology is
implemented in the 82V8313. The algorithm used is a logical ORing of 1
(or more) M-bit errors in 2 (or more) out of 4 (or fewer) consecutive
M-frames with the F-bit error criteria. The OOF defect is ended when the
signal does not contain any more framing bits (F-bits and M-bits) error in
several consecutive frames (1 M-frame or more). The defect detection
and termination must be done in less than 2.3ms (1.5 times the
Maximum Average Reframe Time (MART). The 82V8313 can be config-
ured for either 3 out of 16 consecutive F-bit errors or 3 out of 8 consecu-
tive F-bit errors (DS3 Framer Configuration Register 0x34). OOF
violations are monitored in the DS3 Framer Status Register (0x37).
The 82V8313 has an integration counter which decrements for each
invalid M-frame and increments the integration counter. In slow
detection mode the count saturates 127 which results in a detection time
of 13.5ms. In fast detection mode the saturation point is 21 and results in
a detection time of 2.23ms.
DS3 AIS failure is declared if an AIS defect persists for 2.5 ± 0.5 s.
AIS failure is cleared if AIS defect is absent for 10.0 ± 0.5 s. Typically an
Alarm Indication Signal Counter on the system is incremented each time
an AIS failure appears. On the downstream data flow, two strategies
must be activated during AIS defect:
Continue data processing with the last correct frame alignment
(off-line framer).
1.1.3.3 RED ALARM
RED defect is defined by the occurrence of OOF or LOS in one
M-frame.
Note: due to the amount of errors (AIS, LOF or LOS failure
activated), incoming data can have a M23 and M12 stuffing
ratio between 0 and 100%. In the worst case, some applica-
tions can have problems due to DS1 clock deviation: DS1
clock can vary between 1.544 MHz ± 1745 ppm and 1.544
MHz – 3218 ppm.
1.1.3.4 LOF (Loss of Frame)
Loss of Frame:
LOF is declared when the OOF persists for 2.5 ± 0.5 s.
Send a full 1’s signal to the HDLC controller:
LOF is cleared when the OOF defect is absent for 10.0 ± 0.5 s.
Send downstream full 1’s (stopping DS2 and DS1 framers allowed: in
that case, a full 1’s signal must be sent downstream the DS1 signals).
FCP (Failure Count Path) is incremented each time LOF failure
appears.
1.1.3.5 AIS
AIS signal is transmitted downstream (instead of the normal signal
to):
Maintain transmission continuity
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1.3.6 RAI (Remote Alarm Indication)
1.1.3.6.1 RAI for C-bit Parity Mode
The RAI signal has to be immediately transmitted upon declaring
LOS failure, LOF or AIS failure. An RAI failure is declared as soon as
any of the four following alarm signals are detected on the far-end alarm
channel (FEAC, explained the following section):
TABLE 3 —FERF Status (X1 & X2 State)
X1
X2
FERF Status
0
0
1
1
0
1
0
1
1
Previous State
Previous State
0
Equipment failure (service affecting)
LOS failure, LOF or AIS failure.
RAI failure is cleared as soon as the absence of all of the above
alarm signals is detected. A system counter must be incremented by
one each time the RAI failure begins.
1.1.3.9 Idle Signal
If implemented, the idle signal must have correct M-bits, F-bits and
P-bits. The 3 C-bits in subframe 3 of the M-frame must be set to 0 and all
other C-bits can take any values (and may vary with time). The X-bits
shall be set to 1 and the repeated information pattern 1100 must be sent
(started with 11 after each M-frame alignment, M-subframe alignment, X-
bit, P-bit and C-bit). Such a signal is used before the customer initializes
the channel to avoid declaration of alarm. The identification of the idle sig-
nal should not exceed 10 seconds in duration.
1.1.3.6.2 RAI for M23 Mode
RAI failure is declared when the far-end SEF/AIS defect (if
implemented, X-bits) persists for 2.5 ± 0.5s. The RAI failure is cleared
when SEF/AIS disappears for 10.0 ± 0.5s. A counter must be incre-
mented by one each time the RAI failure begins.
1.1.3.7 Parity error
The 82V8313 uses even parity, which is defined as: if the digital sum
of all information bits (4704 bits in the M-frame) is equal to 1 in the
previous M-frame, the two P bits are set to 1 (similar for 0).
1.1.3.10 C-bits signification if C-bit parity mode
activated
The C-bit parity mode (see M23 chapter) affected C-bits for special
Error is indicated if the received P-bits do not match the locally
calculated parity, or when the two P-bits do not agree. P-bit errors are
counted in the P-bit Error Register (0xA and 0xB).
purposes (no more stuffing bit indicators):
Parity Error Ratio, PER, is typically defined as the number of Parity
errors detected divided by the number of M-frames examined.
1.1.3.8 X-bit: FERF ( Far-End SEF/AIS = RDI)
The two X-bits must be equal in an M-frame.
If X1 = X2 = 0, the Far End Receive Failure (FERF) is declared as
soon as a valid framing is not identified or AIS is received.
FERF status remains in the previous state in the following cases:
If X1 ≠ X2
If OOF is detected: FERF status can be updated only after having
completely processed the current incoming M-frame. If the current
M-frame is numbered n, the last valid FERF information comes from
M-Frame numbered n-2 (error can start in end of M-frame n-1 and
can be declared at the beginning of M-Frame n).
The X-bits must not change more than once per second.
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 4 —C-BIT PARITY MODE DS3 C-BIT ASSIGNMENTS
M-SUBFRAME
NUMBER
C-BIT
FUNCTION
NUMBER
1
2
3
4
5
6
7
1
2
3
Application Identifications
Reserved for future network use
Far-End Alarm and Control (FEAC)
1
2
3
Unused
Unused
Unused
1
2
3
CP (Parity)
CP (Parity)
CP (Parity)
1
2
3
Far-End Block Error (FEBE)
Far-End Block Error (FEBE)
Far-End Block Error (FEBE)
1
2
3
Data Link (DL)
Data Link (DL)
Data Link (DL)
1
2
3
Unused
Unused
Unused
1
2
3
Unused
Unused
Unused
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1.3.10.1 AIC
The Application Identification Channel is used to identify the specific
DS3 M-frame application:
Listing order is in decreasing priority order. Codewords shall be
transmitted continuously for the duration of the condition being
reported, or 10 repetiions whichever is longer.
Control messages are higher in priority then any of the far end alarm
signals.
In M23 mode: AIC shall be random 1s and 0s.
In C-bit Parity mode: AIC shall be set to 1 (In this mode, AIC is not
The idle state of the FEAC channel (no codeword is transmitted) is a full
ones signal. A code is correct (no error during transmission) after being
received 10 times. Some implementations also use algorithms that take
care of BER: a valid BOC message is declared if a code is received 4 out
of 5 times, or 8 out of 10 times as determined by the AVC bit in the FEAC
Configuration Register (0x32).
sufficient for determining identification of C-bit parity application.
The process needs the confirmation by secondary methods such as
the presence of 0s in the FEBE bit positions)
Unchannelized applications may have either any AIC value (if
developed before ANSI T1.107 — 1995 standards) or all 1s (as
C-bit parity mode). The process to identify the DS3 application
should typically not exceed 10 seconds in duration.
1.1.3.10.2 FEAC
Far End Alarm and Control signals are encoded into repeating 16-bit
0xxxxxx011111111 codewords (right-most bit transmitted first): the 6–bits
x allowed 64 distinct signals; assigned codewords GR-499-Core code
words areincluded for reference:
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TABLE 5 —DS3 FEAC LOOPBACK CONTROL MESSAGES
Condition
Line Loopback Activate (4)
Codeword
0 000111 0 11111111
0 011100 0 11111111
0 011011 0 11111111
0 1---n--- 0 11111111
Line Loopback Deactivate (4)
DS3 Line
DS1 Line Number n
(1£ n £ 28) (5)
DS1 Line - All
0 010011 0 11111111
TABLE 6 —DS3 FEAC ALARM AND STATUS MESSAGES
Function
Codeword
DS3 Equipment Failure (Sa)
DS3 LOS (1)
0 011001 0 11111111
0 001110 0 11111111
0 000000 0 11111111
0 010110 0 11111111
0 011010 0 11111111
0 001111 0 11111111
0 011101 0 11111111
0 010101 0 11111111
0 000101 0 11111111
DS3 OOF
DS3 AIS Received
DS3 Idle Signal Received
DS3 Equipment Failure (Nsa)
Common Equipment Failure (Nsa)
Multiple DS1 LOS (2 and 3)
DS1 Equipment Failure (Sa) (3)
NOTES
Sa: Service affecting.
Nsa: Non-service affecting Single DS1 LOS (2 and 3) 0 011110 0 11111111
1. Applicable to B2ZS-coded signal. DS1 Equipment Failure (Nsa) (3) 0 000011 0 11111111
2. Network equipment must not respond to or generate these codewords.
3. Applicable to all type of loopbacks.
4. Code must be transmitted 10 times, followed immediately by 10 repetitions of the DS3 or DS1 line codeword.
5. For Unchannelized DS3 applications, DS1s are unassigned.
*Listing order is in decreasing priority order. Codewords shall be transmitted continuously for the duration of the condition being reported, or 10 repetitions
whichever is longer.
**Control messages are higher in priority than any of the far end alarm signals.
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1.3.10.3 Bit Oriented Code Detector (BOC)
Oriented Code (XBOC) is designed to transmit BOCs in the DS3 C-bit
parity Far End Alarm and Control (FEAC) channel. The XBOC can
transmit 63 of the 64 possible BOCs, and purposefully ignores the
“111111” code which is similar to the idle HDLC flag sequence. BOCs are
transmitted in a FEAC channel as 16–bit sequences composed of an 8–
ones header, a zero six BOC bits, and a trailing 0 (“11111111xxxxxx0”).
The 16–sequence is repeated until disabled by forcing the six code bits
to “111111” Some of the common BOCs are listed here for reference.
The Receive Bit Oriented Code Detector (RBOC) is designed to
detect the presence of BOCs in the DS3 C-bit parity Far End Alarm and
Control (FEAC) channel. The RBOC recognizes 63 of the 64 possible
BOCs, and purposefully ignores the “111111” code which is similar to the
HDLC flag sequence. BOCs are received in a FEAC channel as 16–bit
sequences composed of an 8–ones header, a zero, six BOC bits, and a
trailing 0 (“111111110xxxxxx0”). In order to validate a BOC, the same
code must be repeated at least ten times with at least 8 of 10 or 4 out 5
times (as specified by the AVC bit) being the same.
The RBOC block will trigger an interrupt, unless masked, to indicate
the receipt of a BOC or when the BOC disappears. If the BOC receives
an invalid code the BOC bits will be set to “111111” The Transmit Bit
DS3 C-bit Parity FEAC
XBOC
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 0 15
Data
6 5 4 3 2 1
BOC_REG [6:1]
X X X X X X
6143 drw 35
Figure 4 Transmit BOC
DS3 C-bit Parity FEAC
RBOC
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1 1 1 1 1 1 1 0
15
Data
6 5 4 3 2 1
BOC_REG [6:1]
X X X X X X
6143 drw 36
Figure 5 Receive BOC
FUNCTIONAL DESCRIPTION
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3.3 VOLT M13 MULTIPLEXER
TABLE 7 —DS1 BIT ORIENTED CODES
COMMAND AND RESPONSE MESSAGE
TABLE 9 —DS1 BIT ORIENTED CODES
RESERVED MESSAGES
Function
Codeword
Under Study for Maintenance
0 010110 0 11111111
0 011010 0 11111111
Line Loopback Activate
0 000111 0 11111111
0 011100 0 11111111
0 001010 0 11111111
0 011001 0 11111111
0 001001 0 11111111
0 010010 0 11111111
0 010111 0 11111111
0 010000 0 11111111
0 001110 0 11111111
0 1---n--- 0 111111111
0 001100 0 11111111
0 010011 0 11111111
0 011000 0 11111111
0 000110 0 11111111
0 010001 0 11111111
0 010100 0 11111111
0 000010 0 11111111
0 000100 0 11111111
0 001000 0 11111111
0 1000000 0 11111111
0 111100 0 11111111
0 111110 0 11111111
Reserved for Network Use
0 001011 0 11111111
0 001101 0 11111111
0 001111 0 11111111
0 011101 0 11111111
Line Loopback Deactivate
Payload Loopback Activate
Payload Loopback Deactivate
For Network Use (Loopback Activate)
Universal Loopback Deactivate
ISDN Line Loopback (NT2)
C1/CSU Line Loopback
Reserved for Customer
RAI-CI
0 000011 0 11111111
0 000101 0 11111111
0 000010 0 11111111
0 011011 0 11111111
0 011111 0 11111111
NOTES:
For Network Use (NT1 Power Off)
Protection Switch Line n (1 ≤ n ≤ 27)
Protection Switch Acknowledge
Protection Switch Release
Do not use for synchronization
Status 2 Traceable
1. Sa-Service affecting
2. Nsa-Non Service Affecting
3. Applicable to B3ZS - coded signal
4. Newtork equipment must not respond to or generate these code
words.
5. Applicable to all types of loopbacks
6. Code must be transmitted 10 times, followed immediately by 10
repetition of the DS3 or DS1 line code word.
7. For unchannelized DS3 applications, DS1 are unassigned.
SONET Minimum Clock Traceable
Stratum 4 Traceable
1.1.3.10.4 Terminal-to-Terminal application
specific data link
The nine C-bits in M-subframes 2, 6 and 7 are reserved for
application specific uses in DS3 terminal equipment. If they are not
used, they will be set to one.
Stratum 1 Tracable
Synchronization Traceability Unknown
Stratum 3 Traceable
Reserved for NetworkSynchronization
Transmit Node Clock (TNC)
Stratum 3E Traceable
1.1.3.10.5 DS3 Path Parity Bits
The three CP-bits (Parity bits instead of stuffing indication in C-bit
parity mode) must be set to the same value as the two P-bits in the
M-frame structure. Some transport equipment in the network may alter
P-bits, but any intermediate equipment on the DS3 path typically does
not modify CP–bits. Parity error detection (also called Path Error) is
done by computing the parity of the information bits in the nth M-frame
and is compared to the result with the majority value of the CPbits
received in M-frame n + 1.
TABLE 8 —DS1 BIT ORIENTED PRIORITY
MESSAGES
RAI/Yellow Alarm
Loopback Retention
RAI-CI
0 000000 0 11111111
0 010101 0 11111111
0 011111 0 11111111
1.1.3.10.6 FEBE (Far End Block Error)
The three FEBE bits shall be set to any pattern other than 111 to
indicate a far-end CP-bits error or framing (M or F-bits) error. The
FEBE-bits are equal to 111 if no error is detected.
1.1.3.10.7 DS3PMON counters
The DS3 Performance Monitor is a collection of counter registers for
tracking C-bit Parity Errors (CPERR), Excessive Zeros Occurrences
(EXZS), Far End Block Errors (FEBE), Framing Bit Error (FERR), Line
Code Violations (LCV), and P-bit Parity Errors (PERR). Each counter
can be individually cleared and accessed via microprocessor. If the
counter is not cleared in an appropriate interval defined by the specific
counter register, the counter will stay at the maximum value and not
roll over.
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
During a microprocessor access to a PMON register, an internal
clock transfer signal is generated to transfer the internal count value to
the holding registers. Once this transfer is made the internal counter is
reset until the next interval. In this way, error events occurring during the
reset period are not missed. To preempt an overrun condition, whenever
a counter-to-holding-register transfer occurs, an interrupt is generated
(unless masked). However, if the holding register is not read since the
last interrupt, an overrun will occur and the overrun status bit in the
corresponding register will be set.
Messages shall be transmitted continuously at a minimum rate of
once per second (when no message is transmitted, the data link
contains the repeated idle pattern (“01111110”). The transmitting
terminal must perform zero stuffing to avoid flag pattern occurrence
between opening and closing flags (equipment in receives path must
suppress extra 0s). If the full length of an information field is not needed
(or if the field is not used), the ASCII null character shall be used to
indicate the end of the string. The remaining bit positions of the data field
can contain any combination of 1s and 0s. At any time, the abort code
can be also sent. A carrier may use this data link for the provisioning or
maintenance of the DS3 facility or network. That may cause interrup-
tions, delays or reduction of throughput on the data link. However, that
should not affect the timely transmission of the messages. If not used,
the three bits shall be set to 1.
1.1.3.10.8 Terminal-to-Terminal Path
Maintenance Data Link
The three C-bits in M-subframe 5 may be used as a 28.2 kbit/s
terminal-to-terminal data link for path maintenance data. Data link
protocol follows a subset of the LAPD specification (Recommendation
Q.921) with three messages defined (others are ignored):
TABLE 10 —DATA LINK FORMAT
Bit
Flag
Bit 8
0
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
0
SAPI
TEI
0
0
1
1
1
1
C/R
0
0
EA
EA
0
0
0
0
0
0
1
Control
0
0
0
0
0
0
1
1
76 or 82 Bytes
Information Field
Type (1 byte)
EIC (10 bytes
LIC (11 bytes)
FIC (10 bytes)
Unit (6 bytes)
Final Field (38 bytes)
FCS-16
2-8
2-0
2-15
2-7
NOTES:
1. C/R = 0 if DTE (from user side)
2. C/R = 1 if Carrier (from network side)
3. FCS: is the Frame Check Sequence CRC16 (can be disabled) Polynomial = x16 + x12 + x5 + 1
4. Type: identify type of message (1 byte) with the following value
- For PID message: 00111000 (76 byte info field)
- For ISID message: 00110100 (76 byte info field)
- For TSID message: 00110010 (76 byte info field)
- For ITU-T path ID: 00110010 (82 byte info field)
5. EIC: identify the specific piece of equipment (10 bytes).
6. LIC: identify a particular location (11 bytes).
7. FIC: identify where the equipment is located with in a building (10 bytes).
8. UNIT: identify the equipment location with in a bay (6 bytes).
9. Final field (38 bytes):
- For PID message: FI to identify a specific DS3 path
- For ISID message: PORT number to identify the port number of the equipment that initiated the idle signal.
-For TSID message: GEN nnumber to identify the signal generator that initiated the test signal.
FUNCTIONAL DESCRIPTION
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3.3 VOLT M13 MULTIPLEXER
1.1.3.10.7 Data Link Receiver
To prevent unintentional transmission of abort or flag characters, if
more than five consecutive ones exist in the raw transmit data of in the
CRC data, a zero is stuffed into the serial data output.
The RDL block first searches for the flag characters before
identifying the first byte of data where the RDL block then removes the
stuff bits, calculates the CRC-CCITT frame check sequence (FCS), and
then stores the framed data into a 4-level FIFO buffer. The RDL buffer
has an associated control buffer, which will indicate data ready, flag
detected, end of message (EOM) and overrun (OVR) status to maintain
the RDL.
The Data Link Section provides additional information about the data
link function.
1.1.3.11 DS3 Loopback
The DS3 can be looped back on the line level (asked by remote
equipment via FEAC message or local host decision). However, no
remote DS3 payload loopback is defined. In both these cases, transmit
and receive clocks can be of a different frequency (independent clocks).
In that case, a slip buffer must be provided in order to manage the
discrepancy between the incoming and outgoing data streams. When
the slip buffer underrun (transmit clock faster than receive clock) or
overflow (transmit clock slower than receive clock) an alarm is gener-
ated (these events must also be counted).
In an EOM condition, the Status Register also indicates the FCS
status and the number of valid bits in the last data byte of the message.
An interrupt will be generated not only when the FIFO reaches a
programmable threshold, but also when an abort sequence, FIFO
overrun, or terminating flag sequence are detected.
1.1.3.10.8 Data Link Transmitter
The XDL transmitter is designed to provide a serial path for HDLC
data in C-bit parity applications. The XDL transmitter, will automatically
perform data serialization, CRC generation, bit-stuffing, flag generation,
idle sequence, and abort sequence. The XDL transmitter performs all of
the necessary signaling to maintain the channel. An interrupt is provided
so that a double buffered transmit data register remains full for the
duration of the message. The XDL at the end of the frame will
automatically calculate the CRC-CCITT FCS if enabled. Once the frame
is complete the XDL will transmit idle codes until the following frame
begins. Should an underrun condition occur, the XDL transmitter will
automatically transmit an abort sequence and notify the controlling
processor via the XDL Status Register UDR status bit. An underrun
occurs when, the controller does not write a word to the transmit data
register before the previous byte has been transmitted. Also, at any
time, an abort sequence can be continuously transmitted by setting the
ABT control bit in the XFDL TSB Configuration Register (0x20).
For more information on the loopback capability see the Loopback
Section.
1.1.3.12 Jitter
Jitter is the short-term variations of digital edges from their ideal
positions in time. Short-term variations are phase oscillations of
frequency greater than 10Hz (variations at frequency under 10 Hz are
defined as wander). Jitter amplitude is measured in unit intervals (UI)
where one UI is the phase deviation of one clock period.
T 0
1 U I
The XDL can also be enabled to continuously transmit a flag
character “01111110.” The data flow sequence for the XDL works as
such:
1. Step 1 continues until the all bytes for the frame are written.
2. Transmit data bytes are written to the Transmit Data register.
3. The XDL prepares the byte by performing a serial-to-parallel
conversion of the byte.
4. An interrupt is generated to signal the controller to write the next
byte.
T j
0 . 5 U I
6143 drw55
5. After the last byte is written to the transmit data register, the EOM
bit in the XDL configuration register should be set or the
TDLEOMI pin should be set to indicate the end of message.
6. The XDL sends the last data byte and then the CRC word is sent
(if enabled) or a flag (if CRC is not enabled).
Figure 6 Jitter Definition
7. Once complete, the flag character is sent.
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.1.4.1.1 Dual Rail Configuration (bipolar mode)
There are several kinds of jitter measurement:
Rx3CLK (Input): 44.736 MHz clock with duty cycle between 40 and
Jitter tolerance (GR-499-CORE 7.3.1): minimum jitter at the input of
equipment that results in more than two errored seconds in a
30-second interval.
60 %; clock used to sample (on positive or negative edge: user-
selected edge) Rx signals.
Rx3POS (Input): positive pulse received on the B3ZS-encoded line.
Jitter transfer (GR-499-CORE 7.3.2): ratio of (amplitude of equipment
output jitter) / (applied input jitter).
Rx3NEG (Input): negative pulse received on the B3ZS-encoded
line.
Jitter generation (GR-499-CORE 7.3.3): added jitter by the equipment
or chip. There also exists two categories of jitter:
Tx3CLK (Output): 44.736 MHz clock with duty cycle between 40
and 60%. This clock is used to sample (user-selected edge) all the
Tx signals.
Category I: when the correspondent line does not physically exists.
Category II: when the line physically exists.
Tx3POS (Output): positive pulses that must be sent on B3ZS
encoded line.
Tx3NEG (Output): negative pulses that must be sent on B3ZS
encoded line.
Amplitude
peak-to-peak
(UI)
1.1.4.1.2 Single Rail Configuration (unipolar
mode)
Slope = -20dB / decade
A 0
Rx3CLK (Input): 44.736 MHz clock with duty cycle between 40 and
60%. This clock is used to sample (user-selected edge) all the Rx
signals.
A 1
Shorter the interval measurement,
the higher the “real time jitter”
A 2
Rx3D (Input): logical incoming data stream received on
B3ZS-encoded line.
frequency
RxLCV (Input): Line code violation detected on B3ZS-encoded line.
F 0
F 1
F 2
F 3
jitter
F 4
6143 drw54
Tx3CLK (Output): 44.736MHz clock with duty cycle between 40 and
wander
60%. This clock is used to sample (user-selected edge) all the Tx
signals.
Figure 7 Maximum Jitter Tolerance on DSn Interface Inputs
Tx3D (Output): logical data that must be encoded and sent by the
DS3 LIU.
TxMFP (Output): M-frame pulse synchronization signal that must be high
during one bit time (the first of the M-frame (X1).
TABLE 11 —MAX JITTER TOLERANCE ON DS IF CAT II
Data Rate (Mbit/s
UI (ns)
Jitter Amplitude
A0 (ms)* A1 (UI)
Filter Frequencies
f2 (HZ)
A2 (UI)
f0 (HZ)
f1 (HZ)
f3 (HZ)
6.43
f5 (HZ)
40
1.544
648
192.9
78.9
669
2.63
20
18
10
0.3
1.2 x 10-5
10
22.3
300
1.1.4 DS3 Framer ⇔ to LIU interface
1.1.4.1 If DS3 Framer ⇔ DS3 LIU
The interface between a DS3 LIU and a DS3 Framer depends on which
device is performing the line coding / decoding function:
If the line encoder / decoder is in the LIU: signals follow single rail
configuration.
If the line encoder / decoder is in the framer: signals follow dual rail
configuration.
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.2 M23 MULTIPLEXER
To multiplex 7 DS2 signals into a formatted DS3 signal (respectively,
to terminate a framed DS3 and to generate 7 independent DS2 signals).
The M23 function is not activated when the M13 is used in an unchan-
nelized mode. When the M23 function is used, the DS3 formatted data
stream (but not framed) is made by taken one bit from each DS2 data
streams in a round robin fashion.
External OH
FIFO
FIFO
DS2
DS2
OH Stuffing
B3ZS
Encoder
1:7
TDAT
DS3 Framer
M23 / C-bit Mode
DS2
DS2
B3ZS
Decoder
RDAT
DS3 Framer
1:7
External
OH
Status
6143 drw 31a
Figure 8 M23 Mulitplexer Block
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3.3 VOLT M13 MULTIPLEXER
Maximum data rat: 6.3157Mbit/s (more than 6.312 M/bits ± 20 ppm)
1.2.1 Stuffing
1.2.1.1 Description
The seven DS2 are asynchronous relative to each other and there-
fore may be operating at different rate. Bit Stuffing adjusts the different
incoming rates. The stuff opportunity bit position exits in the last block of
each DS3 M-subframe to adjust the transmission rate of each DS2
stream independently (just one bit stuffing opportunity per DS2 and per
DS3 M-subframe). The signal data rate limits are:
Minimum data rate: 6.3063Mbit/s (less than 6.312 M/bits ± 20 ppm)
Stuffing indication bits are the C overhead bits, 3 C bits for each
DS2 (Ci1, Ci2, and Ci3 for DS2-i)
If 2 or 3 C-bits are “1”s, the bit in the correspondent stuffing position is a
stuff bit (either 0 or 1): if zero or one C-bit equals, “1”, the bit in the stuffing
position is a data.
Stuff
Bit 3
Info Info Info Info Info Info Info
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Info
Bit 84
M1 Sub-Frame
M2 Sub-Frame
M3 Sub-Frame
M4 Sub-Frame
M5 Sub-Frame
M6 Sub-Frame
M7 Sub-Frame
F4
F4
F4
F4
F4
F4
F4
• • •
Stuff
Bit 2
Info
Bit 1
Info Info Info Info Info Info
Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Info
Bit 84
• • •
Stuff
Bit 3
Info Info
Bit 1 Bit 2
Info Info Info Info Info
Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Info
Bit 84
• • •
Stuff
Bit 4
Info Info Info
Bit 1 Bit 2 Bit 3
Info Info Info Info
Bit 5 Bit 6 Bit 7 Bit 8
Info
Bit 84
• • •
Stuff
Bit 5
Info Info Info Info
Bit 1 Bit 2 Bit 3 Bit 4
Info Info Info
Bit 6 Bit 7 Bit 8
Info
Bit 84
• • •
Info Info Info Info Info Stuff Info Info
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Info
Bit 84
• • •
Stuff
Bit 7
Info Info Info Info Info Info
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
Info
Bit 8
Info
Bit 84
• • •
6143 drw19a
Figure 9 DS3 Stuff Block
1.2.1.2 Stuffing strategies
A particular case is the nominal stuff (DS2 signal frequency equal to
6.312 Mbit/s). To multiplex such a DS2 in one DS3 signal, the host must
program the stuffing speed at a special value that corresponds to a
39.06 % stuffed M-frames (for the particular DS2). As the DS2 level is
most often a transition between DS1 and DS3 signals, it is possible to
use always the M23 mode with a fixed stuff: zero stuff, full stuff or
nominal stuff.
1.2.1.2.1 On receive line adaptation
The number of real stuffing bits inserted in transmission is equal to
the number of real stuffing observed in reception. It is called loop-timing
mode.
1.2.1.2.2 M23 Mechanism
As each DS2 signals can be considered asynchronous, the host must
be able to give each DS2s the stuffing speed for transmission. The range
of each DS2 data rates is:
1.2.1.2.3 C-bit parity Mechanism
In this mode, the decision is a full stuff: each stuffing bit opportunity
(for all the DS2) in all DS3 M-Frames contains a stuff except when the
DS3 signal is unchannelized. In this case, it is possible to have a C-bit
parity mode with a null stuff strategy. C-bits are not used for stuffing indi-
cation (always full or zero stuff): they can be used for others purposes
presented in DS3 framer chapter.
If zero stuff: 6.31567 MHz (6.312 MHz ± 581 ppm).
If full stuff: 6.306272 MHz (6.312 MHz ± 907 ppm).
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.3 DS2 FRAMER
The nominal DS2 interface rate is 6.312 Mbit/s ± 33 ppm (± 208
bit/s). Then DS2 framer function is not activated when unchannelized
DS3 is initalized. DS2 signal is a combination of four DS1 signals. A
DS2 M-frame is composed of four DS2 M-subframes. Moreover, each
M-subframe contains six blocks of 48 payload bits (bit-interleaved from
the four DS1 streams; made by M12 function) plus 1 overhead bit (the
four subframes do not represent each separate DS1 signals). The DS2
frame contains 1176 bits (1152 payload bits ± 24 overhead bits) and the
period is 186.31ms.
The DS2 Framer can also be used to frame G.747 bit streams. In
this case the nominal DS2 rate is 6.312 Mb/s multiplexed from three
tributaries of 2.048 Mbit/s.
FIFO
FIFO
TX1
TX4
OH
Stuffing
DS2
1:4
DS2 Framer
G.747 or
DS2 Mode
RX1
DS2
DS2 Framer
1:4
RX4
OH
Stuffing
6143 drw 32a
Figure 10 DS2 Framer Block
294 Bits
M1
M2
M2
X
48-Bits
48-Bits
48-Bits
48-Bits
C1
48-Bits
F1
F1
F1
F1
48-Bits
48-Bits
48-Bits
48-Bits
C2
C2
C2
C2
48-Bits
48-Bits
48-Bits
48-Bits
C3
C3
C3
C3
48-Bits
48-Bits
48-Bits
48-Bits
F2
F2
F2
F2
48-Bits
M Sub-Frame
C1
C1
C1
48-Bits
48-Bits
48-Bits
48-Bits
48-Bits
48-Bits
M Frame
Stuff Block
6143 drw20
Figure 11 DS2 Frame
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.3.1 Reframing
1.3.2 Alarms and errors
1.3.1.1 Procedure
1.3.2.1 OOF
The search of frame alignment must be activated in three cases:
Out Of Frame is declared when n out of m consecutive framing bits
are in error (n = 2 and m = 4 or 5). Optionally, the OOF detection can
take into accounts one or more M-bits in error in 3 or 4 consecutive
M-frames. If configured, during DS2 OOF, an all-ones AIS signal is sent
downstream to all concerned DS1s. Otherwise the payload extracted
with the previous frame alignment is transmitted downstream because it
is an off-line framer. OOF defect is terminated when the signal does not
contain any more framing bits (F-bits and M-bits) error in several
consecutive frames (1 M-frame or more). Defect detection / termination
must be done in less than 10.5 ms (1.5 x MART).
After a reset.
When the microprocessor forced the reframing process.
After an internal out of frame (OOF) declaration (but reframing
asked by microprocessor). When a DS2 reframing is in process, All-
ones AIS signal is sent downstream for the duration of the
reframing.
1.3.1.2 Max Time
The standard indicates a maximum average framing time of 7ms to
resynchronize the incoming data flow (time necessary to check every
bits of a structure before declaring frame synchronization). This time is
significant only if neither mimic pattern (data payload that ìsimulateî a
frame alignment pattern) nor other trouble (like errors) is present inside
the incoming data flow.
1.3.2.2 LOF
LOF failure is declared if OOF defect is present for 2.5 ± 0.5 seconds
except when a DS2 AIS defect is present or DS2 AIS failure has been
declared. LOF is cleared if no error has been detected in 10 ± 0.5
seconds.
G.747
Nominal DS2 rate 6312Kbit/s multiplexing three tributaries of 2048 kbit/s
Nominal DS3 rate 44.736Mb/s multiplexting seven tributaries of 6,312kbits/sec
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9
Bit 167
Set 1
Set 2
1
1
1
0
1
0
0
0
0
0
AIS PAR REV
Set 3
Set 4
C11 C21 C31
C12 C22 C32
Stuff Stuff Stuff
C13 C23 C33
Set 5
1
2
3
6143 drw21
Parity = 1 Odd
Parity = 0 Even
REV
Reserved, should be set to 1
Cji (j = 1,2,3 i = 1,2,3) indicates the ith justification control bit of the jth tributary
Stuff (j) : Stuff bit for the jth tributary
Positive Justification = 111 (Majority decision)
No Justification
= 000 (Majority decision)
Figure 12 G.747 Frame Format
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.3.2.3 AIS
Payload transmission taking with the last correct frame alignment
(off-line framer).
AIS Defect is declared when at least one of the three following condi-
tions (it should be detected in less than 10.5 ms = 1.5 x MART.) is true:
Transmission of AIS (unframed all-ones signal).
Incoming signal with more than 99.9% of ones density (unframed
1.3.2.4 RAI
all-ones signal = AIS from upper level).
The RAI signal (last M-bit Mx) is transmitted upon declaration of LOF
or AIS failure for the duration of the failure (downstream failure). RAI is
declared when this bit presents for an interval of 0.5 to 1.5 seconds with
no more than 10-3 “1”s (active state is zero). Similarly, the inactive state
of RAI signal must be sampled between 0.5 and 1.5 seconds with no
more than 10-3 “0”s.
(Incoming signal with unframed condition (DS2 LOS or OOF).
Host command.
The insertion of AIS (same for the AIS removal) in the downstream
signal has to be made in less than 0.7 ms (0.1 x MART) AIS failure is
declared if an AIS defect is present for 2.5 ± 0.5 seconds and is cleared
if AIS a defect is absent for 10 ± 0.5 seconds. The activation of an AIS
failure must not exceed 0.7 ms and a host can configure one of the two
downstream transmission strategies:
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
integrator counter. AIS is defined as the occurrence of less than 9 zeros
while the framer is OOF during that G.747-frame. RED alarm is defined
as the detection of a RED defect, or OOF in an M-frame. For each
interval, a G.747 frame, if the framer detects a Red defect or AIS event,
the integrator counter is incremented. Accordingly, if a valid G.747 frame
is received then integrator counter is decremented. As a result the DS2
Framer can detect RED alarm and AIS in 6.9ms.
1.4 G.747 Applications
1.4.1 Reframing
1.4.1.1 Procedure
The search of frame alignment must be activated in three cases:
After a reset.
1.4.2.3 RAI
When the microprocessor forced the reframing process.
The DS2 framer also extracts the DS2 X-bit and G.747 Remote
Alarm Indication bit, RAI, to indicate a Far End Receive Failure, FERF.
The DS2 framer uses an internal status FIFO to insure that for an OOF
condition, nearly 100% of the time for DS2 applications and 99.9% of the
time for G.747 applications, that the DS2 framer will freeze in a valid
state. If two successive X-bits or RAI bits are the same, then a FERF
status is indicated and entered into the internal status FIFO. Each
M-frame or G.747 frame the status FIFO will be updated and shifted.
After a total of six M-frames or G.747 frames, the error condition will
reach the sixth (last) position of the FIFO. When the error condition
reaches the last position in the FIFO, the DS2 Status Register will be
updated to indicate to the controller that a FERF has occurred. The error
indication/value will be held in that sixth(last) position while the fifth
through second positions will freeze the FERF state of the four M-frames
following the FERF condition. The first position of the status FIFO will
contain the present FERF state and will be continually updated with the
present FERF status. Once correct frame alignment has been reestab-
lished and the OOF condition is gone, then the first FIFO status location
will have a valid indication. At this point the FIFO will continue to operate
normally, by shifting the FERF status through the FIFO.
After an internal out of frame (OOF) declaration (but reframing
asked by microprocessor). When a DS2 reframing is in process, All-
ones AIS signal is sent downstream for the duration of the
reframing.
1.4.1.2 Max Time
For G.747 applications the DS2 framer has a maximum reframe rime
of less than 1ms. In order for the framer to declare framing however, the
candidate frame alignment signal must be present for 3 consecutive
frames in accordance with CCITT Rec. G.747 Section 4. Once in frame
the DS2 framer will provide frame boundary indications as well as
overhead bit positions.
1.4.2 Alarms and errors
1.4.2.1 OOF
For alarm indications the DS2 framer is designed to indicate OOF
conditions when 4 consecutive frame alignment signals are incorrect in
accordance with CCITT Rec. G.747 Section 4. Much like the DS3
framer, the DS2 framer is an "off-line" framer and will continue to
indicate errors when OOF based on the previous frame alignment.
1.4.2.2 AIS
In G.747 applications the DS2 framer also uses an integration
algorithm with a 1:1 slope to detect RED alarm and AIS. Instead of using
DS2 frames however the DS2 framer uses G.747 frames with the
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.5.2 Stuffing
1.5.2.1 Mechanism
1.5 M12
To multiplex 4 DS1 signals into a formatted DS2 signal (respectively,
to terminate a framed DS2 and to generate 4 independent DS1 signals).
The M12 can also multiplex/demultiplex three E1 (2.048 Mbit/s) streams
into a G.747 formatted 6.312 Mbit/s serial stream. The M12 function is
not activated when unchannelized DS3 initialized.
The four DS1 are asynchronous relative to each other and may be
operating at different rates. Bit Stuffing is used to adjust the different
incoming rates. Stuff opportunity bit position exists in the last block of
each DS2 M-subframe to adjust the transmission rate of each DS1
streams independently (just one bit stuffing opportunity per DS1 and per
DS2 M-subframe). Stuffing indicator bits are the C overhead bits, 3
C–bits for each DS1 (Ci1, Ci2 and Ci3 for DS1-i). If in these three bits
there are 2 or 3 “1”s, the bit in the stuffing position is stuff (value not
specified: either 0 or 1); if there are 0 or 1 “1”, the bit in the stuffing
position is a data.
1.5.1 Actions on the four multiplexed
DS1 bit-streams
The DS2 data stream is built by taking one bit from each of the four
DS1 data streams in a round robin fashion. However, the second and
fourth DS1 signals must have their all bits inverted.
FIFO
FIFO
TX1
TX4
OH
Stuffing
DS2
1:4
DS2 Framer
G.747 or
DS2 Mode
RX1
DS2
DS2 Framer
1:4
RX4
OH
Stuffing
6143 drw 32a
Figure 13 M12 Block
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
1.5.2.2 Stuffing strategies
1.5.2.2.2.1 DS1 nominal stuffing value if M23
mode used between DS2 and DS3 level
1.5.2.2.1 On receive line adaptation
The per-DS1 in a DS2 signal (6.312 Mbit/s) data rate limits are:
The number of real stuffing bits inserted in transmission is equal to
the number of real stuffing observed in reception. This mode is also
called per–T1 loop timing. In this mode, the system must free run under
trouble condition at 1.544 Mbit/s ± 200 bit/s (1.544 Mbit/s ± 130 ppm).
Such a mode seems to be used only if remote loopback (line or payload)
is activated.
Maximum data rate: 1.5458 Mbit/s (more than 1.544 Mbit/s ± 20
ppm).
Minimum data rate: 1.5404 Mbit/s (less than 1.544 Mbit/s-20 ppm).
The nominal stuffing ratio is 33.46 % of stuffed frames (if DS2 at
nominal data rate).
1.5.2.2.2.2 DS1 nominal stuffing value if C-bit
parity mode used between DS2 and DS3 level
1.5.2.2.2 Adaptive frequency
As each DS1 signal comes from its own source (asynchronous), the
host processor must be able to give for each DS1 the stuffing speed for
transmission in order to adapt the DS1 data rates independently. An
external reference has to be used to synchronize the DS1 signals (this
reference is also called Building Integrated Timing Source, BITS). Such
a reference can come from one DS1 received data stream (line-timing
mode) or from an external reference such as GPS for example (external
reference mode). In reception, each DS1stuffing ratio must be esti-
mated. However, the real time stuffing value depends on the mode used
to multiplex DS2s into a DS3 signal:
The per-DS1 in a DS2 signal (6.306 Mbit/s) data rate limits are:
Maximum data rate: 1.5444 Mbit/s (more than 1.544 Mbit/s ± 20
ppm).
Minimum data rate: 1.5390Mbit/s(less than 1.544 Mbit/s-20 ppm).
The nominal stuffing ratio is 7.41% of stuffed frames.
1.5.3 OH Insertion
During the muxing process the M12 MUX also inserts X, F, M and C
bits.
If M23 mode, every DS1 signal works at its own speed. (Near the
nominal stuffing value if M23 stuffing programmed near the nominal
value for example).
1.5.4 Per DS1 Payload Loopback
The M12 multiplex should loopback the DS1 signal if it detects that
Ci3 bit is the inverse of Ci1 and Ci2 bits (i defines the concerned DS1). It
is necessary to repeat this information at least 10 times.
If C-bit parity mode, DS1 stuffing value must be under the nominal
value (less stuff) due to the full stuff processing when DS2 signals
are multiplexed into the DS3 formatted signal.
More information on the Loopback modes are provided in the
Loopback section of the data sheet.
Stuff
Bit 1
Info Info Info Info
Bit 2 Bit 3 Bit 4 Bit 5
Info
Bit 48
M1 Sub-Frame
M2 Sub-Frame
M3 Sub-Frame
F2
F2
F2
F2
• • •
Stuff
Bit 2
Info
Bit 1
Info Info Info
Bit 3 Bit 4 Bit 5
Info
Bit 48
• • •
Info Info Stuff Info Info
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
Info
Bit 48
• • •
Info Info Info Stuff Info
Bit 1 Bit 2 Bit 3
Info
Bit 48
M4 Sub-Frame
• • •
Bit 4
Bit 5
6143 drw20a
Figure 14 DS2 Stuff Block
FUNCTIONAL DESCRIPTION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
The XFDL can be run in three different modes: polled, interrupt driven,
and DMA-controlled. In the polled mode, the TDLINT and TDLUDR out-
put of the XFDL are unused and the microprocessor must periodically poll
(read) the XFDL Status Register to determine when to write the next byte
to the Transmit Data FIFO. In the interrupt driven mode, the micropro-
cessor will use the TDLINT pin as an interrupt pin to determine when the
Transmit Data FIFO is ready for the next data byte. In the DMA controlled
mode the TDLINT output acts as a DMA request to the DMA controller
while DMA end signal feeds the TDLEOMI of the M13. In an under run
condition the TDLUDR drives an interrupt on the controlling microproces-
sor.
Internal Data Link Transmitter:
The Transmitter Data Link Configuration Register and the Transmit
Data Link Control Register are the two main registers used for control-
ling the Transmit Data Link function in the M13. After reser, XFDL is
disabled because the EN bit in the TSB Configuration Register will be 0.
The INTE bit, also in the XFDL TSB Configuration Register, should be
set so that the TDLINT output is masked.
When a frame is ready to be transmitted, the XFDL TSB should be
configured accordingly. If the CCITT-CRC frame check sequence is de-
sired this should be enabled. Then the INTE bit should be enabled (if in
the interrupt driver mode), and then finally the EN bit is set to 1 enable
the overall operation of the XFDL.
TDL TDR TDL
INT UDR EOM
Data
Reg 22
XFDL
Control
Parallel-to-serial
ZeroStuff
Reg 20
Reg 21
Parallel-to-serial
Parallel-to-serial
Parallel-to-serial
Parallel-to-serial
PMDL_Out
MUX
6143 drw37
Figure 15. XFDL
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Polled Mode:
In the polled mode the controlling microprocessor will periodically initiate a service routine to complete the following.
1) Read the XFDL Status Reg.
2) If UDR = 1 clear the Status register by setting UDR = 0, de-asserting TDLEOMI input pin and clearing EOM. Restart the current frame.
3) If INTR = 1 then
a) Write next data byte to XFDL TSB Data Reg.
b) Set EOM = 1 and INTE = 0 or assert TDLEOMI input pin.
4) Repeat steps 1 an 2 to confirm no underrun occurred during step 3.
82V8313
0x21
0x22
XFDL TSB INT Status
XFDL TSB TX Data
TDLEOMI
TDLINT
X
X
TDLUDR
6143 drw42
Figure 16. XFDL Polled Mode
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3.3 VOLT M13 MULTIPLEXER
Interrupt Driven Mode:
In the interrupt driven mode the microprocessor will service the M13 when the XFDL is ready to accept another byte or when an underrun condition
occurs. The ISR will be the same as described above.
XFDL TSB TX Data Reg
ready for new byte
82V8313
0x25
0x26
XFDL TSB INT Status
XFDL TSB TX Data
TDLINT
X
X
6143 drw42a
New Byte Written
to XFDL TSB TX
Data Register
TDLUDR
TDLEOMI
Figure 17. XFDL Interrupt Mode
INT = 0
Write
Read
XFDL TSB
INT Status
UDR Status
Data to
XFDL TSB
Data Reg
or
INT = 1
Set EOMI in
XFDL Config
Reg. if INT = 0
or
UDR = 1
Assert
TDLEOMI
pin & INTE = 0
Clear Status Reg
UDR = 0
Deassert TDLEOMI
Clear EOM = 0
6143 drw42b
Figure 18. XFDL Interrupt Service Routine
DATA LINK
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3.3 VOLT M13 MULTIPLEXER
DMA Mode:
When a DMA controller is used with the XFDL, the TDLINT will initiate a DMA request and consequently the DMA controller will send a byte to the
M13. For each assertion of the TDLINT the DMA controller should send a byte. Once the last byte is sent from the DMA controller to the M13, to
finish the request, the DMA controller should assert the TDLEOMI When the DMA controller sets TDLEOMI high, the EOM bit in the XFDL Configura-
tion register will be set to complete the transaction. If an underrun condition occurs the TDLUDR will interrupt the microprocessor and will stop DMA
controller, clear the condition, reset any necessary data pointers, and restart the DMA to resend the data frame.
Microprocessor
82V8313
TDLUDR
INT
DMA
Reg
End
TDLINT
TDLEOMI
6143 drw41
Figure 19. XFDL DMA Mode
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3.3 VOLT M13 MULTIPLEXER
frame. Again the microprocessor will enter the XFDL ISR and load the
data byte in to the FIFO. Again the TDLINT will de-assert when it begins
to transmit that data byte. This process continues until the last byte of the
frame. Once the last data byte begins to transmit, the TDLINT will be as-
serted, as normal. Since all of the data has been written to the FIFO the
ISR should set the EOM bit (or assert the TDLEMI pin) to end the frame.
Also, the INTE bit should be set to 0 so that the TDLINT interrupt is dis-
abled and the CRC bytes and the closing flag are transmitted. When new
data for the next frame is ready, the TDLINT can be re-enabled by setting
the INTE bit to 1, and thus beginning the sequence over again.
XFDL Normal Data Sequence:
This example shows a normal XFDL interrupt driven sequence with the
CRC enabled. In order to begin the sequence the microprocessor must
first set the INTE bit in the XFDL Configuration/Control Register to enable
the TDLINT interrupt. Once the interrupt is enabled the M13 will assert
the TDLINT to interrupt the microprocessor. The interrupt routine de-
scribed above will cause the microprocessor to write the first data byte of
the frame to the transmit FIFO. Once the byte is written to the FIFO, the
TDLINT will de-assert. When the XFDL begins to transmit the first byte,
TDLINT will assert again to signal that it is ready for the next byte in the
Serial
RFDL Data
Flag
Byte 1
Byte 2
Byte n
C1
C2
Flag
Byte 1
TDLINT
D7-0
6143 drw48
Figure 20. XFDL Normal Data Sequence
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3.3 VOLT M13 MULTIPLEXER
begins to transmit the TDLINT is asserted and the interrupt routine
should be started. For some reason, the routine was not able to write to
the transmit FIFO within five rising clock edges, so the Transmit Data
Link Underrun pin, TDLUDR, is asserted. Once the TDLUDR is
asserted, an abort followed by a flag is automatically sent out on the data
link. The XFDL is stopped, the UDR bit is set, and the M13 must be
serviced by the microprocessor. The UDR bit should be cleared and the
INTE bit should be set to 0. Once this is done, the frame can be
restarted again by setting the INTE bit to 1.
XFDL Underrun Sequence:
This example is also an interrupt driven example, but shows the
XFDL inputs and outputs during and underrun error. Similar to the last
example, the microprocessor begins by setting the INTE bit in the
Configuration/Control Register to 1 thus enabling TDLINT interrupts.
The TDLINT is asserted and the microprocessor enters the interrupt
routine to write the first data byte to the transmit FIFO. Once the byte is
written to the FIFO, the TDLINT is de-asserted. As with the previous
example, once the XFDL begins to transmit the data, the TDLINT will be
asserted to start the next ISR transmit data write sequence. When D3
Serial
XFDL Data
Flag
Byte 1
Byte 2
Byte 3
Abort
Flag
Byte 1
Byte 2
Byte 3
TDLINT
TDLUDR
D7-0
6143 drw 49
Figure 21. XFDL Underrun Sequence
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
causing an underrun. The time from rising edge to rising edge of
TDLINT is a result of the variation in time to transmit the data link byte
over the 3 C-bits of the 5th M-subframe over multiple M-frames, and for
the M13 to latch in the next byte. As shown above, the third byte write to
the XFDL FIFO is missed and thus the TDLUDR goes high when it was
supposed to transmit that third byte.
TDLINT Timing Normal Data
Transmission:
This figure shows the timing requirements for the microprocessor to
adequately service the transmit data link FIFO. Each byte of the packet
must be written within 110µSec of the rising edge of the TDLINT without
Min 216µs
Max 311µs
Min 216µs
Max 311µs
Min 216µs
Max 311µs
<110µs Sec
<110µs Sec
TDLINT
Byte Write to
XFDL FIFO
Missed Write
WRB
(Byte Write
to XFDL FIFO)
TDLUDR
6143 drw52
Figure 22. TDLINT Timing Normal Data TX
DATA LINK
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3.3 VOLT M13 MULTIPLEXER
In the above diagram, TDLEMOI is shown going high synchro-
nously with the write strobe but can be asserted any time up to
210µSec after the rising edge of TDLINT. TDLEMOI is de-asserted
before the end of the second CRC byte (or before the flag transmis-
sion). In this example TDLINT is still active and remains high while
waiting for the first byte of the next frame to be written to the XFDL
Transmit FIFO. In this example, it is important to note that the TDLUDR
is not asserted. In this situations, no underrun can occur since it is the
first byte of the frame. However, once the first byte is written, the XFDL
FIFO must be serviced regularly to prevent an underrun condition. As
noted previously, TDLEOMI must be glitch free. If TDLEMOI is not
used, it can be tied to ground or held low. In this case, the EOM bit can
be used and the same restrictions that apply to the TDLEOMI apply to
the EOM bit. It is strongly recommended that the interrupt routine
described in this data sheet be used.
TDLEOMI Timing:
The Transmit Data Link End Of Message Indicator, TDLEMOI, is used
to indicate to the XFDL block that the last byte of the frame has been writ-
ten to the XFDL Transmit Data Register. When TDLEOMI has been as-
serted, the XFDL will insert the FCS, if enabled, and flags (“01111110”)
after the last byte has been transmitted. To aid designers, the M13 can
accept a wide range of timing for the TDLEOMI. The above diagram will
help illustrate this broad range. At the earliest, the TDLEOMI can be as-
serted synchronously with the falling edge of the write strobe that is used
to write the last data byte to the XFDL Transmit FIFO. At the latest, TD-
LEOMI must be asserted before the next rising edge of TDLINT, when
the XFDL would expect the next data byte to be written to the XFDL
Transmit FIFO (210µSec). For de-assertion a similar logic applies and
the earliest TDLEOMI can be de-asserted would be just after the rising
edge of the TDLINT that registered the TDLEOMI. At the latest, TDLE-
OMI must be de-asserted before the write of the first byte of the nest
frame. If TDLEOMI is still high when TDLINT goes high, that byte will be
considered that last byte and thus the CRC bytes and flag bytes will au-
tomatically be transmitted on the data link
<210µs
Min 216µs
Max 311µs
Last Byte & CRC
Flag “01111110"
850µs
<110µs
TDLINT
WRB
Byte Write
& XFDL FIFO
First Byte
Of Next Frame
TDLEOMI
6143 drw50
Latest
Deassertion
Figure 23. TDLEOMI Timing EOMI After CRC
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
that after the RFDL is enabled (EN = 1 or TR = 1) the RFDL will generate
an interrupt to indicate the status of the link. As a result, the first data
byte read should be discarded. The M13 is designed as a passive
RFDL, any link state in the form of BOC, IDL, active flags, or other indi-
cations should be handled by the controlling microprocessor.
Internal Data Link Receiver:
Like the data link transmitter, the Data Link Receiver should be
disabled at start up by setting the EN bit in the RFDL Configuration
Register. Before initiating the RFDL, the FIFO depth for generating an
interrupt should be set by writing to the RFDL Interrupt Control/Status
register.
Much like the XFDL, the RFDL can be run in a polled, interrupt
driven, or DMA controlled mode. In the polled mode the RDLINT and
RDLEOM outputs are not used and the microprocessor must periodically
read (poll) the Status register to determine when to read the data. In the
Interrupt driven mode the M13 will generate an interrupt via RDLINT pin
to indicate to the microprocessor that data is ready to be read. In the
DMA controlled mode the RDLINT and RDLEOM are used as a hard-
ware handshake to initiate, indicate and terminate the DMA.
By setting the EN bit in the Configuration Register to 1, the RFDL will
be enabled and assumes the link will be idle (all ones). Immediately
after enabling the RFDL however, the RDFL will begin searching for
flags. When the first flag is found, an interrupt will be generated and the
data byte found before the flag will be written to the FIFO. When an
interrupt is generated the RFDL control block guarantees that the FLG
and EOM bits will also be written to the status register reflect the current
state. After the interrupt is generated the data should be read out and
EOM should be logic 1 and the FLG bit logic 1. It is important to note
Zero Destuff
FIFO
Serial to Parallel
Reg 24
RFDL
Control
Reg 25
Reg 26
Data Out
6143 drw38
RDL
INT
RDL
EOM
Figure 24. RFDL
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
6) If FLG = 1 and the link was inactive, then set the link to active,
discard the byte and wait for the next period/interrupt.
Polled Mode:
In the polled mode the controlling microprocessor will periodically
initiate a service routine and complete the following:
7) Save the byte.
1) Read the RFDL Data Register
2) Read the RFDL Status Register
8) If EOMR = 1, then check the CRC, NVB and process the frame
9) If FE = 0, then go to step 1, else wait for next period/interrupt.
3) If the FIFO has underrun (0x00) then discard byte and wait for the
next period/interrupt.
Steps 1 and 2 may be reserved to avoid reading the Data Register
unneccessarily.
4) If the FIFO has overflowed (OVR = 1) then discard the last frame
and wait for the next period/interrupt.
5) If FLG = 0 (i.e. abort) and the link was active discard the byte and
wait for the next period/interrupt.
82V8313
0x25
0x26
RFDL TSB INT. Cnt/Status
RFDL TSB Status
RDLINT
X
X
0x27
RFDL TSB Receive Data
RDLEOM
6143 drw 39a
Figure 25. RFDL Polled Mode
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
described above. The above flow (Steps 5 and 6) assumes that the link
state is stored as a local variable. This is done to determine if the link
state inactive, receiving all ones or BOC which contains all ones
sequences, or active and thus receiving data and flags.
Interrupt Driven Mode:
In the interrupt driven mode the microprocessor will service the M13
when the RFDL indicates when a data byte is ready or when an error
condition occurs. The ISR will be the same as with the polled condition
82V8313
0x25
0x26
RFDL TSB INT. Cut/Status
RDLINT
RFDL TSB Status
0x27
RFDL TSB Receive Data
RDLEOM
6143 drw 39b
Figure 26. RFDL Interrupt Driven Mode
Wait for
Interrupt
Read RFDL
Data Reg
= 0x00
Read Status
Reg
Discard
Data
! = 0x00
Discard
last
frame
= 1
Check
OVR
= 1
= 0
Set link to
Active
Set link to
Inactive
Check
FLG
Save Byte
= 1
= 0
Check CRC, NVB
Process the frame
Check EOMR
= 0
= 1
6143 drw40
Check FE
Figure 27. RFDL Interrupt Service Routine
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
When the DMA controller reads the last byte (EOM or abort) or an
overrun condition occurs the RDLEOM output goes high the DMA
controller will be inhibited from reading more bytes and the processor is
interrupted. When the processor takes over, the DMA can be halted and
readied for the subsequent frame, and the frame processing initiated.
DMA Mode:
The RFDL can also be used with a DMA controller. In this case the
RDLEOM of the M13 is connected to the interrupt pin of the micro-
controller. The RDLEOM is also routed to a gate, with the RDLINT,
which will inhibit a DMA request if the RDLEOM output is high. In this
way, if the RDLEOM is low, the RDLINT will control DMA requests.
82V8313
Microprocessor
INT
RDLEOM
DMA
Request
RDLINT
6143 drw 39
Figure 28. RFDL DMA Mode
DATA LINK
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
register those into the RFDL Data Register. In this example B1 will
contain the remainder of the farme data and the first part of the first byte
of CRC data. B2 will contain the second part of the first byte of the CRC
data plus the first part of the second byte of the CRC data. And finally,
B3 will contain only the second part of the second byte of the CRC data.
When the status register is read for B3, the EOM bit in the RFDL Status
Register will also be set to indicate the end of the current frame (End of
Message --EOM). The RFDL block parses data on byte boundaries until
the RFDL receives the end flag. The RFDL block will indicate the size of
the remainder by setting the NVB (Number of Vaild Bits) in the RFDL
TSB Status register (0x26). The NVB information can be used by
controlling microprocessor to properly parse, check, and handle the
data.
RFDL Normal Data and Abort
Sequence:
The above diagram shows the relationship between the incoming
and extracted data link data and the RDLINT, RDLEOM, and micropro-
cessor bus. To simplify the examples each microprocessor access is a
composition of multiple accesses following the recommended handling
sequence, where each incoming data byte of the farme is “handled”
(read) in turn. As can be seen there is a short delay from the incoming
data to RDLINT going high. It can also be seen that RDLINT will both be
de-asserted until the microprocessor reads the data byte from the RFDL
Data Register. The assert/de-assert sequence is followed through the
entire farme until Byte (n-2) when multiple bytes exist in the buffer. In
this case it can be seen that the RDLINT is not de-asserted. At the end
of an interrupt sequence the controlling microprocessor should realize
that the interrupt has not been completely cleared and thus re-enter the
ISR. At Byte (n-1) the interrupt is cleared and the RDLINT is de-
asserted. In a data link frame, it is not necessary to have an integral
number bytes. In the above example, this is one of those cases. The
“R” represents the non-integral bits that remain at the end of the frame.
The internal RFDL block will take in the remainder and the CRC and also
In the above example, after B3 is read a new frame is started.
Shortly after it starts, it is aborted. The microprocessor first reads Byte 1
and then reads the B1 byte. When B1 is read the Status Register will
indicate FLG bit and EOM bit meaning all bytes up to the abort should be
read.
B1
B3
B2
B1'
R
Serial
Flag
Byte 1
Byte 2
Byte 3
Byte n-1
Byte n
R
C1
C2
Flag
Byte 1
Abort
RFDL Data
RDLINT
(1)
Abort
EOM
EOM
RDLEOM
D7-0
6143 drw46
Figure 29. RFDL Normal Data And Abort Sequence
DATA LINK
91
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DATA LINK
92
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
FUNCTIONAL TIMING:
ROHCLK
X1 F1 C11 F0 C12 F0 C13 S1 X2 F1 C21
F0 C22 F0 C23 S2 P1 F1 C31 F0 C32 F0 C33 S3 P2 F1 C41 F0 C42 F0 C43 S4 M1 F1 C51 F0 C52 F0 C53 S5 M2 F1 C61 F0 C62 F0 C63 S1 M3 F1 C71 F0 C72 F0 C73 S7 X1
ROH
ROHFP
6143 drw43
Figure 30. Receive DS3 OH Serial Stream
TOHCLK
(526 KHz)
TOH
X1 F1 C11 F0 C12 F0 C13 S1 X2 F1 C21 F0 C22 F0 C23 S2 P1 F1 C31 F0 C32 F0 C33 S3 P2 F1 C41 F0 C42 F0 C43 S4 M1 F1 C51 F0 C52 F0 C53 S5 M2 F1
C61 F0 C62 F0 C63 S1 M3 F1 C71 F0 C72 F0 C73 S7 X1
TOHFP
TOHEN
6143 drw43a
Figure 31. Transmit DS3 OH Serial Stream
ROHCLK
(526KHz)
RMSFP
(X,P,M)
ROHP
(X,P,M,C,F)
ROHFO
(X1)
X1 F1 C11 F0 C12 F0 C13 S1 X2 F1 C21 F0 C22 F0 C23 S2 P1 F1 C31 F0 C32 F0 C33 S3 P2 F1 C41 F0 C42 F0 C43 S4 M1 F1 C51 F0 C52 F0 C53 S5 M2 F1 C61 F0 C62 F0 C63 S1 M3 F1 C71 F0 C72 F0 C73 S7 X1
ROH
6143 drw44
Figure 32. Functional Receive OH Timing Low Speed
FUNCTIONAL TIMING
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
ROHCLK
RAIS
X1 F1 C11 F0 C12 F0 C13 S1 X2 F1 C21 F0 C22 F0 C23 S2 P1 F1 C31 F0 C32 F0 C33 S3 P2 F1 C41 F0 C42 F0 C43 S4 M1 F1 C51 F0 C52 F0 C53 S5 M2 F1 C61 F0 C62 F0 C63 S1 M3 F1 C71 F0 C72 F0 C73 S7 X1
X1 F1 C11 F0 C12 F0 C13 S1 X2 F1 C21 F0 C22 F0 C23 S2 P1 F1 C31 F0 C32 F0 C33 S3 P2 F1 C41 F0 C42 F0 C43 S4 M1 F1 C51 F0 C52 F0 C53 S5 M2 F1 C61 F0 C62 F0 C63 S1 M3 F1 C71 F0 C72 F0 C73 S7 X1
RLOS
ROOF
(3 out of 16
F-bits)
ROOF
(3 out of 8
F-bits)
RFERF
RDLSIG
RDLCLK
6143 drw44a
Figure 33. Functional Receive Timing PMON
ROCLK
(44.736 MHz)
X-2bit or P-bit or M-bit
C-bit or F-bit
RODAT
Info
Info
Info
Info
Info
Info
Info
X-bit
RMFP
RMSFP
ROHP
6143 drw45
Figure 34. Functional Receive OH Timing High-Speed
FUNCTIONAL TIMING
94
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Loopback Modes:
Loopback Modes
95
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 Diagnostic Loopback
For a DS3 Diagnostic Loopback, the transmitted DS3 stream will be looped back into the DS3 receive path and as a result the incoming DS3 will
be ignored. As a result of the incoming DS3 being ignored, the receive path will use the transmit clock instead of the RPOS./RDAT and RNEG/RLCV.
MX12 #7
F
RCLK
MX12 #6
F
DS3
RPOS/
RDAT
FRMR
MX12 #5
MX12 #4
F
•
•
•
•
•
•
RNEG/
RLCV
F
MX12 #3
MX12 #2
MX12 #1
F
MX23
F
UNI
TCLK
F
TPOS/
TDAT
DS3
R
M
R
TRAN
TNEG/
TMFP
6143 Drw60
Optional
AIS
Insertion
Figure 35. DS3 Diagnostic Loopback
Loopback Modes
96
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS3 Line Loopback
For a DS3 Line Loopback, the received DS3 stream will be looped back into the DS3 transmit path and as a result the internally generated DS3 will
be ignored. Similar to the DS3 Diagnostic Loopback the transmit clock will be substituted with the receive clock.
MX12 #7
F
RCLK
MX12 #6
F
DS3
RPOS/
RDAT
FRMR
MX12 #5
MX12 #4
F
•
•
•
•
•
•
RNEG/
RLCV
F
MX12 #3
MX12 #2
MX12 #1
F
MX23
F
TCLK
F
TPOS/
TDAT
DS3
R
M
R
TRAN
TNEG/
TMFP
6143 Drw61
Figure 36. DS3 Line Loopback
Loopback Modes
97
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*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS2/G.747 Demultiplex Loopback
For a DS2/G.747 Demultiples Loopback individual DS2 or G.747 streams can be looped from the receive DS3 stream and be placed back on the
transmit DS3 stream. As might be expected, the internally generated DS2 or G.747 DS2 will be ignored.
MX12 #7
F
RCLK
MX12 #6
F
DS3
RPOS/
RDAT
FRMR
MX12 #5
MX12 #4
F
•
•
•
•
•
•
MX23
RNEG/
RLCV
F
MX12 #3
MX12 #2
MX12 #1
F
DS2/G.747 Tributary Loopback Path
Optional
DEMUX AIS
Insertion
F
TCLK
F
TPOS/
TDAT
DS3
R
M
R
TRAN
TNEG/
TMFP
6143 Drw62
Figure 37. DS2 / G.747 Demultiplex Loopback
Loopback Modes
98
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DS1/E1 Demultiplex Loopback
For a DS1/EI Demultiplex Loopback individual DS1 or E1 streams can be looped from the received DS3 stream and be placed back on the transmit
DS3 stream. As with the DS2/G.747 Demultiplex loopback the corresponding incoming DS1 or E1 stream will be ignored.
MX12 #7
F
RCLK
MX12 #6
F
DS3
RPOS/
RDAT
FRMR
MX12 #5
MX12 #4
F
•
•
•
•
•
•
MX23
RNEG/
RLCV
F
MX12 #3
MX12 #2
MX12 #1
F
DS1/E1 Tributary Loopback Path
Optional
DEMUX AIS
Insertion
F
TCLK
F
RD1DATn
RD1CLKn
R
M
R
TPOS/
TDAT
DS3
TRAN
TD1DATn
TD1CLKn
TNEG/
TMFP
6143 Drw63
Figure 38. DS1/E1 Demultiplex Loopback6+
Loopback Modes
99
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*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Loopback Modes
100
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*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage
Min.
Max.
Unit
Vcc
VI
-0.5
GND -0.3
-50
+4.0
Vcc +0.3
50
V
V
Voltage on Digital Inputs
Current at Digital Outputs
Storage Temperature
Io
mA
°C
W
Ts
-55
+125
2
PD
Package Power Dissipation
—
(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max. Unit
Vcc
Positive Supply
3.0
2.0
3.3
—
—
3.6
Vcc
0.8
V
V
V
(1)
VIH
Input HIGH Voltage
Input LOW Voltage
VIL
-0.3
Operating Temperature
Industrial
TOP
-40
25
+85
°C
Notes:
1. Inputs/Outputs are 5V tolerant.
2. Voltages are with respect to ground (GND) unless otherwise stated.
DC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Units
Icc(1)
Supply Current
—
-10
-10
—
—
—
185
60
mA
µA
µA
µA
V
(3.4)
IIL
Input Leakage (input pins)
Input Leakage (I/O pins)
High-Impedance Leakage
Output HIGH Voltage
Output LOW Voltage
(3.4)
IBL
60
(3,4)
IOZ
—
—
—
60
(5)
VOH
2.4
—
—
0.4
(6)
VOL
V
Note:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ Vcc
4. Maximum leakage on pins (output or I/O in High-Impedance state) is over an applied voltage (V).
5. IOH = 10 mA
6. IOL = 10 mA
DC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
AC ELECTRICAL CHARACTERISTICS
MICROPROCESSOR INTERFACE TIMING CHARACTERICSTICS
MICROPROCESSOR READ ACCESS
Symbol
Parameter
Address to Valid Read Set-up Time
Min.
Typ.
Max.
Unit
tSAR
tHAR
tSALR
tHALR
tVL
20
20
20
20
20
20
—
—
—
—
—
—
—
—
—
100
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Valid Read Hold Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
tHLR
tPRD
tZRD
tPINTH
Latch to Read Hold
Valid Read to Valid Data Propagation Delay
Valid Read Deserted to Output Tristate
Valid Read Deasserted to INTB Tristate
50
tSAR
A8-0
ALE
Vaild Address
tSALR
tVL
tHAR
tHAL
tHLR
(CSB + RDB)
tPINTH
INTB
D7-0
tZRD
tPRD
Vaild Data
6143 drw04
Figure 39 Microprocessor Read Access Timing
Notes on Microprocessor Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the microprocessor data bus, (D 7-0).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. Microprocessor timing applies to normal mode register accesses only.
5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to
the 1.4 Volt point of the clock.
6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the
1.4 Volt point of the input.
7. In non-multiplexed address/data bus architectures, ALE should be held high, parameters tSALR, tHALR, tVL, tHLR and tSLR are not applicable.
8. Parameters tHAR and tSAR are not applicable of address latching is used.
AC ELECTRICAL CHARACTERISTICS
103
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
MICROPROCESSOR WRITE ACCESS
Symbol
Parameter
Min.
Max. Unit
tSAW
tSDW
tSALW
tHALW
tVL
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
25
20
20
20
20
0
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSLW
tHLW
tHDW
tHAW
tVWR
Latch to Write Set-up
Latch to Write Hold
20
20
20
40
Data to Valid Write Hold Time
Address Valid Write Hold Time
Valid Write Pulse Width
A8-0
ALE
Vaild Address
tSALW
tHLW
tVL
tSLW
tHLW
tVWR
tHAW
(CSB + RDB)
tSDW
tHDW
D7-0
Vaild Data
6143 drw05
Figure 40 Microprocessor Write Access Timing
Notes on Microprocessor Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WDB signals.
2. Microprocessor timing applies to normal mode register accesses only.
3. In non-multiplexed address/data bus architectures, ALE should be held high, parameters tSALW, tHALW, tVL, tHLW and tSLW are not applicable.
4. Parameters tHAW and tSAW are not applicable of address latching is used.
5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to
the 1.4 Volt point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the
1.4 Volt point of the input.
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TIMING CHARACTERISTICS
RECEIVE DS3 INPUT
Symbol
Parameter
Min.
Max.
Unit
RCLK Frequency (nominally 44.736 MHz)
RCLK Duty Cycle
-20
40
4
+20
60
ppm
%
tSRPOS
RPOS/RDAT Set-up Time
RPOS/RDAT Hold Time
—
—
—
—
ns
tHRPOS
tSRNEG
tHRNEG
6
ns
RNEG/RLCV Set-up Time
RNEG/RLCV Hold Time
4
ns
6
ns
RCLK
tSRPOS
tSRNEG
tHRPOS
tHRNEG
RPOS/RDAT
RNEG/RDAT
6143 drw06
Figure 41 Receive DS3 Input Timing
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TRANSMIT DS3 INPUT
Symbol
Parameter
Min.
Max.
Unit
TICLK Frequency (nominally 44.736 MHz)
TICLK Duty Cycle
20
20
20
20
—
—
—
—
ppm
%
tSTIMFP
tHTIMFP
TIMFP Set-up Time
ns
TIMFP Hold Time
ns
TICLK
tSTIMFP
tHTIMFP
TIMFP
6143 drw07
Figure 42 Transmit DS3 Input Timing
TRANSMIT OVERHEAD INPUT
Symbol
Parameter
TOH Set-up Time
Min.
Max.
Unit
tSTOH
20
20
20
20
—
—
—
—
ns
ns
ns
ns
tHTOH
TOH Hold Time
tSTOHEN
tHTOHEN
TOHEN Set-up Time
TOHEN Hold Time
TOHCLK
TOH
tSTOH
tHTOH
tHTOHEN
tSTOHEN
TOHEN
6143 drw08
Figure 43 Transmit Overhead Input Timing
AC ELECTRICAL CHARACTERISTICS
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*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TRANSMIT TRIBUTARY INPUT
Symbol
Parameter
Min.
Max.
Unit
TD1CLKn Frequency (nominally 1.544 MHz, when configured for
DS1 rate operation)
-130
+130
ppm
TD1CLKn Frequency (nominally 2.048 MHz, when configured for
E1 rate operation; not applicable for n = 4, 8, 12, 16, 20, 24, 28)
-50
-33
+50
+33
ppm
ppm
TD1CLKn Frequency (nominally 6.312 MHz, when configured for
DS2 rate operation; only applicable for n = 4, 8, 12, 16, 20, 24, 28)
TD1CLK Duty Cycle (all configurations)
TD2CLK Frequency (nominally 6.312 MHz)
TD2CLK Duty Cycle
33
-33
33
20
20
67
+33
67
%
ppm
%
tSTD1DAT
tHTD1DAT
TD1DAT Set-up Time
—
ns
TD1DAT Hold Time
—
ns
TD1CLK
TD1DAT
tHTD1DAT
tSTD1DAT
6143 drw09
Figure 44 Transmit Tributary Input Timing
TRANSMIT DATA LINK INPUT
Symbol
Parameter
Min.
Max.
Unit
tSTDLSIG
tHTDLSIG
TDLSIG to TDLCLK Set-up Time
TDLSIG to TDLCLK Hold Time
20
20
—
—
ns
ns
TDLCLK
tSTDLSIG
tHTDLSIG
TDLSIG
6143 drw10
Figure 45 Transmit Data Link Input Timing
AC ELECTRICAL CHARACTERISTICS
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*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TRANSMIT DATA LINK EOM INPUT
Symbol
Parameter
TDLEMOI Pulse Width3
Min.
Max.
Unit
tVTEOMI
5
0
—
—
ns
ns
3
tS1TEOMI
TDLEMOI Pulse to Falling Edge of WFDL
Transmit Data Register Write Set-up Time
tS2TEOMI
TDLEMOI Pulse to Next Falling Edge of
XFDL
0
—
ns
3
Transmit Data Register Write Set-up Time
tS3TEOMI
TDLEMOI Pulse After TDLINT Assertion3
—
210
µs
TDLINT
“write of last byte”
[i.e. WRB &
(A[8:] = 22H])
tHRPOS
tS3TEOMI
tS2TEOMI
TDLEOMI
tVTEOMI
6143 drw11
Figure 46 Transmit Data Link EOM Input Timing
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to
the 1.4 Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the
1.4 Volt point of the input.
3. TD1CLK frequency, TD2CLK frequency, tS1TEOMI, tS2TEOMI, tS3TEOMI and tVTEOMI values are guaranteed by design - not measured.
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TRANSMIT DS3 OUTPUT
Symbol
Parameter
TCLK Duty Cycle
Min.
Max.
Unit
TICLK -5 TICLK +5
%
ns
ns
tPTPOS
tPTNEG
TCLK Low to TPOS/TDAT Valid Prop. Delay
TCLK Low to TNEG/TMFP Valid Prop. Delay
-2
-2
5
5
TCLK
tPTPOS
TPOS/TDAT
tPTNEG
TNEG/TMFP
6143 drw12
Figure 47 Transmit DS3 Output Timing
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RECEIVE DS3 OUTPUT
Symbol
Parameter
Min.
Max.
Unit
tPRODAT
ROCLK Low to RODAT Valid Prop. Delay
ROCLK Low to RMFP Valid Propagation Delay
ROCLK Low to RMSFP Valid Prop. Delay
ROCLK Low to ROHP Valid Propagation Delay
ROCLK Low to RLOS Valid Propagation Delay
-3
-3
-3
-3
-3
3
3
3
3
3
ns
ns
ns
ns
ns
tPRMFP
tPRMSFP
tPROHP
tPRLOS
ROCLK
RODAT
tPRODAT
tPTMFP
RMFP
tPRMSFP
RMSFP
tROHP
ROHP
tPRLOS
RLOS
6143 drw13
Figure 48 Receive DS3 Output Timing
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RECEIVE OVERHEAD OUTPUT
Symbol
Parameter
Min.
Max.
Unit
tPROH
ROHCLK Low to ROH Valid Propagation
Delay
-5
20
ns
tPROHFP
tPRAIS
ROHCLK Low to ROHFP Valid Prop. Delay
-5
-5
20
20
ns
ns
ROHCLK Low to RAIS Valid Propagation
Delay
tPROOF
ROHCLK Low to ROOF Valid Prop. Delay
ROHCLK Low to RFERF Valid Prop. Delay
-5
-5
20
20
ns
ns
tPRFERF
ROHCLK
tPROH
ROH
tPROHFP
ROHFP
tPRAIS
tPROOF
tPRFERF
RAIS
ROOF/RRED
RFERF
6143 drw14
Figure 49 Receive Overhead Output Timing
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
TRANSMIT OVERHEAD OUTPUT
Symbol
Parameter
Min.
Max.
Unit
tPTOHFP
TOHCLK Low to TOHFP Valid Prop. Delay
-10
20
ns
TOHCLK
tPTOHFP
TOHFP
6143 drw15
Figure 50 Transmit Overhead Output Timing
RECEIVE TRIBUTARY OUTPUT
Symbol
Parameter
Min.
Max.
Unit
tPRD1DAT
RD1CLK Low to RD1DAT Valid Prop. Delay
-10
20
ns
RD1CLK
tPRD1DAT
RD1DAT
6143 drw16
Figure 51 Receive Tributary Output Timing
AC ELECTRICAL CHARACTERISTICS
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RECEIVE DATA LINK OUTPUT
Symbol
Parameter
Min.
Max.
Unit
tPRD1DAT
RD1CLK Low to RD1DAT Valid Prop. Delay
-10
20
ns
RDLCLK
tPRDLSIG
RDLSIG
6143 drw17
Figure 52 Receive Data Link Output Timing
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 20 pF load on the high-speed DS3 outputs (TCLK, TPOS/TDAT, TNEG/TMFP,
ROCLK, RODAT, RMFP, RMSFP, and ROHP) and a 50 pF load on the remaining outputs.
AC ELECTRICAL CHARACTERISTICS
113
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
AC ELECTRICAL CHARACTERISTICS
114
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
JTAG Timing Specifications
tJCYC
tJR
tJCH
tJCL
TCK
(1)
Device Inputs
/
TDI/TMS
tJH
tJDC
tJS
(2)
Device Outputs
/
TDO
tJCD
tJRSR
TRST
6143 drw17a
tJRST
Figure 53 Standard JTAG Timing
Notes:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO
JTAG
115
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
JTAG AC Electrical
Characteristics (1,2,3,4)
Symbol
Parameter
Min.
Max. Units
tJCYC
tJCH
tJCL
tJR
JTAG Clock Input Period
JTAG Clcok HIGH
JTAG Clock LOW
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
3(1)
3(1)
-
tJF
-
tJRST
tJRSR
tJCD
tJDC
tJS
50
50
-
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
-
25
-
0
15
15
-
tJH
JTAG Hold
-
Notes:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Value
Description
0x0
0x0312(1)
0x33
Reserved for version number
Defines IDT part number
IDT Device ID (27:12)
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
1
Note:
1. Device ID forIDT82V8313 is 0x0313.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
JTAG
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
plied to the pin a 1 will be read out on TDO for that corresponding pin.
All fourteen even T1 data outputs (D1DAT2,4,6...28) are inverted after
JTAG scan registers. So during JTAG EXTEST operation, their iverted
values will be output on the output pads. In other words if a 0 is loaded
into the pad, a 1 will be seen on the pin when looked at externally.
JTAG Information
All fourteen even T1 data inputs (TD1DAT2, 4, 6...28) are inverted before
JTAG scan registers. So during JTAG preload/sample operation, the in-
verted values will be shifted out in TDO output. In other words if 0 is ap-
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
0010
Places the bypass register (BYR) between TDI and TDO.
Loads the ID register (IDR) with the vendor ID code and places the register
between TDI and TDO.
HIGH-Z
0011
0001
Places the bypass register (BYR) between TDI and TDO. Forces all device
output drivers to a HIGH-Z state.
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO. SAMPLE
allows data from device input(2) to be captured in the boundary scan cells and
shifted serially through TDO. PRELOAD allows data to be input serially into the
boundary scan cells via the TDI.
RESERVED
All other codes
Several combinations are reserved. Do not use codes other than those
indentified above.
Notes:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST
3. The Boundary Scan Description Language (BSDL) file for this device is available on the IDT website (www.idt.com), or b y contacting you local
IDT sales representative.
JTAG
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
JTAG SCAN ORDER
Name
JTAG SCAN ORDER
In
Out
High-Z
Name
In
Out
High-Z
TD1CLK27
RD1DAT27
TD1DAT27
RD1CLK26
TD1CLK26
RD1DAT26
TD1DAT26
RD1CLK25
TD1CLK25
RD1DAT25
TD1DAT25
RD1CLK24
TD1CLK24
RD1DAT24
TD1DAT24
RD1CLK23
TD1CLK23
RD1DAT23
TD1DAT23
RD1CLK22
TD1CLK22
RD1DAT22
TD1DAT22
RD1CLK21
TD1CLK21
RD1DAT21
TD1DAT21
RD1CLK20
TD1CLK20
RD1DAT20
TD1DAT20
RD1CLK19
TD1CLK19
RD1DAT19
TD1DAT19
RD1CLK18
TD1CLK18
0
RD1DAT18
TD1DAT18
RD1CLK17
TD1CLK17
RD1DAT17
TD1DAT17
RD1CLK16
TD1CLK16
RD1DAT16
TD1DAT16
RD1CLK15
TD1CLK15
RD1DAT15
TD1DAT15
RD1CLK14
TD1CLK14
RD1DAT14
TD1DAT14
RD1CLK13
TD1CLK13
RD1DAT13
TD1DAT13
RD1CLK12
TD1CLK12
RD1DAT12
TD1DAT12
RD1CLK11
TD1CLK11
RD1DAT11
TD1DAT11
RD1CLK10
TD1CLK10
RD1DAT10
TD1DAT10
RD1CLK9
55
56
1
2
57
60
63
66
69
72
75
78
81
84
87
90
93
96
99
102
105
108
3
58
61
64
67
70
73
76
79
82
85
88
91
94
97
100
103
106
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
4
5
6
7
8
9
10
13
16
19
22
25
28
31
34
37
40
43
46
49
52
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
TD1CLK9
JTAG
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IDT82V8313
Name
3.3 VOLT M13 MULTIPLEXER
In
Out
High-Z
Name
In
Out
High-Z
RD1DAT9
TD1DAT9
RD1CLK8
TD1CLK8
RD1DAT8
TD1DAT8
RD1CLK7
TD1CLK7
RD1DAT7
TD1DAT7
RD1CLK6
TD1CLK6
RD1DAT6
TD1DAT6
RD1CLK5
TD1CLK5
RD1DAT5
TD1DAT5
RD1CLK4
TD1CLK4
RD1DAT4
TD1DAT4
RD1CLK3
TD1CLK3
RD1DAT3
TD1DAT3
RD1CLK2
TD1CLK2
RD1DAT2
TD1DAT2
RD1CLK1
TD1CLK1
RD1DAT1
TD1DAT1
TDLEMOI
TDLSIG
109
110
TDLCLK_INT
TIMFP
165
167
166
111
114
117
120
123
126
129
132
135
138
141
144
147
150
153
156
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
TICLK
168
169
171
173
175
177
179
181
183
185
187
189
191
193
194
195
197
199
201
203
205
207
209
210
211
212
214
216
218
221
224
227
TCLK
170
172
174
176
178
180
182
184
186
188
190
192
TPOS_DAT
RAIS
TNEG_MFP
GD2CLK
RODAT
ROCLK
RMFP
ROHP
TOHCLK
TOHFP
RMSFP
TOH
TOHEN
ROHFP
ROH
196
198
200
202
204
206
208
ROHCLK
RLOS
RFERF
ROOF_RED
REXZ
RCLK
RPOS_DAT
RNEG_LCV
RDCLK_INT
RDLSIG_EOM
INT
213
215
217
219
222
225
228
D0
220
223
226
229
D1
D2
159
160
161
164
D3
162
163
TD2CLK
JTAG
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Name
In
Out
High-Z
Name
In
Out
High-Z
A7
A8
251
252
253
254
255
D4
D5
D6
D7
CS
ALE
A0
A1
A2
A3
A4
A5
A6
230
233
236
239
242
243
244
245
246
247
248
249
250
231
234
237
240
232
235
238
241
WR
RD
RST
RD1CLK28
TD1CLK28
RD1DAT28
TD1DAT28
RD1CL27
256
259
262
257
260
263
258
261
Note:
All fourteen even T1 data inputs (TS1DAT2,4,6...28) are inverted before JTAG scan registers. So during JTAG preload/sample operation, the inverted values will be shifted out in TDO
output. In other words if a 0 is applied to the pin 1 will be read out on TDO for that corresponding pin.
All fourteen even T1 data outputs (RD1DAT2,4,6...28) are inverted after JTAG scan registers. So during JTAG EXTEST operation, their inverted values will be output on the output pads.
In other words if a 0 is loades into the pad, a 1 will be seen on the pin when looked at externally.
JTAG
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
ORDERING INFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Plastic Quad Flatpack (PQFP, DS208-1)
Plastic Ball Grid Array (PBGA, BB208-1)
DS
BB
82V8313
3.3V M13 Multiplexer
6143 drw18
Datasheet Document History
12/15/2003
03/15/2004
06/03/2004
Pgs. 1 thru 130
Pgs. 3 and 121.
Pgs. 101, 102 and 121.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-5116
fax: 408-492-8674
for Tech Support:
408-330-1552
email:TELECOMhelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
ORDERING INFORMATION
122
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STANDARDS
American National Standards Institute (ANSI)
ANSI T1.101 1994: Synchronization Interface Standard.
ANSI T1.102 1993: Digital Hierarchy: Electrical Interfaces.
ANSI T1.107 1995: Digital Hierarchy: Formats Specifications.
ANSI T1.231 1997: Digital Hierarchy: Layer1 In-Service Digital Transmission Performance Monitoring.
ANSI T1.403 1995: Network-to-Customer Installation Ds1 Metallic Interface.
ANSI T1.404 1994: Network-to-Customer Installation Ds3 Metallic Interface Specification
Bell Communications Research (Bellcore)
TR-TSY-000009 Issue 1, 05/1986: Asynchronous Digital Multiplexes - Requirements and Objectives.
TR-NWT-000170 Issue 2, 01/1993: Digital Cross-Connect System Generic Requirements and Objectives.
TR-NWT-000233 Issue 3, 11/1993: Wideband and Broadband Digital Cross-Connect Systems Generic Criteria.
TR-NWT-001112 Issue 1, 06/1993: Broadband-ISDN User to Network Interface and Network Node Interface Physical Layer Generic Criteria.
GR-499-CORE Issue 2, 12/1998: Transport Systems Generic Requirements (TSGR) Common Requirements.
GR-820-CORE Issue 2, 12/1997: Generic Digital Transmission Surveillance (A module of OTGR, FR-439).
GR-1244-CORE - Issue 1, 06/1995: Clocks for the Synchronized Network: Common Generic Criteria
International Telecommunication Union (ITU-T)
Recommendation G.703 04/91: Physical/electrical characteristics oh hierarchical digitalinterfaces
Recommendation G.704 07/95: Synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels
Recommendation G.706 04/91: Frame alignment and cyclic redundancy check (CGC) procedures relating to basic frame structures defined in
Recommendation G.704
Recommendation G.747 1988: Second order digital multiplex equipment operating at 6312 kbit/s and multiplexing three tributaries at 2048 kbit/s
Recommendation G.752 1988: Characteristics of digital multiplex equipment based on a second order bit rate of 6312 kbit/s and using positive
justification
Recommendation G.824 03/93: The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy
Recommendation M.20 10/92: Maintenance and Philosophy for telecommunication networks
Recommendation O.150 05/96: General requirements for instrumentation for performance measurements on digital transmission equipment
Recommendation O.151 10/92: Error performance measuring equipment operating at the primary rate and above
Recommendation O.152 10/92: Error performance measuring equipment for bit rates of 64 kbit/s and N x 64 kbit/s signals
Recommendation O.153 10/92: Basic parameters for the measurement of error performance at bit rates below the primary rate
Recommendation Q.921 03/93: ISDN user-network interface Data link layer specification
Standards
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
Network Working Group
RFC 2495 01/99: Definitions of Managed Objects for the Ds1, E1, Ds2 and E2 Interface Types.
Other documents
T1 Basics (Telecommunications Techniques Corporation - TTC)
The Fundamentals of Ds3 1992 (Telecommunications Techniques Corporation - TTC)
STANDARDS
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GLOSSARY
ADM
AIC
Add / Drop Multiplexer
Application Identification
AIS
Alarm Indication Singnal
AIS-CI
AISS
AMI
Alarm Indication Signal - Customer Installation
AIS Second
Alternate Mark Inversion
ANSI
B-DCS
BER
BERT
BITS
BnZS
BOC
BPV
C/R
American National Standards Institute
Broadband DCS
Bit Error Rate
Bit Error Rate Testing
Building Integrated Timing Source (or Supply)
Bipolar with n zero Substitution (n = 3 for Ds3 and 8 for Ds1 level)
Bit Oriented Code
Bipolar Violation
Command / Response
CAS-BR
CAS-CC
CC
Channel Associated Signaling - Bit Robbing (signaling distributed in each Ds0)
Channel Associated Signaling - Common Channel (in timeslot 24 in T1 channel)
Composite Clock
CCS
CFA
CGA
CI
Common Channel Signaling
Carrier Failure Alarm
Carrier Group Alarm
Customer Installation
COFA
CP
Change of Frame Alignment
Parity bit instead of stuffing indicator in Ds3 C-bit parity mode
Cyclical Redundancy Check
Controlled Slip
CRC
CS
CSS
CSU
CV
Controlled Slip Second
Customer Service Unit
Code Violation
GLOSSARY
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
CVCP
CVP
"Code Violation, CP-bit"
"Code Violation, P-bit"
DCS
Dsx
Digital Cross-connect System
"Digital Signal hierarchy, level x"
Extension Address (field)
Extended Superframe Format
Equipment Identification Channel
End of Message
EA
EDF
EIC
EOM
ERR
ES
Error
Errored Second
ESA
ESACP
ESAP
ESB
ESBCP
ESBP
ESCP
ESP
"Errored Second, type A"
"Errored Second, type A, CP-bit"
"Errored Second, type A, P-bit"
"Errored Second, type B"
"Errored Second, type B, CP-bit"
"Errored Second, type B, P-bit"
"Errored Second, CP-bit"
"Errored Second, P-bit"
Excessive Zeros
EXZ
EXZS
FAS
Excessive Zero Suppression
Frame Alignment Signal
Failure Count
FC
FCS
Frame Check Sequence
Facility Data Link
FDL
FEAC
FEBE
FEPR
FERF
FIC
Far End Alarm and Control Channel
Far End Block Error
Far End Performance Report
Far End Receive Failure
Fast Information Channel
General Positioning System
High Density Bipolar Three
High Level Data Link Control
High Speed Serial Link
Idle Pattern
GPS
HDB3
HDLC
HSSL
IDL
GLOSSARY
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
ISDN
ISID
ITU
Integrated Services Digital Network
Idle Signal Identification
International Telecommunication Union
Line
L
LAPD
LCV
LFE
LIC
Link Access Protocol on the D Channel
Line Code Violation
Line Far End
Location Identification Channel
Line Interface Unit
LIU
LOD
LOF
LOS
MART
MDL
MOP
NE
Loss of Data
Loss of Frame
Loss of Signal
Maximum Average Reframe Time
Maintenance Data Link
Message Oriented Protocol
Network Element
NP
Network Path
NPFE
NPRM
OC-n
OOF
P
Network Path
Network Performance Report Message
Optical Carrier level n
Out of Frame
Path
PER
PFE
PID
Parity Error Ratio
Path Far End
Path Identification
PM
Performance Monitoring
Polarity
POL
PRM
PRS
PS
Performance Report Message
Primary Reference Source
Protection Switching
Protection Switching Count
Protection Switching Duration
Path Terminating Equipment
Remote Alarm Indication
PSC
PSD
PTE
RAI
GLOSSARY
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IDT82V8313
3.3 VOLT M13 MULTIPLEXER
RAI-CI
RDI
Remote Alarm Indication - Customer Installation
Remote Defect Indication
RED
SAPI
SAS
Red Alarm
Service Access Point Identifier
Severely Errored Frame / Alarm Indication Signal (SEF/AIS) Second
Severely Errored Frame
SEF
SES
Severely Errored Second
SESCP
SESP
SF
"Severely Errored Second, CP-bit"
"Severely Errored Second, P-bit"
Superframe Format Signal
SLC96
SONET
SPRM
STS-n
TCA
Subscriber Loop Carrier (96 subscriber access line)
Synchronous Optical Network
Supplement Performance Report Message
Synchronous Transport Signal Level n (STS-1: transmission rate of 51.84 Mbit/s)
Threshold Crossing Alert
TEI
Terminal Endpoint Identifier
TSID
UAS
Test Signal Identification
Unavailable Second
UASCP
UASP
UDR
UI
"Unavailable Second, CP-bit"
"Unavailable Second, P-bit"
Underrun
Unit Interval
VT
Virtual Tributary (VT1.5: 1.544 Mbit/s signal encapsulated in a higher rate)
Wideband DCS
W-DCS
ZBTSI
Zero-byte time slot interchange
GLOSSARY
128
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INDEX
FEBE - Far End Block Error...............................................11, 19, 27, 71
ALTFEBE..................................................................................... 19
DFEBE ........................................................................................ 23
FEBE........................................................................................... 27
FERF - Far End Receive Failure................... 1, 6, 22, 37, 39, 40, 42, 71
FERF0......................................................................................... 46
FERFE................................................................................... 37, 42
FERFI.................................................................................... 39, 42
FERFV....................................................................... 37, 39, 40, 43
RFERF .................................................................... 5, 6, 37, 39, 67
XFERF......................................................................................... 46
H
HDLC - High Level Data Link Control...................6, 8, 11, 16, 20, 28, 71
REXHDLC ................................................................... 6, 16, 17, 20
TEXHDLC.............................................................. 8, 16, 17, 20, 21
I
IDL - Idle Pattern........................................................................... 22, 71
IDLE .................................................................... 35, 36, 37, 39, 40
IDLEI ........................................................................................... 35
IDLI.............................................................................................. 39
IDLV............................................................................................. 40
RIDL ........................................................................................ 5, 22
L
LAPD - See Previous Page for Description....................... 29, 30, 31, 71
LCV - Line Code Violation..............................................1, 11, 24, 38, 71
DLCV........................................................................................... 23
RLCV....................................................................................... 5, 63
LOF - Los Of Frame........................................................................ 1, 71
LOS - Loss Of Signal .......................................................... 1, 19, 39, 71
DLOS........................................................................................... 22
LOS ............................................................................................. 37
LOSE........................................................................................... 37
LOSI............................................................................................ 39
LOSV............................................................................... 37, 39, 40
RLOS........................................................................... 5, 37, 39, 66
O
OOF - Out Of Frame ................................... 5, 19, 36, 37, 39, 41, 42, 71
OOFE .................................................................................... 37, 42
OOFI............................................................................................ 39
OOFV ........................................................................ 37, 39, 40, 43
ROOF................................................................ 5, 6, 19, 37, 39, 67
ROOV.......................................................................................... 37
P
A
AIS - Alarm Indication Signal 1, 6, 12, 17, 19, 22, 23, 32, 33, 36, 37, 38,
39, .........................................................................40, 42, 43, 46, 47, 71
AISC ......................................................................................36, 38
AISE.......................................................................................37, 42
AISI........................................................................................39, 43
AISONES...............................................................................36, 38
AISPAT...................................................................................36, 38
AISV...........................................................................37, 39, 40, 43
DAIS ......................................................................................32, 47
LINEAIS.......................................................................................17
MAIS......................................................................................33, 47
RAIS ........................................................................5, 6, 37, 39, 67
XAIS.............................................................................................46
B
BOC - Bit Oriented Code ...............................................................35, 71
BOCE...........................................................................................35
BOCI............................................................................................35
RBOC ....................................................................9, 12, 20, 35, 71
XBOC...............................................................................12, 34, 35
C
CRC - Cyclical Redundancy Check.........................................28, 31, 71
CCITT-CRC .................................................................................28
E
EOM - End Of Message...........................................8, 28, 30, 31, 65, 71
RDLEOM ...............................................................6, 16, 17, 20, 31
RFDLEOM ...................................................................................20
ERR - Error..........................................................................................71
CPERR ............................................................................ 11, 26, 27
DCPERR......................................................................................23
DFERR ........................................................................................23
DMERR........................................................................................23
DPERR ........................................................................................23
FERR............................................................. 11, 12, 24, 25, 41, 44
PERR......................................................................... 11, 12, 26, 45
RFERR ..........................................................................................5
EXZS - Excessive Zero Suppression................................. 11, 25, 38, 71
EXZSO.........................................................................................38
F
FDL - Facility Data Link .......................................................................71
RFDL ...............................................................6, 12, 20, 29, 30, 31
RFDLEOM ...................................................................................20
RFDLINT......................................................................................20
WFDL...........................................................................................65
XFDL.......................................................... 8, 11, 20, 21, 28, 29, 65
XFDLINT......................................................................................20
XFDLUDR....................................................................................21
FEAC - Far End Alarm Control....................................12, 20, 34, 35, 71
POL - Polarity...................................................................................... 71
REMPOL ..................................................................................... 17
RINTPOL..................................................................................... 17
TINTPOL ..................................................................................... 17
TUDRPOL ................................................................................... 17
INDEX
129
June 3, 2004
*Notice: The information in this document is subject to change without notice
IDT82V8313
3.3 VOLT M13 MULTIPLEXER
R
RAI - Remote Alarm Indication..................................................1, 43, 46
RED - Red Alarm.............................................19, 36, 37, 39, 40, 42, 71
RED2 ...........................................................................................20
RED2ALME .................................................................................19
RED3 ...........................................................................................20
RED3ALME .................................................................................19
REDE.....................................................................................37, 42
REDI ......................................................................................39, 42
REDO ..........................................................................6, 19, 37, 39
REDV...................................................................37, 39, 40, 42, 43
RRED...........................................................................6, 19, 37, 39
U
UDR - Underrun.............................................................................28, 71
TDLUDR ......................................................................8, 16, 17, 21
XFDLUDR....................................................................................21
INDEX
130
June 3, 2004
*Notice: The information in this document is subject to change without notice
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