IDTCV107EPVG [IDT]
Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48;
| 型号： | IDTCV107EPVG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总21页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
IDTCV107E
DESCRIPTION:
FEATURES:
IDTCV107Eisa48pinclockgenerationdevicefordesktopPCplatforms.
ThischipincorporatesfourPLLstoallowindependentgenerationofCPU,AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referencedIREF toreducetheimpactofVDD variationondifferentialoutputs,
whichcanprovidemorerobustsystemperformance.
• 4 PLL architecture
• Linear frequency programming
• Independent frequency programming and SSC control
• Band-gap circuit for differential output
• High power-noise rejection ratio
• 66MHz to 533MHz CPU frequency
• VCO frequency up to 1.1G
• Support index block read/write, single cycle index block read
• Programmable REF, 3V66, PCI, 48MHz I/O drive strength
• Programmable 3V66 and PCI Skew
• Available in SSOP package
StaticPLLfrequencydivideerrorcanbeaslowas36ppm,providinghigh
accuracyoutputclock. EachCPU,AGP/PCI,SRCclockhasitsownSpread
Spectrumselection.
KEYSPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 125ps
• SATA CLK cycle to cycle jitter < 125ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error as low as 36 ppm
FUNCTIONALBLOCKDIAGRAM
PLL1
SSC
EasyN
CPU CLK
CPU[1:0]
Output Buffers
Programming
X1
XTAL
Osc Amp
IREF
REF 2.1.0
X2
AGP/PCI
Output Buffers
PLL2
SSC
EasyN
Programming
PCI[5:0], PCIF[2:0]
3V66[3:0]
SDATA
SM Bus
Controller
SCLK
SRC CLK
Output Buffer
PLL3
SSC
SRC
VTT_PWRGD
Watch Dog
Timer
IREF
FS[1:0]
Control
Logic
48MHz[1:0]
SEL24_48#
48MHz
Output Buffer
PLL4
24 - 48MHz
RESET#
OUTPUTTABLE
CPU (Pair)
3V66
3V66/VCH
PCI
PCIF
REF
48MHz
24 - 48MHz
SRC (Pair)
Reset#
2
3
1
6
3
3
2
1
1
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-6390/15
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
*FS1/REF0
*FS0/REF1
REF2
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
2
VSS
TSTG
Storage Temperature
–65
0
+150
+70
+115
° C
° C
° C
V
3
IREF
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
4
RESET#
VSS
VDD_REF
5
X1
X2
ESD Prot Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2000
6
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS
VSS
PCIF0
7
8
PCIF1
9
PCIF2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_PCI
VSS
SRCT
PCI0
SRCC
PCI1
VDD_SRC
*VTT_PWRGD/PD#
*SDATA
*SCLK
PCI2
PCI3
HWFREQUENCYSELECTION
VDD_PCI
VSS
FS1.0
00
CPU
100
AGP
66.66
66.66
66.66
66.66
PCI
33.3
33.3
33.3
33.3
N Resolution
0.223721591
0.447443181
0.298295454
0.397727272
3V66_0
3V66_1
VSS
PCI4
01
200
PCI5
10
133.33
166.67
**SEL24/24_48MHz
48MHz0
48MHz1
VSS
VDD_3V66
3V66_2
3V66_3/VCH
11
VDD48
* = ~ 130KΩ internal pull-up.
** = ~ 130KΩ internal pull-down.
SSOP
TOP VIEW
2
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
SWFREQUENCYSELECTION
BS[2:0] and WBS[2:0] are band selects. Whenever there is a band switch, the user has to issue a WD soft alarm (see Byte 32 and Byte 33).
In CPU N/M programming, CPU frequency = N * resolution.
WDBS[2:0]or WDBS[2:0]or WDBS[2:0]or
WDBS[2:0]or WDBS[2:0]or WDBS[2:0]or WDBS[2:0]or
WDBS[2:0]or
BS[2:0]=111
CFS[3:0]
BS[2:0]=000 BS[2:0]=001
BS = 010
133.34
135.13
138.11
139.9
BS[2:0]=011
166.65
167.84
169.83
173.01
175
BS[2:0]=100
200.01
BS[2:0]=101 BS[2:0]=110
000
100
100.9
200.01
201.8
400.01
401.8
266.66
267.57
333.3
001
66.67
334.89
010
102.91
104.93
110.07
114.99
119.91
125.06
0.223721591
447
204.93
209.85
215.22
220.14
225.06
229.99
0.447443181
447
011
100
101
141.99
144.97
147.95
150.05
0.298295454
447
178.18
180.17
184.94
0.397727272
419
110
111
NResolution
CorrespondingN
0.447443181
447
0.894886363
447
0.894886363
298
0.795454544
419
SPREADSPECTRUMMAGNITUDE
3V66-PCI/FSKEW
CONTROL(SMC)
Skew[2:0]
000
001
010
011
100
101
110
111
normal, 3V66 leads PCI 2.5ns
moveforward200ps
SMC[2:0]
000
001
010
011
100
101
110
111
Off
-0.25
- 0.5
moveforward400ps
moveforward600ps
movebackward200ps
movebackward400ps
movebackward600ps
movebackward800ps
-0.75
- 1
± 0.125
± 0.25
± 0.375
AGP/PCISTRENGTH
Str[1:0]
(1)
0, 0
2H
(2)
AGP/PCIFREQUENCYSELECTION
0, 1
1L
In AGP/PCI N/M programming, AGP frequency = N * 0.223721591
(2)
1, 0
1H
(1)
AFS[2:0]
000
AGP
66.67
68.68
70.7
PCI
Corresponding N
1, 1
2L
33.33
34.34
35.35
36.35
37.25
38.26
39.26
40.27
298
307
316
325
333
342
351
360
NOTES:
1. Recommended for multiple load.
2. Recommended for single load.
001
010
011
72.71
74.5
100
REFSTRENGTH
101
76.51
78.53
80.54
REFStr[1:0]
110
(1)
0, 0
2L
111
(2)
0, 1
1H
(1)
1, 0
2H
(2)
1, 1
1L
NOTES:
1. Recommended for multiple load.
2. Recommended for single load.
3
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
Pin Number
Name
FS1/REF0
FS0/REF1
VDD_REF
VDD_REF
X1
Type
I/O
Description
1
2
Frequencyselectlatchinput3.3VinputHIGH/LOWvoltage/14.318MHzreferenceclockoutput(1)
Frequencyselectlatchinput2.5VinputHIGH/LOWvoltage/14.318MHzreferenceclockoutput(1)
I/O
3
PWR
PWR
IN
3.3V
4
3.3V
5
Xtalinput
Xtaloutput
GND
6
X2
OUT
GND
I/O
7
VSS
(2)
8
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS
Frequency select latch input 3.3V input HIGH/LOW voltage/ PCI free running clock
9
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
I/O
PCIfree runningclock
PCIfree runningclock
3.3V
10
11
12
13
14
15
16
17
18
19
20
21
GND
PCI0
PCI clock
PCI clock
PCI clock
PCI clock
3.3V
PCI1
PCI2
PCI3
VDD_PCI
VSS
GND
PCI4
PCI clock
PCI clock
PCI5
SEL24/24_48MHZ
24MHz or 48MHz clock output. Frequency selected by SEL24 latch input. 1 = 24MHz, 0 = 48MHz,
alsocanbe programmedthroughSMBus Byte 34.(2)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
48MHz0
48MHz1
VSS
OUT
OUT
GND
PWR
OUT
OUT
PWR
GND
OUT
OUT
IN
48MHzclockoutput. OutputdrivestrengthcanbedoubledthroughSMprogramming. Poweronis2x.
48MHzclockoutput
GND
VDD48
3.3V
3V66_3/VCH
3V66_2
VDD_3V66
VSS
66MHz or 48MHz clock output. Selectable by SMBus. Power on is 66MHz.
66MHzclockoutput
3.3V
GND
3V66_1
3V66_0
SCLK
66MHzclockoutput
66MHzclockoutput
(1)
SMBus clock
SDATA
VTT_PWRGD/PD#
VDD_SRC
SRCC
I/O
SMBus data(1)
IN
Used for power on latch, active HIGH after power on becomes power down control, active LOW.(1)
PWR
OUT
OUT
GND
OUT
OUT
3.3V
SATA0.7Vcurrentmodedifferentialclockoutput
SATA0.7Vcurrentmodedifferentialclockoutput
GND
SRCT
VSS
CPUC0
CPUT0
Hosts0.7Vcurrentmodedifferentialclockoutput
Hosts0.7Vcurrentmodedifferentialclockoutput
NOTES:
1. ~ 130KΩ internal pull-up.
2. ~ 130KΩ internal pull-down.
4
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
PINDESCRIPTION(CONT.)
Pin Number
Name
VDD_CPU
CPUC1
CPUT1
VSS
Type
PWR
OUT
OUT
GND
OUT
OUT
GND
PWR
Description
41
42
43
44
45
46
47
48
3.3V
Hosts0.7Vcurrentmodedifferentialclockoutput
Hosts0.7Vcurrentmodedifferentialclockoutput
GND
RESET#
IREF
Resetsignalfromwatchdogcircuit
Referencecurrentfordifferentialclockoutput
VSS
GND
3.3V
VDDA
5
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
SMBUSPROTOCOL
INDEXBLOCK WRITEPROTOCOL
ONECYCLE™INDEXBLOCKREAD
Bit
1
# of bits From
Description
Bit
1
# of bits From
Description
1
8
1
8
1
8
1
8
1
8
1
Master Start
Master D2h
Slave Acknowledge
Master Registeroffsetbyte(startingbyte)
Slave Acknowledge
Master Byte count N (0 is not a valid byte count)
Slave Acknowledge
Master Firstdatabyte
Slave Acknowledge
Master Seconddatabyte
1
8
1
8
1
8
Master
Master
Slave
Start
2-9
2-9
D2h
10
10
Acknowledge
11-18
19
11-18
19
Master
Slave
Registeroffsetbyte(startingbyte)
Acknowledge
(1)
20-27
28
20-27
Master
1xxxxxxx. Bit[20] = 1, followed with byte
count, which will be stored into SMBus table
byte 8.
29-36
37
28
29
1
1
8
1
8
Slave
Master
Master
Slave
Slave
Acknowledge
Repeatedstart
D3h
38-45
46
30-37
38
Slave
Acknowledge
Acknowledge
:
39-46
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
Nthdatabyte
Stop
47
48-55
56
1
8
1
8
Master
Slave
Master
Slave
Acknowledge
NOTE:
1. Bit [21:27] = byte count.
Bit 20 = 1, bit [21:27] will be stored into SMBus table, Byte 8. SM Bus Byte 8 is read
byte count register, power on default is 0FH.
Offsetdatabyte,specifiedbybit[11:18]
Acknowledge
Offset+1data byte
:
57-64
Bit 20 = 0, normal SM bus operation.
Slave
Master
Slave
Offset + N-2
Acknowledge
Offset + N-1
Notacknowledge
Stop
INDEXBLOCKREADPROTOCOL
Bit
1
# of bits From
Description
1
8
1
8
1
1
8
1
8
Master Start
Master D2h
Slave Acknowledge
Master Registeroffsetbyte(startingbyte)
Slave Acknowledge
2-9
10
11-18
19
BYTEWRITEMETHODS:
20
Master Repeatedstart
Master D3h
• Setting bit[11:18] = starting address, bit [20:27] = 01H.
21-28
29
Slave
Slave
Acknowledge
30-37
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
38
39-46
47
1
8
1
8
Master
Slave
Acknowledge
BYTE READ METHODS (CHOSE ONE):
• Use IDT OneCycle Index Block Read, bit[20:27] = 10000001.
Notice that byte count register (byte 8) will be changed to 0IH.
• Use Index Block Write protocol to change byte count (byte 8) to
1. After that, use Index Block Read.
Offsetdatabyte,specifiedbybit11-18
Master Acknowledge
48-55
Slave
Slave
Offset+1data byte
:
Offset + N-2
Master Acknowledge
TO CHANGE BYTE 8 VALUE:
• Use IDT OneCycle Index Block Read, as above
• Use Index Block Write protocol to change byte 8 value.
Slave
Offset + N-1
Notacknowledge
Stop
6
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
BYTE 0: DUMMY BYTE
BYTE 1
Bit
7
Output(s)Affected
Reserve
Description/Function
0
1
Type
Power On
0
0
1
0
1
1
1
1
6
Reserve
5
SS_EN
Spreadspectrumenable
Outputenable
On
Off
RW
RW
4
Reserve
3
SRCT, SRCC
Reserve
Tristate
Enable
2
1
CPUT1, CPUC1
CPUT0, CPUC0
Outputenable
Outputenable
Tristate
Tristate
Enable
Enable
RW
RW
0
BYTE 2
Bit
7
Output(s)Affected
Description/Function
0
1
Type
Power On
SRCT
Reserve
CPUT1, 0
Reserve
3V66_2
SRCT Powerdown drive mode
CPUT Powerdown drive mode
Outputenable
Driven in power down
Driven in power down
Tristate
Tristateinpowerdown
RW
RW
RW
0
0
0
0
1
1
1
1
6
5
Tristateinpowerdown
Enable
4
3
2
Reserve
Reserve
Reserve
1
0
BYTE 3
Bit
7
Output(s)Affected
Reserve
Reserve
PCI5
Description/Function
0
1
Type
Power On
Recommended
0
1
1
1
1
1
1
1
6
RW
RW
RW
RW
RW
RW
RW
0
5
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
4
PCI4
3
PCI3
2
PCI2
1
PCI1
0
PCI0
7
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
BYTE 4
Bit
Output(s)Affected
Description/Function
Drivestrength
0
1
Type
Power On
Recommended
7
48MHz0
2 * DRIVE
100MHz
Normal
200MHz
RW
0
1
6
5
SRCFS0
Reserve
SRCfrequencyselect
RW
RW
0
1
0
4
3
2
1
0
3V66_1
3V66_0
PCIF2
PCIF1
PCIF0
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
1
1
1
1
1
BYTE 5
Bit
7
Output(s)Affected
Description/Function
0
1
Type
Power On
3V66_3/VCH
Reserve
3V66_3/VCH modeselect
3V66 mode, 66MHz
VCH mode, 48MHz
RW
0
0
0
1
0
0
0
0
6
5
Reserve
4
3V66_3/VCH
Reserve
Outputenable
Tristate
Enable
RW
3
2
Reserve
1
Reserve
0
Reserve
BYTE 6: DUMMY BYTE
BYTE 7
Bit
7
Output(s)Affected
Description/Function
0
1
Type
Power On
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
x
x
x
x
0
1
0
1
6
5
4
3
2
1
0
8
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
BYTE 8 (READ BYTE COUNT REGISTER)
Bit
7
Output(s)Affected
Description/Function
0
1
Type
Power On
Reserve
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0
0
0
0
1
0
0
1
6
Seenote1
5
4
3
2
1
0
NOTE:
1. Can be written by index block write or OneCycle block read. See SMBUS PROTOCOL tables.
BYTES 9-20: DUMMY BYTES
BYTE21
Bit
7
Output(s)Affected
PCIFStr1
PCIFStr0
Reserve
Description/Function
AGP/PCI STRENGTH table
AGP/PCI STRENGTH table
0
1
Type
Power On
1
1
1
1
1
1
1
1
6
5
4
Reserve
3
Reserve
2
Reserve
1
3V66Str1
3V66Str0
AGP/PCI STRENGTH table
AGP/PCI STRENGTH table
0
BYTE22
Bit
7
Output(s)Affected
Description/Function
0
1
Type
Power On
Recommended
REFStr1
REFStr0
REF STRENGTH table
REF STRENGTH table
1
0
1
1
1
1
1
1
6
5
PCIStrC1
PCIStrC0
PCIStrB1
PCIStrB0
PCIStrA1
PCIStrA0
PCI[7:5] strength control, AGP/PCI STRENGTH table
PCI[7:5] strength control, AGP/PCI STRENGTH table
PCI[4:2] strength control, AGP/PCI STRENGTH table
PCI[4:2] strength control, AGP/PCI STRENGTH table
PCI[1:0] strength control, AGP/PCI STRENGTH table
PCI[1:0] strength control, AGP/PCI STRENGTH table
1
0
1
0
1
0
4
3
2
1
0
9
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
BYTE23
Bit
7
Output(s)Affected
48MHz0
24_48MHz
REF1
Description/Function
Outputenable
0
1
Type
RW
RW
RW
RW
RW
RW
RW
Power On
Recommended
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
0
6
Outputenable
5
Outputenable
4
REF0
Outputenable
3
REF2
OutputEnable
Outputenable
2
48MHz1
Reserve
Reserve
1
0
0
BYTE24
Bit
7
Output(s)Affected
WDHRB
Description/Function
0
1
Type
R
Power On
WDhardalarmstatusreadback
WDsoftalarmstatusreadback
6
WDSRB
R
5
4
3
2
0
1
FSR1
FSR0
HW FS1 read back
HW FS0 read back
R
R
HW FS1
HW FS0
0
BYTE 25: CPU PLL CONTROL
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPUfrequencybandsource select
0 = selected by HW latched FS[1:0], CFS[2:0]
1 = selected by BS[2:0], CFS[2:0]
HW
SW
RW
0
(1)
6
5
4
3
2
1
0
BS2, Band select 2
BS1, Band select 1
BS0, Band select 0
CFS2
BS[2:0] CFS[2:0] select CPU frequency
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
(1)
BS[2:0] CFS[2:0] select CPU frequency
(1)
BS[2:0] CFS[2:0] select CPU frequency
(1)
BS[2:0] CFS[2:0] select CPU frequency
(1)
CFS1
BS[2:0] CFS[2:0] select CPU frequency
(1)
CFS0
BS[2:0] CFS[2:0] select CPU frequency
CPU N Programming Enable
CPU N Programming Enable
Disable
Enable
NOTES:
1. See SW FREQUENCY SELECTION table.
10
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
BYTE 26: CPU PLL CONTROL
Bit
7
Output(s)Affected
WDBS2
Description/Function
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
AttheeventofWDhardalarmtimeout,
If Byte 32 bit 7 = 1, CPU frequency is
1
0
0
0
1
0
0
1
6
WDBS1
(1)
5
WDBS0
selected by WDBS[2:0] WDCFS[2:0]
4
CSMC2
CSMC1
CSMC0
CPN9
CPU SMC2, SMC table
CPU SMC1, SMC table
CPU SMC0, SMC table
CPU PLL N9
3
2
1
0
CPN8
CPU PLL N8
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 27: CPU PLL N PROGRAMMING
In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N driver. See
SWFREQUENCYSELECTIONtable.
Bit
7
Output(s)Affected
CPN7
Description/Function
CPU PLL N7
CPU PLL N6
CPU PLL N5
CPU PLL N4
CPU PLL N3
CPU PLL N2
CPU PLL N1
CPU PLL N0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
1
0
1
0
1
0
6
CPN6
5
CPN5
4
CPN4
3
CPN3
2
CPN2
1
CPN1
0
CPN0
BYTE 28: AGP/PCI PLL CONTROL
Bit
7
Output(s)Affected
AFS2
Description/Function
0
1
Type
Power On
See AGP/PCI FREQUENCY SELECTION table
See AGP/PCI FREQUENCY SELECTION table
See AGP/PCI FREQUENCY SELECTION table
AGP/PCIWDhardalarmtime outfrequencyselection
AGP/PCIWDhardalarmtime outfrequencyselection
AGP/PCIWDhardalarmtime outfrequencyselection
AGP/PCI PLL N9
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
6
AFS1
5
AFS0
4
WDAFS2
WDAFS1
WDAFSO
APN9
3
2
1
0
APN8
AGP/PCI PLL N8
11
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
BYTE 29: AGP/PCI N PROGRAMMING
InAGP/PCINprogrammingmode, AGP/PCIfrequency=APN[9:0]*0.223721591. APN0hastobewrittenfortheAPN[9:0]tobeloadedintoPLLNdivider.
Bit
7
Output(s)Affected
APN7
Description/Function
AGP/PCI PLL N7
AGP/PCI PLL N6
AGP/PCI PLL N5
AGP/PCI PLL N4
AGP/PCI PLL N3
AGP/PCI PLL N2
AGP/PCI PLL N1
AGP/PCI PLL N0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
1
0
1
0
1
0
6
APN6
5
APN5
4
APN4
3
APN3
2
APN2
1
APN1
0
APN0
BYTE 30: AGP/PCI SRC CONTROL
Bit
7
Output(s)Affected
Description/Function
AGP/PCI N Programming Enable
0 = fixed 66/33MHz
0
1
Type
Power On
AGP/PCI N Programming Mode Enable
AGP/PCI Frequency Source Select
Disable
Enable
RW
RW
0
0
6
66/33MHz
(1)
1 = selected by AFS[2:0]
(2)
5
4
3
2
1
0
AGP SMC 2
AGP SMC 1
AGP/PCI SSC magnitude control
RW
RW
RW
RW
RW
RW
0
1
0
0
0
0
(2)
AGP/PCI SSC magnitude control
(2)
AGP SMC 0
AGP/PCI SSC magnitude control
(3)
3V66-PCI/F skew 2
3V66-PCI/F skew 1
3V66-PCI/F skew 0
Adjust 3V66 and PCI/F skew
(3)
Adjust 3V66 and PCI/F skew
(3)
Adjust 3V66 and PCI/F skew
NOTES:
1. See AGP/PCI FREQUENCY SELECTION table.
2. See SMC table.
3. See 3V66 AND PCI/F SKEW table.
BYTE 31: WATCHDOG TIMER
Bit
7
Output(s)Affected
WD Hard Alarm timer 7
WD Hard Alarm timer 6
WD Hard Alarm timer 5
WD Hard Alarm timer 4
WD Hard Alarm timer 3
WD Hard Alarm timer 2
WD Hard Alarm timer 1
WD Hard Alarm timer 0
Description/Function
Specify WD Hard Alarm time out waiting time.
Time Out time = WD Hard Alarm timer[7:0] * 290ms
Defaultis 11*290=3.2s
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
1
0
1
1
6
5
4
3
2
1
0
12
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
BYTE 32: WD SOFT RESET TIMER
WDSoftAlarmtimerhastobeshorterthanWDHardAlarmtimer. WDEandWDSoftAlarmbits,Byte33bit7andbit5,havetobeenabledforthisSoftAlarm
function.
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPU WD Hard Alarm
safefrequencymodeselect
0 = frequency select controlled by Byte 25 bit 7
1 = CPU frequency specified
HW/SMBus
WDBS
WDCFS
RW
0
by WDBS[2:0] WDCFS[2:0]
6
5
4
3
2
1
0
WDCFS2
CPU WD time out safe frequency select(1)
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
1
0
WDCFS1
WDCFS0
WDsoftalarmtimer3
WDsoftalarmtimer2
WDsoftalarmtimer1
WDsoftalarmtimer0
Specify WD Soft Alarm Time Out time
TimeOuttime=WDSoftAlarmTimer[3:0]*290ms
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 33: WD CONTROL
Bit
7
Output(s)Affected
WDE
Description/Function
Watchdogenable
0
1
Type
RW
RW
Power On
Disable
Disable
Enable
Enable
0
0
6
WDFSrelatch
Relatch HW FS2, 1, 0
in event of WD Hard Alarm time out
WDSoftAlarmenable
5
4
WDSoftAlarmenable
Disable
Enable
RW
RW
0
0
AGP/PCI WD Hard Alarm
In event of WD Hard Alarm time out
HW/SMBus WDAFS
timeoutsafefrequencymodeselect 0 = AGP/PCI frequency controlled by Byte 30 bit 6
1 = AGP/PCI frequency specified by WDAFS[2:0]
(1)
3
2
1
0
SRC SMC 2
SRC SMC 1
SRC SMC 0
Reserve
SRC SSC magnitude control
1
0
1
0
(1)
SRC SSC magnitude control
(1)
SRC SSC magnitude control
NOTE:
1. See SMC table.
BYTE34
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
SW24_48MHzcontroloverride
0 = controlled by hardware, 1 = controlled by bit 6 HWcontrol controlledby
bit 6
RW
0
6
5
4
3
2
1
0
24_48MHzselect
Reserve
48MHz
24MHz
RW
RW
0
0
0
0
13
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
CPUANDAGPCLOCKFREQUENCYSELECTION
BandswitchwilltakeeffectonlywhenWDSoftAlarmtimeoutisissued,whichmeansthereisaRESETissued. EveniftheuserchangedBS[2:0],ifthere
is noWDSoftAlarm,CPUPLLstilluses theoldband.
CPN[9:0] and APN[9:0] will be loaded into PLL only when CPN0 and APN0 are written respectively.
AGP/PCIFREQUENCY
CPUFREQUENCY
Byte 30 bit 7, bit 6
AGP/PCI Frequency Selected by:
Byte 25 bit 0, bit 7
CPU Frequency Selected by:
HW FS[1:0]
00
01
10
11
66/33
00
01
10
11
AFS[2:0], Byte 28
BS[2:0], CFS[2:0], Byte 25
CPN[9:0] * Band Resolution
CPN[9:0] * Band Resolution
APN[9:0]*0.223721591
APN[9:0]*0.223721591
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
WD HARD ALARM TIME OUT
Set WDHRB
WD SOFT ALARM TIME OUT
If WD Soft Alarm Enabled:
Set WDSRB
Trigger Watch Dog Circuit
Issue RESET#
Change CPU Frequency (see Byte 32, bit 7)
Change AGP/PCI Frequency (see Byte 33, bit 4)
If WD FS Relatch enabled, relatch HW FS2, FS1, FS0
Reset Byte 30 bit 7, and Byte 25 bit 0, to 0
Issue RESET#
Switch CPU PLL band
Useronlyuses WDSoftAlarmwhenthere is a bandswitch. Itcanbe fromHWtoSWselect, orinthe SWselectwithbandchange. SoftAlarmTimerhas
to be shorter than Hard Alarm Timer.
AttheeventofWDHardAlarmtimeout,CPUSafereturnfrequencyisdecidedbytwobits:Byte32bit7andByte25bit7. AGP/PCISafeReturnFrequency
is decided by Byte 33 bit 4 and Byte 30 bit 6. Byte 30 bit 7, and Byte 25 bit 0, will be reset to 0.
Byte 32 bit 7,
CPU WD Hard Alarm Time Out Frequency Select:
Byte 33 bit 4,
AGP/PCI Hard Alarm Time Out Frequency Select:
Byte 25 bit 7
Byte 30 bit 6
00
01
10
11
Latched HW FS[1:0]
00
01
10
11
66/33MHz
BS[2:0], CFS[2:0], Byte 25
AFS[2:0], Byte 28
WDAFS, Byte 28
WDAFS, Byte 28
WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
14
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIH
3.3V Input HIGH Voltage
3.3V ± 5%
2
—
VDD + 0.3
V
VIL
IIH
3.3V Input LOW Voltage
Input HIGH Current
3.3V ± 5%
VIN = VDD
VSS - 0.3
–5
—
—
0.8
5
V
µ A
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors –200
Full active, CL = full load
–5
—
—
—
µ A
400
70
12
—
7
µ A
IIL2
Input LOW Current
—
—
—
—
—
—
—
—
—
—
30
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
mA
mA
All differential pairs driven
—
All differential pairs tri-stated
VDD = 3.3V
—
(2)
FI
Input Frequency
14.31818
—
MHz
nH
LPIN
Pin Inductance(3)
CIN
Logic inputs
—
5
COUT
CINX
TSTAB
Input Capacitance(3)
Clock Stabilization(3,4)
Output pin capacitance
—
6
pF
X1 and X2 pins
—
5
From VDD power-up or de-assertion of PD# to first clock
Triangular modulation
—
1.8
33
15
300
5
ms
KHz
ns
(3)
Modulation Frequency
—
(3)
TDRIVE_SRC
SRC output enable after PCI_Stop# de-assertion
CPU output enable after PD# de-assertion
Fall time of PD#
—
—
—
—
—
—
—
—
TDRIVE_PD#(3)
TFALL_PD#(3)
—
us
—
ns
(4)
TRISE_PD#
Rise time of PD#
—
5
ns
TDRIVE_CPU_Stop#(3)
TFALL_CPU_Stop#(3)
TRISE_CPU_Stop#(4)
CPU output enable after CPU_Stop# de-assertion
Fall time of PD#
—
10
5
us
—
ns
Rise time of PD#
—
5
ns
NOTES:
1. Available to CV104, CV105, CV107, and CV109.
2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
3. This parameter is guaranteed by design, but not 100% production tested.
4. See TIMING DIAGRAMS for timing requirements.
15
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(2)
Maximum Voltage (Overshoot)
Minimum Voltage (Undershoot)
VO = VX
VOVS
VUDS
VH + 0.3
—
V
-0.3
660
–150
—
V
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
850
mV
(2)
Voltage LOW
150
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
1150
—
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Variation of crossing over all edges
140
(2,3)
Long Accuracy
See TPERIOD Min. - Max. values
400MHz nominal, no Intel spec
333.33MHz nominal, no Intel spec
266.66MHz nominal, no Intel spec
–300
—
—
—
—
300
2.4993
2.9991
3.7489
2.5008
3.0009
3.7511
TPERIOD
Average Period(3)
200MHz nominal
4.9985
—
5.0015
ns
166.66MHz nominal
5.9982
7.4978
9.997
—
—
—
—
—
—
6.0018
7.5023
10.003
2.5008
3.0009
3.7511
133.33MHz nominal
100MHz nominal
400MHz spread, no Intel spec
333.33MHz spread, no Intel spec
266.66MHz spread, no Intel spec
2.4993
2.9991
3.7489
TPERIOD
Average Period(3)
200MHz spread
4.9985
—
5.0266
ns
166.66MHz spread
133.33MHz spread
100MHz spread
5.9982
7.4978
9.997
175
—
—
—
—
6.032
7.54
10.0533
700
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
ps
ps
ps
ps
%
ps
ps
Fall Time(2)
VOL = 0.175V, VOH = 0.525V
175
—
—
45
—
—
—
—
—
—
700
125
125
55
d-tR
Rise Time Variation(2)
Fall Time Variation(2)
Duty Cycle(2)
d-tF
dT3
Measurement from differential waveform
VT = 50%
(2)
tSK3
Skew
—
—
100
85
tJCYC-CYC
Jitter, Cycle to Cycle(2)
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
16
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
ELECTRICALCHARACTERISTICS-3V66
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
Min.
-300
2.4
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
—
Unit
ppm
V
(1,2)
ppm
LongAccuracy
See Tperiod Min. - Max. values
IOH = -1mA
VOH
OutputHIGHVoltage
OutputLOWVoltage
ClockPeriod(2)
VOL
IOL = 1mA
—
0.55
15.0045
15.0799
—
V
TPERIOD
66MHzoutputnominal
66MHzoutputspread
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Rising/Fallingedgerate
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
14.9955
14.9955
-33
ns
IOH
IOL
Output HIGH Current
OutputLOWCurrent
mA
mA
—
-33
30
—
—
38
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
ns
tR1
tF1
0.5
2
0.5
2
ns
(1)
tSK1
dT1
Skew
—
250
55
ps
Duty Cycle(1)
VT = 1.5V
45
%
(1)
tJCYC-CYC
Jitter
VT = 1.5V, 3V66
—
250
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
30.009
30.1598
—
Unit
ppm
ns
(1,2)
ppm
LongAccuracy
ClockPeriod(2)
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
0.5
0.5
45
2
2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
250
ps
(1)
tJCYC-CYC
Jitter
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
17
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS, 48MHZ, USBANDVCH
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
20.8271
2.4
—
-33
—
30
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.8396
—
Unit
ppm
ns
(1,2)
ppm
LongAccuracy
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
mA
-33
—
IOL
OutputLOWCurrent
mA
—
1
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
2
V/ns
V/ns
ns
Fallingedgerate
1
2
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
1
2
1
2
ns
dT1
Duty Cycle(1)
45
55
%
(1)
tJCYC-CYC
Jitter
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS,DOT48MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.8396
—
Unit
ppm
ns
(1,2)
ppm
LongAccuracy
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
20.8271
2.4
—
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
2
4
V/ns
V/ns
ns
Fallingedgerate
2
4
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
0.5
0.5
45
1
1
ns
dT1
Duty Cycle(1)
55
%
(1)
tJCYC-CYC
NOTES:
Jitter
—
350
ps
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
18
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
PD#, POWER DOWN
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low
beforeturningofftheVCO.InPD#de-assertionallclockswillstartwithoutglitches.
PWRDWN#
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
3V66
66MHz
Low
REF
14.318MHz
Low
1
0
IREF * 2 or float
IREF * 2 or float
PD#ASSERTION
PD#shouldbe sampledlowbytwoconsecutive CPU#risingedges before stoppingclocks.Allsingle-endedclocks willbe heldlowontheirnexthighto
lowtransition. Alldifferentialclockswillbeheldhighonthenexthightolowtransitionofthecomplimentaryclock.Ifthecontrolregisterdeterminingtodrive
modeissetto‘tri-state’,thedifferentialpairwillbestoppedintri-statemode,undriven. WhenthedrivemodebutcorrespondingtotheCPUorSRCclockof
interestis setto‘0’thetrueclockwillbedrivenhighat2xIREF andthecomplementaryclockwillbetristated.Ifthecontrolregisteris programmedto‘1’both
clockswillbetristated.
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
19
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
COMMERCIALTEMPERATURERANGE
PD#DE-ASSERTION
Thetimefromthede-assertionofPD#oruntilpowersupplyrampstogetstableclockswillbelessthan1.8ms.IfthedrivemodecontrolbitforPD#tristate
isprogrammedto‘1’thestoppeddifferentialpairmustfirstbedrivenhightoaminimumof200mVinlessthan300µs ofPD#deassertion.
tSTABLE <1.8mS
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN#
<300μS, <200mV
NPROGRAMMINGJITTERMEASUREMENT
Tested on IDT test board, 10" trace, 10pF loading.
MeasuredatCPU0,differentialactiveprobe.
Data showed may vary due to CMOS process.
133MHzMODE
N =
100MHzMODE
N =
OutputFreq. (MHz)
CPUJitter(ps)
OutputFreq. (MHz)
CPUJitter(ps)
200h (512)
153
229
306
76
79
72
200h (512)
115
172
229
80
51
65
300h (768)
300h (768)
3FFh (1023)
3FFh (1023)
166MHzMODE
N =
200MHzMODE
N =
OutputFreq. (MHz)
CPUJitter(ps)
OutputFreq. (MHz)
CPUJitter(ps)
200h (512)
204
305
407
71
72
92
200h (512)
229
344
458
68
84
82
300h (768)
300h (768)
3FFh (1023)
3FFh (1023)
20
IDTCV107E
COMMERCIALTEMPERATURERANGE
CLOCKGENERATORFORDESKTOPPCPLATFORMS
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
Commercial Temperature Range
(0°C to +70°C)
Blank
Small Shrink Outline Package
PV
Clock Generator for Desktop PC Platforms
107E
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
logichelp@idt.com
21
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