IDTCV115C [IDT]
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR; 可编程FLEXPC时钟P4处理器
| 型号： | IDTCV115C |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| 文件： | 总19页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDTCV115C
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
DESCRIPTION:
FEATURES:
IDTCV115C is a 56 pin clock device, complying the latest Intel CK410
requirements, for Intel advance P4 processors. The CPU output buffer is
designedtosupportupto400MHzprocessor. OnededicatedPLLforSerial
ATA clock provides high accuracy frequency. This device also implements
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential
outputs,whichcanprovidemorerobustsystemperformance.
• One high precision N and SSC programmable PLL for SRC/PCI
• One high precision N and SSC programmable PLL for CPU
• One high precision SSC programmable PLL for SATA
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support multiple spread spectrum modulation, down and
center
EachCPU/SRC/PCI,SATAclockhasitsownSpreadSpectrumselection,
whichallowsforisolatedchangesinsteadofaffecting otherclockgroups.
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, and USB48MHz
• Available in SSOP package
KEYSPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONALBLOCKDIAGRAM
SATA PLL
SCC
SRC4 - SATA
SATA/
Programmable
PCI[4:0], PCIF[2:0]
PCI/
PCIEX PLL
SCC
N Programmable
14.318MHz
Osc
PCIE/
Host/
SRC[6:5] [3:1]
CPU_ITP/
SRC7
MUX
CPU PLL
SCC
N Programmable
CPU[1:0]
USB48
48MHz/
96MHz/
Fixed PLL
No SCC
DOT96
OUTPUTTABLE
CPU
CPU_ITP/SRC
SRC
SATA
PCI/PCIF
REF
DOT96
48MHz
2
1
5
1
8
1
1
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC - 6520/10
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
TESTMODESELECT(1)
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW
Pin38
(test_mode)
VDD_PCI
VSS_PCI
PCI2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI1
CPU
REF/N
Hi-Z
SRC
REF/N REF/N REF REF/N REF/N
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
PCI/F REF DOT96
USB
2
PCI0
1
0
3
FS_A
VDD_suspend
PCI3
4
NOTE:
PCI4
5
REF0
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N.
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
6
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SCL*
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCIF2
VDD_48
ITP_EN
SDA*
USB48MHz
VSS_48
CPUT0
CPUC0
VDD_CPU
ITP_EN
pin 38
CPUC2_ITP
SRCC7
pin 39
CPUT_ITP
SRCT7
1
0
DOT_96
DOT_96#
CPUT1
**VTT_PWRGD#/PWRDWN
CPUC1
VSS_CPU
SRCT1
SRCC1
IREF
VDD_SRC
FS_B/Test_Mode
FS_C/Test _Sel
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
VDD_SRC
VSS
SRCT2
SRCC2
SRCT3
SRCC3
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
VSS_GND
SRCT4_SATA
SRCC4_SATA
VDD_SRC
* = ~ 130KΩ internal pull-up.
** = ~ 130KΩ internal pull-down.
SSOP
TOP VIEW
HWFREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC4_SATA
SRC[3:1],SCR[7:5]
PCI
USB
48
DOT
96
REF
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
48
96
011
166
48
96
010
200
48
96
000
266
48
96
100
333
48
96
110
400
48
96
111
Reserve
48
96
2
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Number
Name
VDD_PCI
VSS_PCI
PCI2
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/0
Description
1
2
3.3V
GND
3
PCI clock
PCI clock
PCI clock
GND
4
PCI3
5
PCI4
6
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
7
3.3V
8
PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD# assertion), HIGH = CPU_2.
9
OUT
OUT
PWR
OUT
GND
OUT
OUT
I/O
PCI clock,
10
11
12
13
14
15
16
PCIF2
PCI clock,
VDD_48
3.3V
USB48
48MHz clock
VSS_48
GND
DOT_96T
DOT_96C
**VTT_PWRGD#/PWRDWN
96MHz0.7Vcurrentmodedifferentialclockoutput
96MHz0.7Vcurrentmodedifferentialclockoutput
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_ENinputs. AfterVTT_PWRGD# assertion, becomesareal-timeinputforassertingpower
down (active high). Internal pull LOW.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SRCT1
SRCC1
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
I/O
DifferentialSerialreferenceclock
DifferentialSerialreferenceclock
VDD_SRC
VSS
3.3V
GND
SRCT2
DifferentialSerialreferenceclock
SRCC2
DifferentialSerialreferenceclock
SRCT3
DifferentialSerialreferenceclock
SRCC3
DifferentialSerialreferenceclock
VSS
GND
SRCT4_SATA
SRCC4_SATA
VDD_SRC
VSS_SRC
SRCC5
SATA clock
SATA clock
3.3V
GND
DifferentialSerialreferenceclock
SRCT5
DifferentialSerialreferenceclock
SRCC6
DifferentialSerialreferenceclock
SRCT6
DifferentialSerialreferenceclock
VDD_SRC
CPUC2_ITP/ SRCC7
CPUT2_ITP/ SRCT7
FS_C/Test_Sel
FS_B/Test_Mode
IREF
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7
Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7
CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted.
CPU frequency selection. In test mode, 1=Hi-Z, 0=REF/N.
Referencecurrentfordifferentialoutputbuffer
I/O
OUT
GND
OUT
OUT
PWR
OUT
OUT
I/O
VSS
GND
CPUC1
Host0.7Vcurrentmodedifferentialclockoutput
Host0.7Vcurrentmodedifferentialclockoutput
3.3V
CPUT1
VDD_CPU
CPUC0
Host0.7Vcurrentmodedifferentialclockoutput
Host0.7Vcurrentmodedifferentialclockoutput
SMBus data
CPUT0
*SDA
3
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Pin Number
Name
Type
Description
47
48
49
50
51
52
53
*SCL
VDD_REF
XTAL_OUT
XTAL_IN
VSS_REF
REF0
IN
SMBus CLK
PWR
OUT
IN
3.3V
Xtaloutput
Xtalinput
GND
OUT
PWR
GND
14.318MHzreferenceclockoutput
VDD_Suspend
In thepowerdownmode, supply3.3VtoSMcontrolregisters, <1mA. Inthenormaloperation, regular
VDD.
54
55
56
FS_A
PCI0
PCI1
IN
CPU frequency selection
PCI clock
OUT
OUT
PCI clock
SMPROTOCOL
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N, (0 is not valid
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
11-18
19
29-36
37
20
21-28
29
D3h
38-45
46
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Byte count, N (block read back of N
bytes), Byte 8
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Setting bit[11:18] = starting address. After reading back the first data byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0]
Multiple loads
Single loads
USB48
00
01
10
11
2L
1H
1L
Recommend
Recommend
Recommend
Recommend
2H
Recommend
Recommend
SSCMAGNITUDECONTROL, SMC
PCI
When Byte5 bit6 = 0; otherwise, PCI = SRC frequency/3
SMC[2:0]
000
%
OFF
PCIS[1:0]
PCI
001
-0.25
- 0.5
00
01
10
11
33.33
36.36
40
010
011
±0.125
±0.25
±0.375
±0.5
100
101
110
111
±0.75
S_CBS[1:0], H_CBS[1:0] BAND
SELECTION
S_CNS, S_PNS, H_CNS,H_PNS N
SELECTION
S_CBS/H_CBS[1:0]
NS[1:0]
00
01
10
11
FS[C,B,A]
00
01
10
11
Standard of Each CPU Mode (Band)
N Selection 1
CB1_[2:0], byte17, CPU PLL Mode selection1
CB2_[2:0], byte17, CPU PLL Mode selection2
Don’tcare
N Selection 2
Don’tcare
RESOLUTION
CB1[2:0]. CB2[2:0], CPU MODE
SELECTION
N Resolution (MHz)
0.666667
%
N=
150
150
125
150
100
125
150
150
CPU = 100MHz mode
CPU = 133MHz mode
CPU = 166MHz mode
CPU = 200MHz mode
CPU = 266MHz mode
CPU = 333MHz mode
CPU = 400MHz mode
SRC (PCI Express)
0.67%
0.67%
0.8%
CB[2:0]
101
CPU Mode, MHz
0.888889
100
133
1.333333
001
1.333333
0.67%
1.00%
0.8%
011
166
2.666667
010
200
2.666667
000
266
2.666667
0.67%
0.67%
100
333
0.666667
110
400
111
Reserve
5
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPUT2, CPUC2/
SRCT7, SRCC7
Outputenable
Tristate
Enable
RW
1
6
5
4
3
2
1
0
SRCT6, SRCC6
SRCT5, SRCC5
SRCT4, SRCC4 (SATA)
SRCT3, SRCC3
SRCT2, SRCC2
SRCT1, SRCC1
REF0 2x drive
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
2x drive enable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1x
Enable
Enable
Enable
Enable
Enable
Enable
2x
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
Recommended
7
6
5
4
3
2
1
0
DOT96T,DOT96C
Reserve
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
0
1
1
1
0
0
0
USB48
Reserve
REF0
CPUT1, CPUC1
CPUT0, CPUC0
Reserve
0
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCI4
PCI3
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PCI2
PCI1
PCI0
PCIF2
PCIF1
PCIF0
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
FSC latched value on power up
FSB latched value on power up
FSA latched value on power up
SRCT PWRDWN drive mode
CPUT2 PWRDWN drive mode
CPUT1 PWRDWN drive mode
CPUT0 PWRDWN drive mode
DOT96 PWRDWN drive mode
R
R
R
SRCT[7:1]
CPUT2
CPUT1
CPUT0
DOT96T
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristate
RW
RW
RW
RW
RW
0
0
0
0
0
6
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCIFStr1
PCIFStr0
PCIStr1
PCIFstrengthselection
see SE Clock Strength table
PCIstrengthselection
0
0
0
1
0
0
1
1
PCIStr0
see SE Clock Strength table
REFstrengthselection
REFStr1
REFStr0
48MHStr1
48MHzStr0
see SE Clock Strength table
USB48MHz0strengthselection
see SE Clock Strength table
BYTE 5
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
PCIPLLS
PCIS1
PCI PLL select
SATA PLL
PCI EX PLL
RW
0
See PCIS table, only valid when
Byte5 bit 6 = 0 See PCIS Table
RW
RW
RW
0
0
1
4
3
PCIS0
SMcontrolregisters
contents Power Down
mode
During the Power Down
ResetSMtodefault
SM contents have
no change
2
1
0
SATA_SMC2
SATA_SMC1
SATA_SMC0
SATAPLLspreadspectrum
magnitudecontrolselect
see SMC table
RW
RW
RW
0
1
0
BYTE 6
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
WDHRB
Hard Alarm read back,
reset by WD disable
R
6
5
WDSRB
Soft Alarm read back,
rest by WD disable
R
SRC_SMC2
SRC(PCIEXpress)
PLLspreadspectrummagnitude
controlselect
RW
0
1
4
SRC_SMC1
RW
see SMC table
3
2
1
0
SRC_SMC0
CPU_SMC2
CPU_SMC1
CPU_SMC0
RW
RW
RW
RW
0
1
0
0
CPU PLL spread spectrum
controlmagnitudeselect
see SMC table
7
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
0
0
0
0
0
1
0
1
BYTE 8
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
BYTES 9 - 16 ARE DUMMY BITES
BYTE17
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CB1_2
CB1_1
CB1_0
CPU PLL Mode Selection 1
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
See CPU Mode Selection table
CB2_2
CB2_1
CPU PLL Mode Selection 2
0
0
0
0
See CPU Mode Selection table
CB2_0
CN1_8, MSB
CPU PLL N selection 1
BYTE18
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN1_7
CN1_6
CPU PLL N selection 1
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
CN1_5
CN1_4
CN1_3
CN1_2
CN1_1
CN1_0, LSB
8
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE19
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN2_8, MSB
CN2_7
CPU N selection 2
0
1
0
0
1
0
1
1
CN2_6
CN2_5
CN2_4
CN2_3
CN2_2
CN2_1
BYTE20
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CN2_0, LSB
CPU N selection 2
0
PN1_8, MSB
PN1_7
RW
RW
0
1
BYTE21
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
PN1_6
SRC PLL (PCI Express)
N Selection 1
RW
0
6
5
4
3
2
1
0
PN1_5
PN1_4
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
1
0
0
PN1_3
PN1_2
PN1_1
PN1_0, LSB
PN2_8, MSB
BYTE22
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
PN2_7
SRC PLL (PCI Express)
N Selection 2
RW
1
6
5
4
3
2
1
0
PN2_6
PN2_5
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
1
1
0
PN2_4
PN2_3
PN2_2
PN2_1
PN2_0, LSB
9
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE23
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
S_CBS1
Soft Alarm CPU PLL mode
select, see S_CBS Band
RW
0
6
5
4
3
S_CBS0
S_CNS1
S_CNS0
S_PNS1
SelectionTable
RW
RW
RW
RW
0
0
0
0
Soft Alarm CPU PLL N select,
see S_CNS N Selection Table
Soft Alarm SRC PLL (PCI
Express) N select,
2
1
0
S_PNS0
see S_PNS N Selection Table
RW
0
BYTE24
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
H_CBS1
H_CBS0
H_CNS2
H_CNS0
H_PNS1
Hard Alarm CPU PLL mode select,
see H_CBS Band Selection Table
Hard Alarm CPU PLL N select,
see H_CNS N Selection Table
Hard Alarm SRC PLL
RW
RW
RW
RW
RW
0
0
0
0
0
(PCI Express) N select,
2
1
0
H_PNS0
see H_PNS N selection table
RW
0
BYTE25
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
WD Timer 7
WD Timer 6
WD Timer 5
WD Timer 4
WD Timer 3
WD Timer 2
WD Timer 1
WD Timer 0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
0
1
1
Watchdogtimer
Defaultis11*290ms
Hard Alarm = WD timer * 290ms
BYTE26
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
SoftTimer3
SoftTimer2
SoftTimer1
SoftTimer0
0
0
0
1
SoftAlarmtimer
Soft Alarm = Soft timer * 290ms
10
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
BYTE27
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
WatchDogEnable
WatchDogEnable
Disable
Enable
RW
0
SoftAlarmEnable
Reserved
SoftAlarmEnable
Hard Alarm Enable
Disable
Disable
Disable
Enable
Enable
Relatch
RW
RW
RW
RW
RW
0
0
0
0
0
Hard Alarm Enable
Reserved
Hard Alarm FS
RelatchEnable
Reserved
Relatch FS[C, B, A]
at Hard Alarm
0
RW
0
BYTE 42, 43 SRC SPREAD MAGNITUDE(1)
BYTE 44 SRC SPREAD CENTER(1)
BYTE38 SRCSPREADCONTROLSWITCH(FROMBYTE6TOBYTES42,43,44)(1)
NOTE:
1. Contact IDT for detailed application note.
11
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PLLFREQUENCYPROGRAMMINGPROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may
enable either one or both of the alarms.
User presets the CPU PLL Mode and N, and SRC PLL N value:
1. Set CPU PLL Mode, CB1 and CB2, byte 17
2. Set CPU PLL N, CN1 and CN2, byte 18 and byte 19
3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte 21, 22
UserselectsthefrequencyforSoftAlarmandHardAlarm, ifenabledrespectively:
4. SelectSoftAlarmfrequency,byte23
5. Select Hard Alarm frequency, byte 24
UsersetstheTimerandenablestheWDcircuitforfrequencyswitch:
6. Set Hard Alarm Timer, byte 25
7. SetSoftAlarmTimer, byte26
8. Enable Soft and Hard Alarm, byte 27
9. Enable Watch Dog (WDE), byte 27
•
•
WDEDisableresetsWDSRBandWDHRB.
PCI CLK is selectable from SRC PLL or SATA PLL, byte 5 bit 6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI
is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte 5 bit[5:4].
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
If Hard Alarm Enabled (byte 27):
Set WDHRB (byte 6)
If Soft Alarm Enabled (byte 27):
Set WDSRB (byte 6)
Trigger Watch Dog Circuit
Load CPU N and Band selections into PCU PLL
Load SRC N selections into SRC PLL
Load CPU N and Mode
selections into PCU PLL
Load SRC N selection
into SRC PLL
If Hard Alarm Relatch Enabled:
Latch FSC, B, A
12
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
VSS - 0.3
0.7
VSS - 0.3
–5
—
0.8
V
VIH_FS
VIL_FS
IIL
FS Input HIGH Voltage
FS Input LOW Voltage
Input LeakageCurrent
Operating Supply Current
Powerdown Current
For FSA,B,C and Test_Mode
For FSA,B,C and Test_Mode
0< VIN < VDD, no internal pull-up or pull-down
Full active, CL = full load
—
VDD + 0.3
V
—
0.35
+5
400
70
12
—
7
V
—
mA
mA
mA
IDD3.3OP
IDD3.3PD
—
—
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
—
—
—
—
FI
Input Frequency(1)
Pin Inductance(2)
—
14.31818
—
MHz
nH
LPIN
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Output pin capacitance
—
—
6
pF
X1 and X2 pins
—
—
5
Clock Stabilization(2,3)
Modulation Frequency(2)
TDRIVE_SRC(2)
From VDD power-up or de-assertion of PD# to first clock
Triangular modulation
—
—
1.8
33
15
300
5
ms
KHz
ns
30
—
SRC output enable after PCI_Stop# de-assertion
CPU output enable after PD# de-assertion
Fall time of PD#
—
—
TDRIVE_PD#(2)
—
—
us
TFALL_PD#(2)
—
—
ns
TRISE_PD#(3)
Rise time of PD#
—
—
5
ns
TDRIVE_CPU_Stop#(2)
TFALL_CPU_Stop#(2)
TRISE_CPU_Stop#(3)
CPU output enable after CPU_Stop# de-assertion
Fall time of PD#
—
—
10
5
us
—
—
ns
Rise time of PD#
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
13
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
Voltage HIGH(2)
Voltage LOW(2)
IOH = -1mA
IOL = 1mA
—
—
V
—
—
0.4
V
VHIGH
VLOW
VOVS
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
—
850
150
1150
—
mV
—
Max Voltage(2)
Measurement on single-ended signal using absolute value
—
mV
VUDS
Min Voltage(2)
–300
250
—
—
VCROSS(ABS) Crossing Voltage (abs)(2)
—
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Long Accuracy(2,3)
Variation of crossing over all edges
—
See TPERIOD Min. - Max. values
400MHz nominal/spread
–300
—
—
—
—
300
2.4993
2.9991
3.7489
2.5008
3.0009
3.7511
333.33MHz nominal/spread
266.66MHz nominal/spread
TPERIOD
Average Period(3)
200MHz nominal/spread
4.9985
—
5.0015
ns
166.66MHz nominal/spread
133.33MHz nominal/spread
100MHz nominal/spread
5.9982
7.4978
9.997
—
—
—
6.0018
7.5023
10.003
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
—
—
—
200MHz nominal/spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
166.66MHz nominal/spread
ns
133.33MHz nominal/spread
100MHz nominal/spread
7.4128
9.912
—
—
—
—
96MHz nominal
10.1635
175
175
—
—
—
—
—
—
—
—
—
—
700
700
125
125
55
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
ps
ps
ps
ps
%
Fall Time(2)
d-tR
Rise Time Variation(2)
Fall Time Variation(2)
Duty Cycle(2)
d-tF
—
dT3
Measurement from differential waveform
VT = 50%
45
tSK3
Skew(2)
—
100
85
ps
ps
tJCYC-CYC
NOTES:
Jitter, Cycle to Cycle(2)
Measurement from differential waveform
—
1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
30.009
30.1598
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
Duty Cycle(1)
Skew(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
0.5
0.5
45
2
2
ns
dT1
55
%
tSK1
VT = 1.5V
—
500
250
ps
tJCYC-CYC
Jitter(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.834
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
—
20.8257
2.4
—
TPERIOD
VOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
2
V/ns
V/ns
ns
Fallingedgerate
1
2
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
1
2
1
2
ns
dT1
Duty Cycle(1)
45
55
%
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
15
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
300
69.855
—
Unit
ppm
ns
ppm
LongAccuracy(1)
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
Clock Period
69.827
2.4
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current(1)
OutputLOWCurrent(1)
RiseTime(1)
V
VOL
IOL = 1mA
0.4
-33
38
V
IOH
VOH at Min. = 1V, VOH at Max. = 3.135V
VOL at Min. = 1.95V, VOL at Max. = 0.4V
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
-33
30
mA
mA
ns
IOL
tR1
1
2
tF1
FallTime(1)
1
2
ns
tSK1
Skew(1)
—
500
55
ps
dT1
Duty Cycle(1)
VT = 1.5V
45
%
tJCYC-CYC
Jitter(1)
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
16
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighallclockswillbedrivenlowbefore
turningofftheVCO.InPDde-assertionallclockswillstartwithoutglitches.
PWRDWN
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
0
1
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
17
IDTCV115C
PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PDDE-ASSERTION
tSTABLE <1.8mS
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN
<300µS, <200mV
18
IDTCV115C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR
ORDERINGINFORMATION
IDTCV XXX
Device Type
XX
X
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
Small Shrink Outline Package
SSOP - Green
PV
PVG
Programmable FlexPC™ Clock for P4 Processor
115C
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
logichelp@idt.com
(408) 654-6459
19
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