IDTQS5LV919-133J [IDT]
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | IDTQS5LV919-133J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
QS5LV919
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION:
• 3.3V operation
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and
design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
• JEDEC compatible LVTTL level outputs
• Clock inputs are 5V tolerant
• < 300ps output skew, Q0–Q4
• 2xQ output, Q outputs, Q output, Q/2 output
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Functional equivalent to MC88LV915, IDT74FCT388915
• Positive or negative edge synchronization (PE)
• Balanced drive outputs ±24mA
• 160MHz maximum frequency (2xQ output)
• Available in QSOP and PLCC packages
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONALBLOCKDIAGRAM
REF_SEL
FEEDBACK
PLL_EN
FREQ_SEL
LOCK
PE
0
1
SYNC0
SYNC1
0
1
1
0
PHASE
LOOP
FILTER
VCO
/2
DETECTOR
OE/RST
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q5
Q/2
Q4
Q3
Q2
Q1
Q0
2xQ
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
FEBRUARY 2006
1
c
2006 Integrated Device Technology, Inc.
DSC-5820/7
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PINCONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
1
Q4
GND
Q5
2
3
4
VDD
4
3
2
1
28 27 26
VDD
2xQ
Q/2
25 Q/2
FEEDBACK
REF_SEL
SYNC0
AVDD
5
OE/RST
FEEDBACK
REF_SEL
SYNC0
GND
24
23
22
21
20
19
6
GND
Q3
5
6
7
8
9
Q3
7
VDD
Q2
VDD
Q2
8
AVDD
PE
PE
9
GND
10
11
GND
LOCK
AGND
LOCK
PLL_EN
GND
10
11
AGND
SYNC1
SYNC1
12 13 14 15 16 17 18
17
16
15
FREQ_SEL
GND
12
13
14
Q1
VDD
Q0
PLCC
QSOP
TOP VIEW
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating
Max.
–0.5to+7
–0.5to+5.5
655
Unit
V
VDD, AVDD SupplyVoltagetoGround
DCInputVoltage VIN
V
Maximum Power
QSOP
mW
mW
° C
Dissipation(TA =85°C) PLCC
StorageTemperatureRange
770
TSTG
NOTE:
–65to+150
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE(TA = 25°C, f = 1MHz, VIN = 0V)
QSOP
PLCC
Parameter
Typ.
Max.
Typ.
Max.
Unit
CIN
3
4
4
6
pF
2
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PINDESCRIPTION
Pin Name
SYNC0
I/O
Description
I
I
I
I
I
Referenceclockinput
SYNC1
Referenceclockinput
REF_SEL
FREQ_SEL
FEEDBACK
Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.
VCOfrequencyselect.ForchoosingoptimalVCOoperatingfrequencydependingoninputfrequency.
PLLfeedbackinputwhichisconnectedtoauserselectedoutputpin.Externalfeedbackprovidesflexibilityfordifferent
outputfrequencyrelationships.SeetheFrequencySelectionTableformoreinformation.
Clockoutputs
Q0 -Q4
Q5
O
O
O
O
O
Clockoutput.Matchedinfrequency,butinvertedwithrespecttoQ.
Clockoutput.Matchedinphase,butfrequencyisdoubletheQfrequency.
Clockoutput.Matchedinphase,butfrequencyis halftheQfrequency.
PLLlockindicationsignal.1indicatespositivelock.0indicatesthatthePLLisnotlockedandoutputsmaynotbe
synchronizedtotheinputs.
2xQ
Q/2
LOCK
OE/RST
I
Outputenable/asynchronousreset.Resetsalloutputregisters.When0,alloutputsareheldinatri-statedcondition.When
1,outputsareenabled.
PLL_EN
I
I
PLLenable.EnablesanddisablesthePLL.Usefulfortestingpurposes.
When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with
the negative edge of SYNC.
PE
VDD
AVDD
GND
AGND
—
—
—
—
Powersupplyforoutputbuffers.
Powersupplyforphaselockloopandotherinternalcircuitries.
Groundsupplyforoutputbuffers.
Groundsupplyforphaselockloopandotherinternalcircuitries.
OUTPUTFREQUENCYSPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD / VDD = 3.3V ± 0.3V
Symbol
FMAX_2XQ
FMAX_Q
Description
–55
55
–70
70
–100
100
50
–133
133
66.5
33.25
20
–160
160
80
Units
MHz
MHz
MHz
MHz
M H z
MHz
Max Frequency, 2xQ
Max Frequency, Q0 - Q4, Q5
Max Frequency, Q/2
Min Frequency, 2xQ
Min Frequency, Q0 - Q4, Q5
Min Frequency, Q/2
27.5
13.75
20
35
FMAX_Q/2
FMIN_2XQ
FMIN_Q
17.5
20
25
40
20
20
10
10
10
10
10
FMIN_Q/2
5
5
5
5
5
3
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
FREQUENCYSELECTIONTABLE
SYNC (MHz)
Output Used for
Feedback
Q/2
(allowablerange)(1)
OutputFrequencyRelationships(2)
FREQ_SEL
HIGH
HIGH
HIGH
HIGH
LOW
Min.
Max
FMAX_Q/2
FMAX_Q
Q/2
Q5
Q0 - Q4
SYNC X 2
SYNC
2XQ
FMIN_Q/2
FMIN_Q
SYNC
– SYNC X 2
– SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
Q0 -Q4
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
Q5
FMIN_Q
FMAX_Q
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
(3)
2xQ
FMIN_2XQ
FMIN_Q/2/2
FMIN_Q /2
FMIN_Q /2
FMIN_2XQ /2
100
– SYNC / 2
– SYNC X 2
– SYNC
Q/2
Q0 -Q4
Q5
FMAX_Q/2/2
FMAX_Q /2
FMAX_Q /2
FMAX_2XQ /2
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
LOW
SYNC / 2
– SYNC / 2
SYNC / 4
LOW
SYNC
– SYNC
SYNC / 2
LOW
2xQ
– SYNC / 2
NOTES:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with Sync inputs outside
specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
3. The 2xQ is limited to a maximum frequency (FMAX_2XQ) of 100MHz only when used as a feedback.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified
Industrial:TA = -40°C to +85°C, AVDD/VDD= 3.3V ± 0.3V
Symbol
VIH
Parameter
Input HIGH Voltage
InputLOWVoltage
OutputHIGHVoltage
Conditions
GuaranteedLogicHIGHLevel
GuaranteedLogicLOWLevel
IOH = −24mA
Min.
Typ.
—
—
—
—
—
—
100
—
—
—
Max.
—
Unit
V
2
—
VIL
0.8
V
VOH
VDD– 0.6
VDD– 0.2
—
—
V
IOH = −100μA
—
VOL
OutputLOWVoltage
VDD = Min., IOL = 24mA
VDD = Min., IOL = 100μA
—
0.45
0.2
V
—
VH
IOZ
IIN
InputHysteresis
—
—
mV
μA
μA
μA
OutputLeakageCurrent
InputLeakageCurrent
InputPull-DownCurrent(PE)
VOUT = VDD or GND, VDD = Max.
AVDD = Max., VIN = AVDD or GND
AVDD = Max., VIN = AVDD
—
± 5
± 5
± 100
—
IPD
—
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
IDDQ
QuiescentPowerSupplyCurrent
VDD = Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
VDD = Max., VIN = 3V
1
mA
ΔIDD
Power Supply Current per Input HIGH
Dynamic Power Supply Current (1)
1
30
μA
IDDD
VDD = Max., CL = 0pF
0.2
0.4
mA/MHz
NOTE:
1. Relative to the frequency of Q outputs.
4
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INPUTTIMINGREQUIREMENTS
Symbol
tR,tF
FI
Description(1)
Min.
—
2.5
2
Max.
3
Unit
ns
Maximum input rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC0, SYNC1(1)
100
—
75
MHz
ns
(2)
tPWC
Input clock pulse, HIGH or LOW
DH
Input duty cycle, SYNC0, SYNC1(2)
25
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and
FREQ_SEL combinations.
2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
tSKR
tSKF
tSKALL
tPW
Parameter(1)
Min.
Max.
Unit
ps
(2)
Output Skew Between Rising Edges, Q0-Q4 (and Q/2 if PE = LOW)
—
300
(2)
Output Skew Between Falling Edges, Q0-Q4 (and Q/2 if PE = HIGH)
Output Skew, All Outputs(2, 5)
—
300
ps
—
500
ps
Pulse Width, 2xQ output, >40MHz
TCY/2 −0.4
TCY/2 −0.4
−0.15
−500
—
TCY/2 + 0.4
ns
tPW
Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz
TCY/2 + 0.4
ns
(4)
tJ
Cycle-to-Cycle Jitter
0.15
0
ns
(6)
tPD
SYNC Input to Feedback Delay
ps
tLOCK
tPZH
tPZL
tPHZ
tPLZ
tR,tF
SYNC to Phase Lock
10
14
ms
ns
(3)
Output Enable Time, OE/RST LOW to HIGH
0
(3)
Output Disable Time, OE/RST HIGH to LOW
0
14
2
ns
ns
Output Rise/Fall Times, 0.8V ∼ 2V
0.3
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. Skew measured at selected synchronization edge.
6. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
5
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
BOARD VCC
DIGITAL
ANALOG VCC
VCC
10μF
Low
0.1μF
High
0.1μF
Freq.
Bypass
Freq.
Bypass
Bypass
DIGITAL
GND
ANALOG GND
BOARD GND
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the QS5LV919 in a normal digital environment.
Figure 1. Recommended Analog Isolation Scheme for the QS5LV919
NOTES:
1. Figure 1 shows an analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation:
a. All analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage
transients.
b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the QS5LV919's sensitivity to voltage
transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the QS5LV919's
digital VCC supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the QS5LV919 additional protection from the power supply and ground plane
transients that can occur in a high frequency, high speed digital system.
2. The bypass capacitors can be ceramic chip capacitors. There should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane.
This will reduce output switching noise caused by the QS5LV919 outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors
should also be tied as close to the QS5LV919 package as possible.
6
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PLLOPERATION
ThePhaseLockedLoop(PLL)circuitincludedintheQS5LV919provides PLLcircuitis toprovide aneffective zeropropagationdelaybetweenthe
for replication of incoming SYNC clock signals. Any manipulation of that outputandinputsignals.Infact,addingdelaycircuitsinthefeedbackpath,
signal, suchas frequencymultiplyingorinversionis performedbydigital ‘propagationdelay’canevenbe negative!Asimplifiedschematicofthe
logicfollowingthe PLL(see the blockdiagram).The keyadvantage ofthe QS5LV919PLL circuit is shown below.
SIMPLIFIEDDIAGRAMOFQS5LV919FEEDBACK
2xQ
Q
Q/2
Q
INPUT
VCO
/2
/2
PHASE
DETECTOR
Thephasedifferencebetweentheoutputandtheinputfrequenciesfeeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize atthe same frequencyas the input.Hence,this is a true negative
feedbackclosedloopsystem.Inmostapplications,theoutputwilloptimally
havezerophaseshiftwithrespecttotheinput.Infact,theinternalloopfilter
onthe QS5LV919typicallyprovides within150ps ofphase shiftbetween
inputandoutput.
Iftheuserwishes tovarythephasedifference(typicallytocompensate
forbackplane delays), this is mosteasilyaccomplishedbyaddingdelay
circuits tothefeedbackpath.Therespectiveoutputusedforfeedbackwill
beadvancedbytheamountofdelayinthefeedbackpath.Allotheroutputs
willretaintheirproperrelationships tothatoutput.
7
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
ThefrequencyrelationshipshownhereisapplicabletoallQoutputs(Q0,Q1,
50 MHz signal
25 MHz feedback signal
Q2, Q3 and Q4).
HIGH
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Q4
2Q
OE/RST
Q5
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequencywillequaltheSYNCfrequency. TheQ/2 output willalwaysrunat
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
12.5 MHz
signal
Q/2
Q3
Q2
FEEDBACK
LOW
REF_SEL
SYNC(0)
VCC(AN)
PE
25 MHz
input
25 MHz
"Q"
Clock
Outputs
Notethatwith2Qasfeedback,themaximuminputfrequencyis100MHzforFS
= HIGH
QS5LV919
GND(AN)
50 MHz feedback signal
HIGH
FQ_SEL
HIGH
Q0
Q1
PLL_EN
HIGH
Q4
2Q
OE/RST Q5
FEEDBACK
12.5 MHz
input
Q/2
LOW
REF_SEL
SYNC(0)
50 MHz
input
AllowableInputFrequencyRange:
25 MHz
Q3
"Q"
Clock
Outputs
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
QS5LV919
VCC(AN)
PE
Q2
Figure 2b. Wiring Diagram and Frequency Relationships with
Q4 Output Feedback
GND(AN)
FQ_SEL
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Q0
Q1
PLL_EN
HIGH
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always runat2Xthe Q/2frequency, andthe 2Qoutputwillrunat4Xthe Q/2
HIGH
frequency.
50 MHz signal
12.5 MHz feedback signal
AllowableInputFrequencyRange:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
HIGH
Figure 2a. Wiring Diagram and Frequency Relationships with 2Q
Output Feedback
2Q
Q/2
OE/
RST
Q5
Q4
FEEDBACK
REF_SEL
LOW
12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
Q3
Q2
SYNC(0)
VCC(AN)
PE
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
QS5LV919
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency(andtherestofthe"Q"outputs)willequaltheSYNCfrequency. The
Q/2 output willalways runat1/2theQfrequency,andthe2Qoutputwillrun
at2Xthe Qfrequency.
GND(AN)
FQ_SEL
PLL_EN
HIGH
Q0
Q1
HIGH
AllowableInputFrequencyRange:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with
Q2 Output Feedback
8
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
QS5LV919
PLL
2f
CLOCK
@f
SYSTEM
CLOCK
SOURCE
CMMU
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
QS5LV919
PLL
2f
CMMU
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
QS5LV919
PLL
MEMORY
CONTROL
2f
MEMORY
CARDS
CLOCK @2f
at point of use
Figure 3. Multiprocessing Application Using the QS5LV919 for Frequency Multiplication and Low Board-to-Board skew
QS5LV919 System Level Testing Functionality
Theserelationshipscanbeseenintheblockdiagram. Arecommendedtest
configurationwouldbetouseSYNC0orSYNC1asthetestclockinput,andtie
PLL_ENandREF_SELtogetherandconnectthemtothetestselectlogic.
WhenthePLL_ENpinisLOW,thePLLisbypassedandtheQS5LV919is
inlowfrequency"testmode". Intestmode(withFREQ_SELHIGH),the2Q
outputisinvertedfromtheselectedSYNCinput,andtheQoutputsaredivide-
by-2(negativeedgetriggered)oftheSYNCinput,andtheQ/2outputisdivide-
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-
by-2oftheSYNC,theQoutputsdivide-by-4,andtheQ/2outputdivide-by-8.
Thisfunctionalityisneededsincemostboard-leveltestersrunat1MHzor
below,andtheQS5LV919cannotlockontothatlowofaninputfrequency. In
thetestmodedescribedabove,anytestfrequencytestcanbeused.
9
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TEST LOADS AND WAVEFORMS
VDD
300Ω
100Ω
7.0V
OUTPUT
OUTPUT
300Ω
30pF
100Ω
TEST CIRCUIT 1
TEST CIRCUIT 2
1.0ns
1.0ns
tR
tF
3.0V
2.0V
3.0V
2.0V
0.5VDD
0.8V
Vth = 0.5VDD
0.8V
tPW
0V
0V
LVTTL INPUT TEST WAVEFORM
LVTTL OUTPUT WAVEFORM
ENABLE
DISABLE
3V
0.5VDD
0V
CONTROL
INPUT
tPLZ
tPZL
OUTPUT
NORMALLY
LOW
3.0V
VOL
SWITCH
CLOSED
0.5VDD
0.3V
0.3V
tPHZ
tPZH
VOH
SWITCH
OPEN
0.5VDD
OUTPUT
NORMALLY
HIGH
0V
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
10
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TIMING DIAGRAM
SYNC
tPD
FEEDBACK
tJ
Q
tSKF
Q0-Q4
tSKR
Q/2
2xQ
tSKALL
Q5
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC
input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.
2. All parameters are measured at 0.5VDD.
11
QS5LV919
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
ORDERINGINFORMATION
X
QS
X
XXXX
XX
Package
Device Type
Speed
Process
Industrial (-40°C to +85°C)
Blank
Q
QG
J
Quarter Size Outline Package
QSOP - Green
Plastic Leaded Chip Carrier
JG
PLCC - Green
100
133
160
100MHz Max. Frequency
133MHz Max. Frequency
160MHz Max. Frequency
Low Skew CMOS PLL Clock Driver
with Integrated Loop Filter
5LV919
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
logichelp@idt.com
www.idt.com
12
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IDTQS5LV919-55J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV919-55Q
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28
IDT
IDTQS5LV919-70J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV931-50Q8
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-66Q
PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-66Q8
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-80Q
PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-80Q8
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
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