M2005-01-644.5313 [IDT]
Support Circuit, 1-Func, 9 X 9 MM, SMT-36;
| 型号： | M2005-01-644.5313 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Support Circuit, 1-Func, 9 X 9 MM, SMT-36 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：1116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M2005-01
Micro Networks
An Integrated Circuit Systems Company
Preliminary Specifications
M2005-01
Frequency Translator
DESCRIPTION
The M2005-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator PLL designed for
reference clock frequency translation and jitter
attenuation in a high speed data communications
system. The device is similar to the M2004-01 but
includes a frequency hold-over feature that allows
the output frequency to be maintained in the event
of a disrupted input reference clock. Internal divider
ratios are user selectable, and external loop filter
components allow tailoring of the PLL loop
response.
FEATURES
ABSOLUTE MAX RATINGS
Integrated SAW (surface acoustic wave)
delay line
Inputs, VI :
................................................. -0.5 to VCC+0.5V
Output, VO : ................................................. -0.5 to VCC+0.5V
Supply Voltage, VCC : ......................................................... 4.6 V
Storage Temperature, TSTO :............................ -45°C to +100°C
Output clock frequency up to 700MHz
(Consult factory for available frequencies)
Stresses beyond those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These ratings are stress specifications
only. Functional operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
RMS Jitter <1ps RMS (12kHz-80MHz)
Hold-over error +10ppm max
Single 3.3V supply
Small 9x9mm SMT package includes SAW
device
Ideal for OC-48, SDH-12, 10GbE transmit
clock
ISO 9001
Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
1
M2005-01
Micro Networks
Preliminary Specifications
An Integrated Circuit Systems Company
FUNCTIONAL BLOCK DIAGRAM
complete relationship for the output frequency is
defined as:
The internal PLL will adjust the VCSO output
frequency to be M (feedback divider) divided by P
(input divider) times the selected input reference
clock frequency. Note that the ratio of M/P times
input frequency must be such that it falls within the
“lock” range of the VCSO. The M divider (17-bits)
can be programmed for a maximum value of
131,071 and a minimum value of 4. The P divider
(9-bits) can be set to a maximum value of 511 and
a minimum value of 1. The N output divider can be
programmed to divide the VCSO output frequency
by 1, or 4 and provide a 50% output duty cycle.
F VCSO
N
M
N x P
FOUT =
= F REF_CLK x
The N1 input can be hard wired to set the N divider
to a specific state that will automatically occur
during power-up.
Serial operation occurs when S_LOAD is LOW. The
shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of
the shift register are loaded into the M divider and
N output divider when S_LOAD transitions from
LOW to- HIGH. The M divider and N output divide
values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider
and N output divider on each rising edge of
S_CLOCK.
The M2005-01 is serially programmed via a 3 wire
interface. Figure 1 shows the timing diagram for
serial programming.
The relationship between the VCSO frequency, the
M & P dividers, and the input REF_CLK is defined
as follows:
M
P
F VCSO = F REF_CLK x
When the HOLD input is asserted the M2005-01
will revert back to the initial accuracy of the VCSO
and remain at that frequency until the HOLD signal
is returned LOW.
When the N output divider is included, the
R
C
LOOP
R
LOOP
POST
External
C
POST
Loop Filter
Components
C
POST
R
C
LOOP
R
LOOP
POST
M2005-01
OP_IN
nOP_IN OP_OUT
nOP_OUT nVC
VC
Phase
Detector
0
1
MUX
1
SAW Delay Line
R
IN
REF_CLK1
REF_CLK0
Frequency
Hold
0
R
IN
Loop Filter
Amplifier
Phase
Shifter
REF_SEL
VCSO
M Divider
M = 3-1023
FOUT
nFOUT
P Divider
P = 1 or 4
S_DATA
S_CLK
Serial / Parallel
S_LOAD
nP_LOAD
Configuration Register
6
M5:0
P1
HOLD
MR
FIGURE 1
Low Low Null N1 N0 Null Null Null M5 M4 M3 M2
S_DATA
M1 M0
S_CLK
S_LOAD
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456 www.micronetworks.com
2
M2005-01
Micro Networks
An Integrated Circuit Systems Company
Preliminary Specifications
FUNCTIONAL DESCRIPTION
LOOP FILTER
FIGURE 2
Cloop
Rloop
The M2005-01 requires the use of an external loop
filter via the provided filter pins. Due to the
differential design, the implementation requires two
identical RC filters as shown in Figure 2.
Rpost
nVc
OP_IN
Cpost
nOP_OUT
OP_OUT
Cpost
nOP_IN
Vc
Rpost
Rloop
Cloop
TABLE 1. RECOMMENDED LOOP FILTER VALUES
REF_CLK
Frequency
VCSO
Frequency
M
N
FOUT
622.0800MHz
Rloop
5kΩ
Cloop
Rpost
Cpost
19.44MHz
622.0800MHz
32
1
1MF
50kΩ
100pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
3
M2005-01
Micro Networks
Preliminary Specifications
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
Configuration
TABLE 2
Pin Number
1, 2, 3
Name
I/O
GND
Analog I/O
nOP_OUT, OP_OUT Analog I/O
Description
Power Supply Ground
GND
OP_IN, nOP_IN
4, 9
Used for external loop filter. See Figure 2.
Used for external loop filter. See Figure 2
VCSO Differential Control Voltage Input Pair
Power Supply Ground
5, 8
6, 7
nVC, VC
GND
Input
GND
Power
Input
10, 14, 26
11, 19, 22, 33
12
Vcc
Positive Supply Pins
HOLD
Pull - down
Pull - down
When HIGH the device operates in digital HOLD
mode. LVCMOS / LVTTL interface levels.
Determines the output divider value as
defined in Table 3C. LVCMOS / LVTTL
interface levels.
13
N1
Input
15, 16
17
FOUT, nFOUT
MR
Output
Input
Unterminated
Pull - down
Differential output, 3.3V LVPECL levels.
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input
into the shift register on the rising edge of
S_CLOCK.
18
S_CLOCK
Input
Pull - down
20
21
23
24
25
S_DATA
Input
Input
Input
Input
Input
Pull - down
Pull - down
Pull - down
Pull - down
Pull - down
Shift register serial input. Data is sampled on the
rising edge of S_CLOCK.
S_LOAD
Controls transition of data from shift register into
the dividers. LVCMOS / LVTTL interface levels
Input reference clock. LVCMOS / LVTTL interface
levels.
REF_CLK 1
REF_CLK 0
REF_SEL
Input reference clock. LVCMOS / LVTTL interface
levels.
Selects between the different reference clock
inputs as the PLL reference source. See Table
3D. LVCMOS / LVTTL interface levels.
No connection. Internal test pins.
27, 28, 29, 30, 31 N/C
32, 34, 35, 36
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456 www.micronetworks.com
4
M2005-01
Micro Networks
An Integrated Circuit Systems Company
Preliminary Specifications
PIN CHARACTERISTICS
TABLE 4
Symbol
Parameter
Input Capacitance
Test Conditions
Min
Typical
Max
Units
pF
C
4
IN
R
Input Pullup Resistor
Input Pulldown Resistor
51
51
kΩ
PULLUP
R
kΩ
PULLDOWN
PARALLEL & SERIAL MODES FUNCTION
TABLE 5A
Inputs
MR nP_LOAD
M
X
X
N
X
X
S_LOAD S_CLOCK S_DATA
Conditions
Reset, Forces outputs LOW.
H
L
X
H
X
L
X
X
↑
Data
Serial input mode. Shift register is loaded with data
on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M
divider and N output divider.
L
H
X
X
↑
L
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
H
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is
clocked.
Data
Note: L = Low; H = High; X = Don’t care; ↑ = Rising Edge Transition; ↓ = Falling Edge Transition
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
5
M2005-01
Micro Networks
Preliminary Specifications
An Integrated Circuit Systems Company
PARALLEL MODE FUNCTION
SERIAL MODE FUNCTION
TABLE 5C
TABLE 5B
Inputs N Divider Output Frequency (MHz)
Inputs
N1 N2
Value
Min
Max
REF_SEL
Reference
REF_CLK0
0
1
0
0
1
4
311
700
0
1
77.75
175
REF_CLK1
POWER SUPPLY DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
3.465
Units
V
V
Power Supply Voltage
Power Supply Current
3.135
3.3
CC
ICC
162
mA
V = 3.3V ±5%, TA= 0°C to 70°C
CC
LVCMOS/LVTTL DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Units
V
Input High
Voltage
REF_SEL, S_LOAD,
2
VCC + 0.3
V
IH
S_DATA, S_CLOCK, N1, MR
REF_CLK0, REF_CLK1
2
VCC + 0.3
0.8
V
V
V
Input Low
Voltage
REF_SEL, S_LOAD, S_DATA, S_CLOCK,
nP_LOAD, MR
-0.3
IL
REF_CLK0, REF_CLK1
-0.3
1.3
V
I
Input High
Current
N1, MR, S_CLOCK, S_DATA, S_LOAD,
REF_SEL, REF_CLK0, REF_CLK1
N1, MR, S_CLOCK, S_DATA, S_LOAD,
REF_SEL, REF_CLK0, REF_CLK1
V = V = 3.465V
150
µA
IH
DD
IN
I
Input Low
Current
V = 3.465, V = 0V
-5
µA
IL
DD
IN
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
OH
V
0.5
OL
Note 1: Outputs terminated with 50Ω to VCC /2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456 www.micronetworks.com
6
M2005-01
Micro Networks
An Integrated Circuit Systems Company
Preliminary Specifications
LVPECL DC CHARACTERISTICS
Symbol
Parameter
Output High Voltage
Signal
Min
Vcc – 1.4
Vcc – 2.0
0.6
Max
Vcc – 1.0
Vcc – 1.7
0.85
Units
V
FOUT, nFOUT
FOUT, nFOUT
FOUT, nFOUT
V
V
V
OH
V
Output Low Voltage
OL
V
Peak-to-Peak Output Voltage Swing
SWING
Note 1: Output terminated with 50Ω to V –2.V
CC
INPUT FREQUENCY CHARACTERISTICS
Test Conditions
Symbol
Parameter
Min
Max
166
50
Units
MHz
V
F
Input Frequency REF_CLK0, REF_CLK1
S_CLOCK
0.3
IN
Note: Output terminated with 50Ω to V –2.V
CC
AC CHARACTERISTICS
Test Conditions
Symbol
Parameter
Min
Typ
Max
Units
FOUT
Output Frequency
Single Side Band
Phase Noise
77.75
667
MHz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ØNOISE
1kHz offset
-72
-94
10kHz offset
100kHz offset
12kHz to 20 MHz
-123
0.69
50
J (t)
odc
tR
Jitter (RMS)
Output Duty Cycle
Output Rise Time
Setup Time
%
FOUT = 155MHz
M, N, to nP_LOAD
S_DATA to S_CLK
S_CLK to S_LOAD
M, N, to nP_LOAD
S_DATA to S_CLK
S_CLK to S_LOAD
20% to 80%, each
300
5
800
ps
tS
ns
5
ns
5
ns
tH
Hold Time
5
ns
5
ns
5
ns
tLOCK
tPW
PLL Lock Time
1
ms
Output Pulse Width S_LOAD
Initial Frequency Accuracy
in Digital HOLD Mode
TBD
ns
FHOLD
Stable Input Clock
Selected Until Entering
Digital Hold
10
ppm
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
7
M2005-01
Micro Networks
Preliminary Specifications
An Integrated Circuit Systems Company
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL
VCC
nDIFF_CLK
DIFF_CLK
VPP
VCMR
Cross Points
VEE
INPUT AND OUTPUT RISE AND FALL TIME
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456 www.micronetworks.com
8
M2005-01
Micro Networks
An Integrated Circuit Systems Company
Preliminary Specifications
PARAMETER MEASUREMENT INFORMATION
ODC & tPERIOD
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
SETUP AND HOLD TIME
S_DATA
tHOLD
S_CLOCK
S_LOAD
tSET-UP
tSET-UP
M[5:0]
N[1:0]
tHOLD
nP_LOAD
tSET-UP
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
9
M2005-01
Micro Networks
Preliminary Specifications
An Integrated Circuit Systems Company
MECHANICAL DIMENSIONS & PIN CONFIGURATION
.354 [9.0]
.110 [2.8]
#19
#27
#28
#36
#18
#10
.354 [9.0]
ORIENTATION TAB
Pin #1
.025 [0.6]
PIN#
1
DESIGNATION
GND
PIN#
DESIGNATION
S_CLOCK
VDD
.200 [5.1]
18
2
GND
19
3
GND
20
S_DATA
S_LOAD
VDD
4
OP_IN
nOP_OUT
nVC
21
5
22
6
23
REF_CLK1
REF_CLK0
REF_SEL
GND
7
VC
24
8
OP_OUT
nOP_IN
GND
25
9
26
10
11
12
13
14
15
16
17
27
N/C
VDD
28
N/C
.041 [1.0]
HOLD
N1
29
N/C
30
N/C
.007 [0.2]
GND
31
32
N/C
R.006 [R0.2]
FOUT
N/C
nFOUT
MR
33
VDD
34, 35, 36
N/C
1. DIMENSIONS ARE IN INCHES, ( ) ARE IN MM.
ORDERING INFORMATION
Part Number
M2005-01 - 622.0800
Available VCSO Frequencies
622.0800
625.0000
627.3296
644.5313
666.5143
669.1281
669.3266
672.1600
690.5692
693.4830
Series
Model
VCSO Frequency
(i.e. 622.0800MHz)
Micro Networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are
non-infringing on any valid US or foreign patents. Micro Networks assumes no liability as a result of the use
of said specifications and reserves the right to make changes to specifications without notice. Contact your
nearest Micro Networks sales representative office for the latest specifications.
Micro Networks
An Integrated Circuit Systems Company
324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456
European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715
www.micronetworks.com
Rev. 4.1
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