MK3754ATRLF [IDT]

Clock Generator, 54MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8;
MK3754ATRLF
型号: MK3754ATRLF
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Clock Generator, 54MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

时钟 控制器 微控制器 微控制器和处理器 光电二极管 外围集成电路 晶体 时钟发生器
文件: 总4页 (文件大小:59K)
中文:  中文翻译
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MK3754  
Low Cost 54 MHz 3.3 Volt VCXO  
ICR O CLOC K  
Features  
Description  
The MK3754 is ICS/Microclock’s lowest cost, low  
jitter, high performance 3.3 Volt VCXO and PLL  
clock synthesizer designed to replace expensive  
54 MHz VCXOs. The on-chip Voltage Controlled  
Crystal Oscillator accepts a 0 to 3.3 V input voltage  
to vary the output clocks by ±100 ppm. Using  
ICS/Microclock’s patented VCXO and  
analog/digital Phase-Locked Loop (PLL)  
techniques, the device uses an inexpensive external  
13.5 MHz pullable crystal input to produce a  
54 MHz output clock.  
• Packaged in 8 pin SOIC  
• 3.3 V only operating voltage  
• Uses an inexpensive 13.500 MHz external crystal  
• On-chip VCXO (patented) with pull range of  
200ppm (minimum)  
• VCXO tuning voltage of 0 to 3.3 V  
• 12mA output drive capability at TTL levels  
• Advanced, low power, sub-micron CMOS process  
• The A version is the latest, manufactured in a  
smaller geometry process. The MK3754A gives a  
wider pull range than the MK3754S, and so is  
recommended for all new designs, and cost  
reductions of existing designs.  
The MK3754A is a drop-in replacement to the  
earlier MK3754S.  
Block Diagram  
VIN  
X1  
Voltage  
Controlled  
Crystal  
PLL/Clock  
Synthesis  
Circuitry  
13.5 MHz  
pullable  
crystal  
Output  
Buffer  
54MHz  
Oscillator  
X2  
MDS 3754 D  
1
Revision 060100  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com  
MK3754  
Low Cost 54 MHz 3.3 Volt VCXO  
ICR O CLOC K  
Pin Assignment  
MK3754  
1
2
3
4
8
X2  
X1  
7
6
5
GND  
CLK  
VDD  
VDD  
VIN  
GND  
8 pin (150 mil) SOIC  
Pin Descriptions  
Number  
Name  
X1  
Description  
1
2
3
4
5
6
7
8
Crystal connection. Connect to a pullable 13.5 MHz crystal.  
VDD. Connect to +3.3 V.  
VDD  
VIN  
GND  
VDD  
CLK  
GND  
X2  
Voltage input to VCXO. Zero to 3.3V analog input which controls the frequency of the VCXO.  
Connect to ground.  
VDD. Connect to +3.3 V.  
54 MHz clock output.  
Connect to ground.  
Crystal connection. Connect to a pullable 13.5 MHz crystal.  
Pullable Crystal Specifications:  
Correlation (load) Capacitance  
C0/C1  
ESR  
Operating Temperature  
Initial Accuracy  
14 pF  
240 max  
35 Wmax  
0 to 70 °C  
±20 ppm  
Temperature plus Aging Stability  
±50 ppm  
MDS 3754 D  
2
Revision 060100  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com  
MK3754  
Low Cost 54 MHz 3.3 Volt VCXO  
ICR O CLOC K  
Electrical Specifications  
Parameter  
Conditions  
Minimum  
Typical  
Maximum Units  
ABSOLUTE MAXIMUM RATINGS (note 1)  
Supply voltage, VDD  
Referenced to GND  
7
VDD+0.5  
70  
V
V
Inputs and Clock Outputs  
Ambient Operating Temperature  
Soldering Temperature  
Storage temperature  
Referenced to GND  
Max of 10 seconds  
-0.5  
0
°C  
°C  
°C  
260  
-65  
150  
DC CHARACTERISTICS (VDD = 3.3 V unless noted)  
Operating Voltage, VDD  
3.15  
2.4  
3.45  
0.4  
V
V
Output High Voltage, VOH  
Output Low Voltage, VOL  
IOH=-12mA  
IOL=12mA  
IOH=-4mA  
No Load  
V
Output High Voltage, VOH, CMOS level  
Operating Supply Current, IDD  
Short Circuit Current  
VDD-0.4  
0
V
9
mA  
mA  
V
±50  
VIN, VCXO control voltage  
3.3  
AC CHARACTERISTICS (VDD = 3.3 V unless noted)  
Input Crystal Frequency  
13.50000  
MH z  
ns  
Output Clock Rise Time  
0.8 to 2.0V  
2.0 to 0.8V  
At 1.4V  
1.5  
1.5  
60  
Output Clock Fall Time  
ns  
Output Clock Duty Cycle  
40  
50  
%
Maximum Absolute Jitter, short term  
54 MHz output pullability, note 2  
100  
ps  
0V £ VIN £ 3.3 V  
±100  
ppm  
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged  
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.  
2. With an ICS approved pullable crystal. The A version has a typical range of ±180 ppm.  
External Components  
The MK3754 requires a minimum number of external components for proper operation. A decoupling  
capacitor of 0.01µF should be connected between VDD and GND on pins 2 and 4, as close to the  
MK3754 as possible. A series termination resistor of 33 Wmay be used for the clock output. The input  
crystal must be connected as close to the chip as possible. The input crystal should be a parallel mode,  
pullable, AT cut, 13.5 MHz, with 14 pF load capacitance. Consult ICS for recommended suppliers.  
IMPORTANT - read application note MAN05 before laying out the PCB.  
MDS 3754 D  
3
Revision 060100  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com  
MK3754  
Low Cost 54 MHz 3.3 Volt VCXO  
ICR O CLOC K  
Package Outline and Package Dimensions  
(For current dimensional specifications, see JEDEC Publication No. 95.)  
8 pin SOIC  
Inches  
Min  
Millimeters  
Symbol  
A
Max  
Min  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
1.27 BSC  
5.80  
0.25  
0.41  
Max  
0.0532 0.0688  
0.0040 0.0098  
0.0130 0.0200  
0.0075 0.0098  
0.1890 0.1968  
0.1497 0.1574  
.050 BSC  
1.75  
0.24  
0.51  
0.24  
5.00  
4.00  
A1  
B
C
E
H
INDEX  
AREA  
D
E
e
H
h
0.2284 0.2440  
0.0099 0.0195  
0.0160 0.0500  
6.20  
0.50  
1.27  
1
2
h x 45°  
L
D
A
A1  
C
B
e
L
Ordering Information  
Part/Order Number  
MK3754A  
Marking  
MK3754A  
MK3754A  
MK3754S  
MK3754S  
Shipping packaging  
tubes  
Package  
Temperature  
0-70 °C  
8 pin SOIC  
8 pin SOIC  
8 pin SOIC  
8 pin SOIC  
MK3754ATR  
MK3754S  
tape and reel  
tubes  
0-70 °C  
0-70 °C  
MK3754STR  
tape and reel  
0-70 °C  
CHANGE HISTORY  
Version Date first published  
Status  
Comments  
D
C
B
A
6/01/00  
12/29/99  
5/25/99  
4/19/99  
Added A version  
Preliminary  
Preliminary  
Preliminary  
Added JEDEC dimensions. Changed VDD to ±5%. Added crystal specs.  
Updated specs for crystal capacitance, IDD, jitter.  
Original  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems Incorporated (ICS) assumes no responsibility for either its  
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is  
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does  
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.  
MDS 3754 D  
4
Revision 060100  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com  

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