MK3805RILFTR [IDT]
Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20;
| 型号： | MK3805RILFTR |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
BUFFER/CLOCK DRIVER
MK3805
Description
Features
The MK3805 is a non-inverting clock driver/buffer providing
two independent banks of four outputs each. These buffers
have a tri-state output enable input (active low) with 1-input,
5-output configuration per group. The skew between the
outputs of the same package is 0.5 ns and the skew
between the outputs of different packages is 0.8 ns. The
maximum input to output delay is 4.5 ns.
• Packaged in 20-pin SSOP
• Pb (lead) free package
• Five outputs for each bank with one clock input
• Two separate banks of five outputs each
• Advanced, low-power, CMOS process
• Ten output clocks
• Two separate inputs
• Industrial temperature range -40°C to +85°C
• Hysteresis on all inputs
Block Diagram
VDD
2
OEA
INA
OA0-4
5
5
OEB
INB
OB0-4
MON
3
GND
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BUFFER/CLOCK DRIVER
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Pin Assignment
Truth Table
Inputs
Outputs
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OA0
OA1
OA2
GND
OA3
OA4
VCC
OB0
OEA, OEB
INA, INB
OAN, OBN
MON
L
L
L
H
L
L
H
Z
Z
L
H
L
OB1
OB2
GND
OB3
OB4
MON
OEB
INB
H
H
H
H
GND
OEA
INA
20 pin (150 mil) SSOP/20 pin (300mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
VCC
OA0
OA1
OA2
GND
OA3
OA4
GND
OEA
INA
Power
Connect to +3.3 V.
Output Clock output.
Output Clock output.
Output Clock output.
3
4
5
Power
Connect to ground.
6
Output Clock output.
Output Clock output.
7
8
Power
Input
Input
Input
Input
Connect to ground.
Tri state output enable input (active low).
9
10
11
12
13
14
15
16
17
18
19
20
Clock input.
INB
Clock input.
OEB
MON
OB4
OB3
GND
OB2
OB1
OB0
VCC
Tri state output enable input (active low).
Output Monitor output.
Output Clock output.
Output Clock output.
Power
Connect to ground.
Output Clock output.
Output Clock output.
Output Clock output.
Power
Connect to +3.3 V.
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BUFFER/CLOCK DRIVER
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External Components
PCB Layout Recommendations
The MK3805 requires a minimum number of external
components for proper operation.
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through the signal
layers. Other signal traces should be routed away from the
MK3805. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
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Recommended Operation Conditions
Parameter
Min.
-40
Typ.
Max.
+85
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
+3.13
+3.3
+3.46
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40°C to +85°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
Operating Voltage
3.13
3.3
3.3
3.46
V
Supply Current
IDD
No load, OEA,OEB
GND, fo=10MHz, 50%
duty cycle
mA
IDD
ICC
No load, OEA,OEB
GND, fo=2.5MHz,
50% duty cycle
1.8
3
mA
Quiescent Current
Input High Voltage
Input Low Voltage
30
µA
V
V
2
IH
V
0.8
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
Nominal Output Impedance
Input Hysteresis
V
V
I
I
I
= -4 mA
= -12 mA
= 12 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
0.4
V
OL
I
CLK output
50
5
mA
pF
Ω
OS
Z
20
O
V
150
mV
H
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40°C to +85°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Skew between outputs of same
package)
tsk
CL=50 pF, RL=500Ω
0.5
ns
(o)
Skew between outputs of
different packages at same
temp (same transition)
tsk
CL=50 pF, RL=500Ω
0.8
ns
(t)
Propagation Delay INA to OAN
INB to OBN
t
t
,
CL=50 pF, RL=500Ω
CL=50 pF, RL=500Ω
CL=50 pF, RL=500Ω
1.5
4.5
2
ns
ns
ns
ns
ns
PLH
PHL
Output Rise Time
0.8 V to 2.0 V
t
R
Output Fall Time
2.0 V to 0.8 V
t
2
F
Output Enable Time
OEA to OAN, CL=50 pF, RL=500Ω
OEB to OBN
1.5
1.5
6.2
5.0
Output Disable Time
OEA to OAN, CL=50 pF, RL=500Ω
OEB to OBN
Duty Cycle Measured at VDD/2
Operating Frequency
CL=50 pF, RL=500Ω
CL=50 pF, RL=500Ω
45
1
55
%
100
MHz
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Package Outline and Package Dimensions (20-pin SSOP, 1±0 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Inches*
Symbol
Min
1.35
0.10
--
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
.069
.010
.059
0.012
.010
.344
.244
.157
A
A1
A2
b
C
D
.053
.0040
--
E1
E
INDEX
AREA
0.20
0.18
8.55
5.80
3.80
0.008
.007
.337
.228
.150
1
2
E
E1
e
D
0.635 Basic
0.025 Basic
L
α
0.40
0°
1.27
8°
.016
0°
.050
8°
A
A2
*For reference only. Controlling dimensions in mm.
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
MK3805RILF
Marking
MK3805RILF
MK3805RILF
Shipping Packaging
Tubes
Package
20-pin SSOP
20-pin SSOP
Temperature
-40 to +85° C
-40 to +85° C
MK3805RILFTR
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ BUFFER/CLOCK DRIVER
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MK3805
REV E 051310
MK3805
BUFFER/CLOCK DRIVER
FAN OUT BUFFER
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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Printed in USA
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