MPC941AER2 [IDT]
TQFP-48, Reel;
| 型号： | MPC941AER2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-48, Reel 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
MPC941
The MPC941 is a 1:27 low voltage clock distribution chip. The device features
the capability to select either a differential LVPECL or an LVCMOS compatible
input. The 27 outputs are LVCMOS compatible and feature the drive strength to
drive 50 Ω series or parallel terminated transmission lines. With output-to-output
skews of 250 ps, the MPC941 is ideal as a clock distribution chip for the most
demanding of synchronous systems. For a similar product with a smaller number
of outputs, please consult the MPC940 data sheet.
LOW VOLTAGE 3.3 V/2.5 V
1:27 CLOCK
DISTRIBUTION CHIP
•
•
•
•
•
•
•
•
•
LVPECL or LVCMOS Clock Input
250 ps Maximum Output-to-Output Skew
Drives Up to 54 Independent Clock Lines
Maximum Output Frequency of 250 MHz
High Impedance Output Enable
Extended Temperature Range: –40°C to +85°C
48-Lead LQFP Packaging
48-Lead Pb-free Package Available
3.3 V or 2.5 V VCC Supply Voltage
With a low output impedance, in both the HIGH and LOW logic states, the
FA SUFFIX
48-LEAD LQFP PACKAGE
CASE 932-03
output buffers of the MPC941 are ideal for driving series terminated transmission
lines. More specifically, each of the 27 MPC941 outputs can drive two series
terminated 50 Ω transmission lines. With this capability, the MPC941 has an
effective fanout of 1:54. With this level of fanout, the MPC941 provides enough
copies of low skew clocks for most high performance synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface
directly with an LVPECL fanout buffer like the MC100EP111 to build very wide
clock fanout trees or to couple to a high frequency clock source. The LVCMOS
input provides a more standard interface for applications requiring only a single
clock distribution chip at relatively low frequencies. In addition, the two clock
sources can be used as a test clock interface as well as the primary system clock.
A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock
input.
AE SUFFIX
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
The MPC941 is fully 3.3 V and 2.5 V compatible. The 48-lead LQFP package was chosen to optimize performance, board
space and cost of the device. The 48-lead LQFP has a 7x7 mm body size.
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
LOGIC DIAGRAM
PECL_CLK
Pulldown
0
1
PECL_CLK
Q0
LVCMOS_CLK
Pulldown
25
Q1–Q25
Q26
LVCMOS_CLK_SEL
Pulldown
OE
PULLDOWN
Pinout: 48-Lead TQFP (Top View)
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
GND
Q16
Q17
Q18
VCC
Q19
Q20
GND
Q21
Q22
Q23
VCC
VCC
Q7
FUNCTION TABLE
LVCMOS_CLK_SEL
23
22
21
20
19
18
17
16
15
14
13
Input
Q6
0
1
PECL_CLK
LVCMOS_CLK
Q5
GND
Q4
MPC941
Q3
VCC
Q2
Q1
Q0
GND
1
2
3
4
5
6
7
8
9
10 11 12
Table 1. Pin Configuration
Pin
I/O
Type
Function
PECL_CLK,
PECL_CLK
Input
LVPECL
LVPECL differential reference clock inputs
LVCMOS_CLK
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
Supply
Alternative reference clock input
Input reference clock select
Output tristate control
LVCMOS_CLK_SEL
OE
GND
VCC
Negative voltage supply output bank (GND)
Positive voltage supply
Supply
Q0–Q26
Output
LVCMOS
Clock outputs
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Table 2. Absolute Maximum Ratings(1)
Symbol
VCC
VIN
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
Unit
V
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
VCC+0.3
VCC+0.3
±20
V
VOUT
IIN
IOUT
TS
V
mA
mA
°C
±50
–40
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 3. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40 to +85°C)
Symbol
VIH
Characteristics
Min
2.0
Typ
Max
VCC + 0.3
0.8
Unit
V
Condition
LVCMOS
Input High Voltage
Input Low Voltage
Input Current
LVCMOS_CLK
LVCMOS_CLK
VIL
–0.3
V
LVCMOS
IIN
±120(1)
µA
mV
VPP
Peak-to-Peak Input Voltage
PECL_CLK,
PECL_CLK
500
1.2
2.4
LVPECL
VCMR
Common Mode Range
PECL_CLK,
PECL_CLK
VCC –0.8
V
LVPECL
VOH
VOL
Output High Voltage
Output Low Voltage
V
IOH = –24 mA(2)
IOL = 24 mA(2)
IOL = 12 mA
0.55
0.40
V
V
IOZ
ZOUT
CPD
CIN
Output Tristate Leakage Current
Output Impedance
100
10
5
µA
Ω
14 – 17
7-8
Power Dissipation Capacitance
Input Capacitance
pF
pF
mA
V
Per Output
4.0
ICCQ
VTT
Maximum Quiescent Supply Current
Output Termination Voltage
All VCC Pins
V
CC ÷ 2
1. Input pull-up / pull-down resistors influence input current.
2. The MPC941 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Table 4. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40 to +85°C)(1)
Symbol
fMAX
Characteristics
Maximum Output Frequency
Min
Typ
Max
250(2)
1.0(3)
Unit
MHz
ns
Condition
0
tr, tf
LVCMOS_CLK Input Rise/Fall Time
0.8 to 2.0 V
tPLH
tPHL
Propagation Delay
PECL_CLK to any Q
LVCMOS_CLK to any Q
1.2
0.9
1.8
1.5
2.6
2.3
ns
ns
tPLZ, HZ
tPZL, LZ
tsk(O)
Output Disable Time
Output Enable Time
Output-to-Output Skew
ns
ns
ps
PECL_CLK to any Q
LVCMOS_CLK to any Q
125
125
250
250
tsk(PP)
tsk(PP)
DCQ
tr, tf
Device-to-Device Skew
Device-to-Device Skew
Output Duty Cycle
PECL_CLK to any Q
1000
1000
ps
ps
For a given TA and
VCC, any Q
LVCMOS_CLK to any Q
PECL_CLK to any Q
LVCMOS_CLK to any Q
1400
1400
ps
ps
For any TA, VCC
and Q
PECL_CLK to any Q
LVCMOS_CLK to any Q
45
45
50
50
60
55
%
%
DCREF = 50%
DCREF = 50%
Output Rise/Fall Time
0.2
1.0
ns
0.55 to 2.4 V
1. AC characteristics apply for parallel output termination of 50 Ω to VTT.
2. AC characteristics are guaranteed up to fmax. Please refer to applications section for information on power consumption versus operating
frequency and thermal management.
3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application,
signal transition times smaller than 3 ns can be applied to the MPC941.
Table 5. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40 to +85°C)
Symbol
VIH
Characteristics
Min
1.7
Typ
Max
VCC + 0.3
0.7
Unit
V
Condition
LVCMOS
Input High Voltage
Input Low Voltage
Input Current
LVCMOS_CLK
LVCMOS_CLK
VIL
–0.3
V
LVCMOS
IIN
±120(1)
µA
mV
VPP
Peak-to-Peak Input Voltage
PECL_CLK,
PECL_CLK
500
1.1
1.8
LVPECL
LVPECL
VCMR
Common Mode Range
PECL_CLK,
PECL_CLK
VCC – 0.7
V
VOH
VOL
IOZ
Output High Voltage
V
V
IOH = –15 mA(2)
IOL = 15 mA(2)
Output Low Voltage
0.6
Output Tristate Leakage Current
Output Impedance
100
µA
Ω
ZOUT
CPD
CIN
18 – 20
7 – 8
4.0
Power Dissipation Capacitance
Input Capacitance
10
5
pF
pF
mA
V
Per Output
ICCQ
VTT
Maximum Quiescent Supply Current
Output Termination Voltage
All VCC Pins
V
CC ÷ 2
1. Input pull-up / pull-down resistors influence input current.
2. The MPC941 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Table 6. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40 to +85°C)(1)
Symbol
fMAX
Characteristics
Maximum Output Frequency
Min
Typ
Max
250(2)
1.0(3)
Unit
MHz
ns
Condition
0
tr, tf
LVCMOS_CLK Input Rise/Fall Time
Propagation Delay
0.7 to 1.7 V
tPLH
tPHL
PECL_CLK to any Q
1.3
1.0
2.1
1.8
2.9
2.6
ns
ns
LVCMOS_CLK to any Q
tPLZ, HZ
tPZL, LZ
tsk(O)
Output Disable Time
Output Enable Time
Output-to-Output Skew
ns
ns
ps
PECL_CLK to any Q
LVCMOS_CLK to any Q
125
125
250
250
tsk(PP)
tsk(PP)
DCQ
tr, tf
Device-to-Device Skew
Device-to-Device Skew
Output Duty Cycle
PECL_CLK to any Q
1200
1200
ps
ps
For a given TA and
VCC, any Q
LVCMOS_CLK to any Q
PECL_CLK to any Q
LVCMOS_CLK to any Q
1600
1600
ps
ps
For any TA, VCC
and Q
PECL_CLK to any Q
LVCMOS_CLK to any Q
45
45
50
50
60
55
%
%
DCREF = 50%
DCREF = 50%
Output Rise/Fall Time
0.2
1.0
ns
0.6 to 1.6 V
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. AC characteristics are guaranteed up to fMAX. Please refer to the applications section for information on power consumption versus operating
frequency and thermal management.
3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application,
signal transition times smaller than 3 ns can be applied to the MPC941.
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
APPLICATIONS INFORMATION
Driving Transmission Lines
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
The MPC941 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091 in the Timing Solutions data book (DL207/D).
In most high performance clock networks, point-to-point
distribution of signals is the method of choice. In a point-to-
point scheme, either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50 Ω
resistance to VCC/2. This technique draws a fairly high level
of DC current, and thus, only a single terminated line can be
driven by each output of the MPC941 clock driver. For the
series terminated case, however, there is no DC current
draw; thus, the outputs can drive multiple series terminated
lines. Figure 1 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC941 clock
driver is effectively doubled due to its capability to drive
multiple lines.
VL = VS ( ZO / (RS + RO + ZO))
ZO = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
RO = 14 Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case, 4.0 ns).
3.0
OutA
tD = 3.8956
2.5
2.0
1.5
1.0
0.5
0
OutB
tD = 3.9386
IN
MPC941
Output
Buffer
ZO = 50Ω
RS = 36Ω
14Ω
IN
OutA
2
4
6
8
10
12
14
TIME (ns)
Figure 2. Single versus Dual Waveforms
MPC941
Output
Buffer
ZO = 50Ω
ZO = 50Ω
RS = 36Ω
RS = 36Ω
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 3 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
OutB0
OutB1
14Ω
IN
Figure 1. Single versus Dual Transmission Lines
MPC941
Output
Buffer
The waveform plots of Figure 2 show the simulation
results of an output driving a single line vs two lines. In both
cases, the drive capability of the MPC941 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC941. The output waveform
in Figure 2 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
RS = 22Ω
RS = 22Ω
ZO = 50Ω
14Ω
Z
O = 50Ω
14Ω + 22Ω || 22Ω = 50Ω ||50Ω
25Ω = 25Ω
Figure 3. Optimized Dual Line Termination
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Power Consumption of the MPC941 and Thermal
Management
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination. VOL, IOL, VOH and IOH are a
function of the output termination technique, and DCQ is the
clock signal duty cyle. If transmission lines are used, ΣCL is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature TJ as a
function of the power consumption.
Where Rthja is the thermal impedance of the package
(junction to ambient), and TA is the ambient temperature,
according to Table 7, the junction temperature can be used to
estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC941 in a series terminated
transmission line system.
The MPC941 AC specification is guaranteed for the entire
operating frequency range up to 250 MHz. The MPC941
power consumption and the associated long-term reliability
may decrease the maximum frequency limit, depending on
operating conditions such as clock frequency, supply voltage,
output loading, ambient temperture, vertical convection and
thermal conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the MPC941
die junction temperature and the associated device reliability.
For a complete analysis of power consumption as a function
of operating conditions and associated long term device
reliability, please refer to the Freescale application note
AN1545. According the AN1545, the long-term device
reliability is a function of the die junction temperature:
TJ,MAX should be selected according to the MTBF system
requirements, and Table 7, Rthja can be derived from Table 8.
The Rthja represent data based on 1S2P boards. Using 2S2P
boards will result in a lower thermal impedance than indicated
below.
Table 7. Die Junction Temperature and MTBF
Junction Temperature (°C)
MTBF (Years)
100
110
120
130
20.4
9.1
4.2
2.0
Table 8. Thermal Package Impedance of the 48ld LQFP
Rthja (1P2S board), K/W
Convection, LFPM
Still air
78
68
59
56
54
53
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC941 needs to be
controlled, and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC941 is
represented in equation 1.
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Where ICCQ is the static current consumption of the
MPC941, CPD is the power dissipation capacitance per
output. (Μ)ΣCL represents the external capacitive output
load, and N is the number of active outputs (N is always 27 in
case of the MPC941). The MPC941 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore, ΣCL
is zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
If the calculated maximum frequency is below 250 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC941. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to a estimated
MTBF of 9.1 years (4 years), a supply voltage of either 3.3 V
or 2.5 V, and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection, a decision on
the maximum operating frequency can be made.
Equation 1
PTOT = [ ICCQ + VCC · fCLOCK · ( N · CPD + Σ CL ) ] · VCC
M
PTOT = VCC · [ ICCQ + VCC · fCLOCK · ( N · CPD +MΣ CL ) ] + Σ [ DCQ · IOH · (VCC – VOH) + (1 – DCQ) · IOL · VOL ]
TJ = TA + PTOT · Rthja
Equation 2
Equation 3
P
Tj,MAX – TA
1
– (ICCQ · VCC
)
]
Equation 4
fCLOCK,MAX =
·
[
CPD · N · V2
Rthja
CC
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
300
300
TA = 55°C
TA = 35°C
TA = 65°C
TA = 45°C
TA = 55°C
fMAX (AC)
250
200
250
200
fMAX (AC)
TA = 75°C
TA = 65°C
TA = 75°C
TA = 85°C
150
100
150
100
TA = 85°C
Safe operation
Safe operation
50
0
50
0
500
400
300
200
100
0
500
400
300
200
100
0
IFPM, CONVECTION
IFPM, CONVECTION
Figure 4. Maximum MPC941 frequency,
CC = 3.3 V, MTBF 9.1 years,
driving series terminated transmission lines
Figure 5. Maximum MPC941 frequency,
V
V
CC = 3.3 V, MTBF 9.1 years, 4 pF load per line
300
300
TA = 65°C
TA = 45°C
TA = 75°C
TA = 85°C
TA = 55°C
fMAX (AC)
250
200
fMAX (AC)
250
200
TA = 65°C
TA = 75°C
TA = 85°C
150
100
150
100
Safe operation
Safe operation
50
0
50
0
500
400
300
200
100
0
500
400
300
200
100
0
IFPM, CONVECTION
IFPM, CONVECTION
Figure 7. Maximum MPC941 frequency,
VCC = 3.3 V, MTBF 4 years,
4 pF load per line
Figure 6. Maximum MPC941 frequency,
VCC = 3.3 V, MTBF 4 years,
driving series terminated transmission lines
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
300
300
TA = 75°C
TA = 65°C
250
200
fMAX (AC)
250
200
fMAX (AC)
TA = 85°C
TA = 75°C
TA = 85°C
150
100
150
100
Safe operation
Safe operation
50
0
50
0
500
400
300
200
100
0
500
400
300
200
100
0
IFPM, CONVECTION
IFPM, CONVECTION
Figure 9. Maximum MPC941 frequency,
VCC = 2.5 V, MTBF 9.1 years,
4 pF load per line
Figure 8. Maximum MPC941 frequency,
VCC = 2.5 V, MTBF 9.1 years,
driving series terminated transmission lines
300
300
TA = 75°C
TA = 85°C
fMAX (AC)
250
200
250
200
fMAX (AC)
TA = 85°C
150
100
150
100
Safe operation
Safe operation
50
0
50
0
500
400
300
200
100
0
500
400
300
200
100
0
IFPM, CONVECTION
IFPM, CONVECTION
Figure 10. Maximum MPC941 frequency,
VCC = 2.5 V, MTBF 4 years,
Figure 11. Maximum MPC941 frequency,
VCC = 2.5 V, MTBF 4 years,
4 pF load per line
driving series terminated transmission lines
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
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MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
DUT MPC941
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 12. LVCMOS_CLK MPC941 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
DUT MPC941
ZO = 50Ω
Differential Pulse
Generator
Z
O = 50Ω
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 13. PECL_CLK MPC941 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
VCC
PCLK_CLK
PCLK_CLK
VCMR
V
CC ÷ 2
LVCMOS_CLK
VPP
GND
VCC
VCC
VCC÷2
V
CC ÷ 2
Q
Q
GND
GND
tPD
tPD
Figure 14. LVPECL Propagation Delay (tPD
)
Figure 15. LVCMOS Propagation Delay (tPD
Test Reference
)
Test Reference
VCC
VCC
V
CC ÷ 2
V
CC ÷ 2
GND
GND
VOH
tP
V
CC ÷ 2
t0
GND
DC = tP/t0 x 100%
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay path
within a single device
Figure 16. Output Duty Cycle (DC)
Figure 17. Output-to-Output Skew tSK(O)
VCC = 3.3 V VCC = 2.5 V
VCC = 3.3 V VCC = 2.5 V
2.0
0.8
1.7 V
0.7 V
2.4
1.8 V
0.6 V
0.55
tF
tR
tF
tR
Figure 18. Output Transition Time Test Reference
Figure 19. Input Transition Time Test Reference
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
10
MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
4X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5m, 1994.
0.200 AB T-U
Z
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLAN AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATAUM PLANE AB.
DETAILY
9
A
P
A1
48
37
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
36
1
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
T
U
B
V
AE
AE
B1
V1
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
12
25
13
MILLIMETERS
24
DIM MIN
MAX
7.000 BSC
3.500 BSC
Z
A
A1
B
B1
C
S1
7.000 BSC
3.500 BSC
T, U, Z
1.400
1.600
0.270
1.450
0.230
S
D
E
F
0.170
1.350
0.170
DETAILY
4X
0.200 AC T-U
Z
G
H
J
K
L
M
N
P
0.500 BSC
0.050
0.090
0.500
0˚
0.150
0.200
0.700
7˚
0.080 AC
12˚ REF
G
AB
AC
0.090
0.150
0.160
0.250 BSC
R
0.250
S
S1
V
V1
W
AA
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
AD
M˚
BASE METAL
TOP & BOTTOM
R
N
J
E
C
F
D
M
0.080
AC T- U Z
SECTION AE-AE
W
H
L˚
K
DETAIL AD
AA
CASE 932-03
ISSUE F
48-LEAD LQFP PACKAGE
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
11
MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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