MPC9653AFA [IDT]
PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MPC9653AFA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总10页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock
Generator
Generator
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing
applications. With output frequencies up to 125 MHz and output skews less
than 150 ps the device meets the needs of the most demanding clock
applications.
LOW VOLTAGE
3.3 V LVCMOS 1:8
PLL CLOCK GENERATOR
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 125 MHz
PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32-lead LQFP packaging
32-lead Pb-free Package Available
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC953 and MPC9653
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Functional Description
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With
the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency
range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8)
and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The
internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock
in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F = 36.25 MHz.
ref
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a
zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected
input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass config-
urations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can
be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock
due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, en-
abling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVC-
MOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For
series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective fanout
2
of 1:16. The device is packaged in a 7x7 mm 32-lead LQFP package.
MPC9653A
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
NETCOM
VCC
Q0
Q1
Q2
Q3
Q4
2⋅25 k
0
1
÷ 1
÷ 2
0
1
0
1
PCLK
÷ 4
PCLK
&
Ref
VCO
PLL1
200-500 MHz
VCC
25 k
Q5
FB_IN
FB
Q6
VCC
3⋅25 k
Q7
PLL_EN
QFB
VCO_SEL
BYPASS
MR/OE
25 k
Note 1. PLL will lock @ 145 MHz
Figure 1. MPC9653A Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Q5
GND
Q0
VCC
Q6
VCC
QFB
GND
GND
Q7
MPC9653A
VCC
MR/OE
PCLK
PLL_EN
BYPASS
VCO_SEL
1
2
3
4
5
6
7
8
Figure 2. MPC9653A 32-Lead Package Pinout (Top View)
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
NETCOM
MPC9653A
Table 1. Pin Configuration
Pin
PCLK, PCLK
FB_IN
I/O
Input
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Function
PECL reference clock signal
Input
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0–7
Input
Input
Input
Input
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Output
Output
Supply
Supply
QFB
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
GND
VCC_PLL
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply
for correct operation
Table 2. Function Table
Control
Default
0
1
Selects the VCO output1
PLL_EN
1
Test mode with PLL bypassed. The reference clock (PCLK) is
substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Selects the output dividers.
VCO_SEL
MR/OE
1
0
VCO ÷ 1 (High frequency range). fREF = fQ0–7 = 4 ⋅ fVCO
VCO ÷ 2 (Low output range). fREF = fQ0–7 = 8 ⋅ fVCO
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of the
device. During reset the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The length of the reset
pulse should be greater than one reference clock cycle
(PCLK).
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
NETCOM
Table 3. General Specifications
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
Condition
VTT
V
CC ÷ 2
V
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
200
2000
200
V
V
mA
pF
CPD
Power Dissipation Capacitance
10
Per output
Inputs
CIN
Input Capacitance
4.0
pF
Table 4. Absolute Maximum Ratings1
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
–0.3
3.9
VCC + 0.3
VCC + 0.3
±20
V
VIN
VOUT
IIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–0.3
–0.3
V
V
mA
mA
°C
IOUT
TS
±50
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)
Symbol
Characteristics
Input high voltage
Min
Typ
Max
Unit
Condition
LVCMOS
VIH
2.0
VCC + 0.3
V
VIL
Input low voltage
0.8
V
mV
V
LVCMOS
LVPECL
LVPECL
VPP
Peak-to-peak input voltage
Common Mode Range
(PCLK)
(PCLK)
300
1.0
1
VCC – 0.6
VCMR
IOH = –24 mA2
IOL = 24 mA
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
V
0.55
0.30
V
V
I
OL = 12 mA
ZOUT
IIN
Output impedance
14 – 17
5.0
Ω
Input Current3
±200
µA
VIN = VCC or GND
ICC_PLL
Maximum PLL Supply Current
10
10
mA
mA
VCC_PLL Pin
All VCC Pins
4
Maximum Quiescent Supply Current
ICCQ
1.
V
CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (DC) specification.
2. The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. The MPC9653A meets
the VOH and VOL specification of the MPC953 (VOH > VCC -0.6 V at IOH = -20 mA and VOL > 0.6 V at IOL = 20 mA).
3. Inputs have pull-down or pull-up resistors affecting the input current.
4. OE/MR = 1 (outputs in high-impedance state).
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
NETCOM
MPC9653A
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)1
Symbol
fREF
Characteristics
Input Reference Frequency
PLL Mode, External Feedback
Min
50
25
Typ
Max
125
62.5
Unit
Condition
÷ 4 feedback2
÷ 8 feedback3
MHz PLL locked
MHz PLL locked
Input reference frequency in PLL bypass mode4
VCO Operating Frequency Range5, 6
0
200
500
MHz
MHz
fVCO
fVCOlock
fMAX
200
VCO Lock Frequency Range7
145
500
MHz
Output Frequency
÷ 4 feedback2
÷ 8 feedback3
50
25
125
62.5
MHz PLL locked
MHz PLL locked
VPP
Peak-to-Peak Input Voltage
Common Mode Range
PCLK
PCLK
450
1.2
1000
mV
V
LVPECL
LVPECL
8
VCC – 0.75
VCMR
Input Reference Pulse Width9
tPW, MIN
t(∅)
2
ns
ps
Propagation Delay (static phase offset)10
Propagation Delay
PCLK to FB_IN
–75
125
PLL locked
tPD
PLL and divider bypass (BYPASS = 0), PCLK to Q0–7
1.2
3.0
3.3
7.0
ns
ns
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0–7
Output-to-Output Skew11
Device-to-Device Skew in PLL and Divider Bypass12
Output Duty Cycle
tsk(O)
150
1.5
ps
ns
tsk(PP)
BYPASS = 0
DC
45
50
55
%
PLL locked
0.55 to 2.4 V
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
Output Disable Time
Output Enable Time
Cycle-to-Cycle jitter
Period Jitter
7.0
6.0
100
100
25
ns
ns
ps
ps
ps
I/O Phase Jitter13
RMS (1σ)
PLL closed loop bandwidth14
PLL mode, external feedback
÷ 4 feedback2
BW
0.8 – 4
0.5 – 1.3
MHz
MHz
÷ 8 feedback3
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. ÷ 4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
3. ÷ 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
4. In bypass mode, the MPC9653A divides the input reference clock.
5. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
6. fVCO is frequency range where AC parameters are guaranteed.
7.
8.
f
VCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO
.
V
CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅)
.
9. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% - DCREF,MIN
.
For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
10. Valid for fREF = 50 MHz and FB = ÷ 8 (VCO_SEL = 1). For other reference frequencies: t(∅) [ps] = 50 ps ± (1 ÷ (120 ⋅ fREF)).
11. Refer to the Application Information section for part-to-part skew calculation in PLL zero-delay mode.
12. For a specified temperature and voltage, includes output skew.
13. I/O phase jitter is reference frequency dependent. Refer to APPLICATIONS INFORMATION section for details.
14. –3 dB point of PLL transfer characteristics.
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
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APPLICATIONS INFORMATION
are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 7
Programming the MPC9653A
The MPC9653A supports output clock frequencies from 25
to 125 MHz. Two different feedback divider configurations can
be used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz for
stable and optimal operation. Two operating frequency ranges
illustrates the configurations supported by the MPC9653A. PLL
zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the
input frequency is within the specified PLL reference frequency
range.
Table 7. MPC9653A Configurations (QFB connected to FB_IN)
Frequency
Output Range (fQ0–7
0 – 200 MHz
BYPASS
PLL_EN
VCO_SEL
Operation
)
Ratio
VCO
n/a
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Test mode: PLL and divider bypass
Test mode: PLL bypass
fQ0–7 = fREF
fQ0–7 = fREF ÷ 4
fQ0–7 = fREF ÷ 8
fQ0–7 = fREF
fQ0–7 = fREF
0 – 50 MHz
n/a
Test mode: PLL bypass
0 – 25 MHz
n/a
PLL mode (high frequency range)
PLL mode (low frequency range)
50 to 125 MHz
25 to 62.5 MHz
fVCO = fREF ⋅ 4
fVCO = fREF ⋅ 8
Power Supply Filtering
The MPC9653A is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9653A provides separate power
supplies for the output buffers (VCC) and the phase-locked loop
(VCCA_PLL) of the device. The purpose of this design technique
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCC_PLL pin for the MPC9653A. Figure 3
illustrates a typical power supply filter scheme. The MPC9653A
frequency and phase stability is most susceptible to noise with
spectral content in the 100 kHz to 20 MHz range. Therefore, the
filter should be designed to target this range. The key
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 3, the filter cut-off frequency is around 4 kHz
and the noise attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9653A has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the VCC_PLL
pin) is typically 5 mA (10 mA maximum), assuming that a
minimum of 2.985 V must be maintained on the VCC_PLL pin.
Using the MPC9653A in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9653A. Designs using the MPC9653A as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9653A clock driver allows for its use as a zero-delay buffer.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device (the propagation delay through the device is virtually
eliminated). The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter), feedback
path delay and the output-to-output skew error relative to the
feedback output.
RF = 5–15 Ω
CF = 22 µF
RF
VCC_PLL
MPC9653A
VCC
CF
10 nF
VCC
33...100 nF
Figure 3. VCC_PLL Power Supply Filter
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
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3.3 V 1:8 LVCMOS PLL Clock Generator
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MPC9653A
Calculation of Part-to-Part Skew
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter
confidence factor of 99.7% (± 3σ) is assumed, resulting in a
worst case timing uncertainty from input to any output of
–197 ps to 297 ps (at 125 MHz reference frequency) relative to
PCLK:
The MPC9653A zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9653As are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
tSK(PP) = [-17ps...117ps] + [-150ps...150ps] +
tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) ⋅ CF
[(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB)
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
tSK(PP) = [-197ps...297ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 5,
can be used for a more precise timing performance analysis.
PCLKCommon
30
20
10
tPD,LINE(FB)
—t(ý)
QFBDevice 1
tJIT(∅)
FB = ÷ 8
FB = ÷ 4
Any QDevice 1
+tSK(O)
0
25 35
45 55
65 75 85 95 105 115 125
Reference Frequency [MHz]
+t(∅)
QFBDevice2
Figure 5. Maximum I/O Jitter versus Frequency
tJIT(∅)
Any QDevice 2
Driving Transmission Lines
+tSK(O)
The MPC9653A clock driver was designed to drive high
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive
either parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of
the line with a 50 Ω resistance to VCC ÷ 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9653A clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 5, illustrates an output
driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme the
fanout of the MPC9653A clock driver is effectively doubled due
to its capability to drive multiple lines.
Max. skew
tSK(PP)
Figure 4. MPC9653A Maximum Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8. Confidence Factor CF
CF
Probability of clock edge within the distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
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MPC9653A
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MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
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3.0
2.5
2.0
1.5
1.0
0.5
0
MPC9653A
OUTPUT
BUFFER
OutA
tD = 3.8956
OutB
tD = 3.9386
ZO = 50 Ω
RS = 36 Ω
14 Ω
OutA
IN
In
MPC9653A
OUTPUT
BUFFER
ZO = 50 Ω
RS = 36 Ω
RS = 36 Ω
OutB0
OutB1
14 Ω
IN
ZO = 50 Ω
2
4
6
8
10
12
14
Figure 6. Single versus Dual Transmission Lines
TIME (ns)
The waveform plots in Figure 7 show the simulation results
of an output driving a single line versus two lines. In both cases
the drive capability of the MPC9653A output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9653A. The output waveform in Figure 7 shows a step in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36 Ω series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 8, should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
MPC9653A
OUTPUT
BUFFER
Z
O = 50 Ω
RS = 22 Ω
RS = 22 Ω
VL = VS (Z0 ÷ (RS + R0 + Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
14 Ω
Z
O = 50 Ω
VL = 3.0 (25 ÷ (18 + 14 + 25)
= 1.31 V
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
Figure 8. Optimized Dual Line Termination
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
MPC9653A DUT
ZO = 50 Ω
Differential
Pulse Generator
Z = 50 Ω
ZO = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 9. MPC9653A AC Test Reference
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MPC9653A
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3.3 V 1:8 LVCMOS PLL Clock Generator
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MPC9653A
VCC
V
CC ÷ 2
PCLK
PCLK
GND
VCC
VPP = 0.8 V
VCMR =
VCC –1.3 V
V
CC ÷ 2
VCC
GND
VCC ÷ 2
tSK(O)
FB_IN
GND
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t(PD)
Figure 11. Propagation delay (t(PD), static phase
offset) Test Reference
Figure 10. Output-to-Output Skew tSK(O)
VCC
V
CC ÷ 2
PCLK
PCLK
GND
tP
Ext_FB
T0
DC = tP/T0 x 100%
TJIT(∅) = |T0–T1mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t0 for a controlled edge with respect to a T0
mean in a random sample of cycles
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
TJIT(CC) = |TN–TN+1
|
TJIT(PER) = |TN–1/f0|
TN
TN+1
T0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 14. Cycle-to-Cycle Jitter
Figure 15. Period Jitter
VCC = 3.3 V
2.4
0.55
tF
tR
Figure 16. Output Transition Time Test
Reference
IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
9
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
NETCOM
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