MPC9992FA
更新时间：2024-09-18 19:16:56
品牌：IDT
描述：Clock Generator, 400MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32
概述
规格参数
数据手册MPC9992FA 概述
Clock Generator, 400MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 时钟发生器
MPC9992FA 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | QFP |
| 包装说明： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 | 针数： | 32 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.18 |
| JESD-30 代码： | S-PQFP-G32 | JESD-609代码： | e0 |
| 长度： | 7 mm | 湿度敏感等级： | 3 |
| 端子数量： | 32 | 最高工作温度： | 70 °C |
| 最低工作温度： | 最大输出时钟频率： | 400 MHz | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | LQFP |
| 封装等效代码： | QFP32,.35SQ,32 | 封装形状： | SQUARE |
| 封装形式： | FLATPACK, LOW PROFILE | 峰值回流温度（摄氏度）： | 225 |
| 电源： | 3.3 V | 主时钟/晶体标称频率： | 400 MHz |
| 认证状态： | Not Qualified | 座面最大高度： | 1.6 mm |
| 子类别： | Clock Generators | 最大压摆率： | 1 mA |
| 最大供电电压： | 3.465 V | 最小供电电压： | 3.135 V |
| 标称供电电压： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Tin/Lead (Sn85Pb15) | 端子形式： | GULL WING |
| 端子节距： | 0.8 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 7 mm |
| uPs/uCs/外围集成电路类型： | CLOCK GENERATOR, OTHER | Base Number Matches： | 1 |
MPC9992FA 数据手册
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PDF下载DATA SHEET
MPC9992
3.3 V Differential ECL/PECL PLL
Clock Generator
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using
SiGe technology and a fully differential design ensures optimum skew and PLL
jitter performance. The performance of the MPC9992 makes the device ideal for
workstation, mainframe computer and telecommunication applications. With
output frequencies up to 400 MHz and output skews less than 100 ps the device
meets the needs of the most demanding clock applications. The MPC9992 offers
a differential PECL input and a crystal oscillator interface. All control signals are
LVCMOS compatible.
3.3 V DIFFERENTIAL
ECL/PECL
CLOCK GENERATOR
Features
•
•
•
7 differential outputs, PLL based clock generator
SiGe technology supports minimum output skew (max. 100 ps)
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
Supports up to two generated output clock frequencies with a maximum clock
frequency up to 400 MHz
•
•
•
•
•
•
•
•
Selectable crystal oscillator interface and PECL compatible clock input
SYNC pulse generation
PECL compatible differential clock inputs and outputs
Single 3.3 V (PECL) supply
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Ambient temperature range 0°C to +70°C
Standard 32 lead LQFP package
Pin and function compatible to the MPC992
32-lead Pb-free Package Available
Functional Description
The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock fre-
quency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency
range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback fre-
quency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input ref-
erence frequency range.
The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC gen-
erator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between
output frequencies.
The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock sig-
nal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input
reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock
frequency specification and all other PLL characteristics do not apply.
The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted.
Assertion of the reset signal forces all outputs to the logic low state.
The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is
PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels
with the capability to drive terminated 50 Ω transmission lines.
The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Bank A
QA0
QA0
All input resistors have a value of 50kΩ
V
CC
QA1
QA1
XTAL_IN
XTAL_OUT
XTAL
1
0
÷2, ÷4
÷4, ÷6, ÷10
÷16, ÷24, ÷40
Sync Pulse
0
1
QA2
QA2
Ref
VCO
÷4
÷2
1
0
PCLK
PCLK
QA3
QA3
PLL
800–1600 MHz
V
CC
Bank B
QB0
QB0
REF_SEL
FB
V
CC
QB1
QB1
VCO_SEL
PLL_EN
QB2
QB2
V
CC
2
FSEL[1:0]
MR/STOP
Sync
QSYNC
QSYNC
Figure 1. MPC9992 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
QB0
QB0
QA1
QA1
QA0
QA0
15
14
13
12
11
10
9
QB1
QB1
MPC9992
GND
QB2
V
QB2
CC_PLL
MR/STOP
PLL_EN
GND
V
CC
1
2
3
4
5
6
7
8
Figure 2. MPC9992 32-Lead Package Pinout (Top View)
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Table 1. MPC9992 PLL Configurations
Frequency Ratio
QA to QB
Internal Feedback
(M ⋅ VCO_SEL)
f
(MHz)
QA[3:0] (N )
A
QB[2:0] (N )
B
VCO_SEL
FSEL_0
FSEL_1
REF
0
0
0
16.6–33.3
25–50
VCO÷8
VCO÷12
3÷2
2÷1
5÷2
3÷1
3÷2
2÷1
5÷2
3÷1
VCO÷48
(6 ⋅ f
)
(4 ⋅ f
)
REF
REF
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
VCO÷4
VCO÷8
VCO÷32
VCO÷80
VCO÷48
VCO÷96
VCO÷64
VCO÷160
VCO÷96
(8 ⋅ f
)
(4 ⋅ f
)
REF
REF
10–20
VCO÷8
(10 ⋅ f
VCO÷20
(4 ⋅ f
)
)
REF
REF
16.6–33.3
8.3–16.6
12.5–25
5–10
VCO÷4
VCO÷12
(4 ⋅ f )
REF
(12 ⋅ f
)
REF
VCO÷16
VCO÷24
(4 ⋅ f )
REF
(6 ⋅ f
)
REF
VCO÷8
VCO÷16
(4 ⋅ f )
REF
(8 ⋅ f
)
REF
VCO÷16
VCO÷40
(4 ⋅ f )
REF
(10 ⋅ f
)
)
REF
8.3–16.6
VCO÷8
VCO÷24
(4 ⋅ f
(12 ⋅ f
)
REF
REF
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
REF_SEL
1
Selects PCLK, PCLK as PLL references signal input
Selects the crystal oscillator as PLL reference signal
input
VCO_SEL
PLL_EN
1
1
Selects VCO÷2. The VCO frequency is scaled by a factor Selects VCO÷4. The VCO frequency is scaled by a factor
of 2 (high input frequency range) of 4 (low input frequency range).
Test mode with the PLL bypassed. The reference clock is Normal operation mode with PLL enabled.
substituted for the internal VCO output. MPC9992 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
MR/STOP
0
Normal operation
Reset of the device and output disable (output clock
stop). The outputs are stopped in logic low state: Qx=L,
Qx=H. The minimum reset period should be greater than
one reference clock cycle.
VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios.
See Table 1 for the device frequency configuration.
Table 3. Pin Configuration
Pin
PCLK, PCLK
XTAL_IN, XTAL_OUT
VCO_SEL
I/O
Type
PECL
Function
Input
Differential reference clock signal input
Crystal oscillator interface
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PECL
Input
VCO operating frequency select
PLL Enable/Bypass mode select
PLL reference signal input select
PLL_EN
Input
REF_SEL
Input
MR/STOP
Input
Device reset and output clock disable (stop in logic low state)
Output and PLL feedback frequency divider select
Differential clock outputs (bank A)
FSEL[1:0]
Input
QA[0-3], QA[0–3]
QB[0-2], QB[0–2]
QSYNC, QSYNC
GND
Output
Output
Output
Supply
Supply
PECL
Differential clock outputs (bank B)
PECL
Differential clock outputs (bank C)
GND
Negative power supply
V
V
Positive power supply. All V pins must be connected to the positive power supply for
CC
CC
CC
correct DC and AC operation
V
Supply
V
PLL positive power supply (analog power supply). It is recommended to use an external RC
CC_PLL
CC
filter for the analog power supply pin V
. Please see applications section for details
CC_PLL
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
V
V
+0.3
V
IN
CC
CC
V
DC Output Voltage
DC Input Current
+0.3
V
OUT
I
±20
mA
mA
°C
IN
I
DC Output Current
Storage Temperature
±50
OUT
T
S
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. General Specifications
Symbol
Characteristics
Output Termination Voltage
Min
Typ
– 2
Max
Unit
V
Condition
V
V
TT
CC
MM
ESD Protection (Machine Model)
175
2000
1000
200
V
HBM
ESD Protection (Human Body Model)
V
CDM ESD Protection (Charged Device Model)
V
LU
Latch-Up Immunity
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
Thermal Resistance Junction to Ambient
JA
JESD 51-3, single layer test board
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θ
Thermal Resistance Junction to Case
23.0
26.3
°C/W MIL-SPEC 883E
JC
Method 1012.1
(1)
T
Operating Junction Temperature
(continuous operation)
J
MTBF = 9.1 years
0
110
°C
1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range. It is
recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to
their particular application.
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
4
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Table 6. DC Characteristics (VCC = 3.3 V ± 5%, GND = 0V, TA = 0°C to 70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
(1)
Differential PECL Clock Inputs (PCLK, PCLK)
(2)
V
AC Differential Input Voltage
0.2
1.0
1.3
V
V
Differential operation
Differential operation
PP
(3)
V
Differential Cross Point Voltage
V
-0.3
CMR
CC
(4)
I
Input Current
±120
µA
V
= V or GND
IN
IN CC
LVCMOS Control Inputs (VCO_SEL, PLL_EN, MR/STOP, REF_SEL, FSEL[1:0])
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
CC
V
V
LVCMOS
LVCMOS
IH
V
I
0.8
IL
(4)
Input Current
±120
µA
V
= V or GND
CC
IN
IN
PECL Clock Outputs (QA[3:0], QA[3:0], QB[2:0], QB[2:0], QSYNC, QSYNC)
V
Output High Voltage
Output Low Voltage
V
–1.025
V
V
–0.880
–1.620
V
V
I
I
= –30 mA
= –5 mA
OH
CC
CC
CC
OH
V
V
–1.920
OL
CC
OL
Supply Current and Voltage
V
PLL Supply Voltage
2.955
V
V
V
V
pin
pin
CC_PLL
CC
CC_PLL
I
Maximum PLL Supply Current
Maximum Supply Current
9.0
80
12
110
mA
CC_PLL
(5)
CC_PLL
I
mA GND pins
GND
1. V (DC) is the minimum differential input voltage swing required to maintain device functionality.
PP
2. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(DC)
CMR
CMR
range and the input swing lies within the V (DC) specification.
PP
3. Inputs have pull-down resistors affecting the input current.
4. Equivalent to a termination of 50 Ω to V
.
TT
5. Does not include output drive current which is dependant on output termination methods.
MPC9992
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
5
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Table 7. AC Characteristics (VCC = 3.3 V ± 5%, GND = 0 V, TA = 0°C to +70°C)(1)
Symbol
Characteristics
Input Reference Frequency
Min
Typ
Max
Unit
Condition
f
÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
÷160 feedback
25.0
16.67
12.5
10.0
8.33
5.0
50.0
33.3
25.0
20.0
16.67
10.0
MHz PLL locked
ref
MHz
MHz
MHz
MHz
MHz
(2)
Input Reference Frequency in PLL Bypass Mode
400
20
MHz PLL bypass
(3)
f
Crystal Interface Frequency Range
10
MHz
MHz
XTAL
(4)
f
VCO Frequency Range
800
1600
VCO
MAX
f
Output Frequency
÷4 output
200.0
100.0
66.6
50.0
40.0
33.3
16.6
400.0
200.0
133.3
100.0
80.0
MHz PLL locked
÷8 output
÷12 output
÷16 output
÷20 output
÷24 output
÷48 output
MHz
MHz
MHz
MHz
MHz
MHz
66.6
33.3
(5)
V
Differential Input Voltage (peak-to-peak)
0.3
1.2
0.6
2.0
1.3
V
V
PP
(6)
V
Differential Input Crosspoint Voltage
(PCLK)
V
–0.3
CC
CMR
V
Differential Output Voltage (peak-to-peak) (PCLK)
0.8
V
O(P-P)
(7)
t
Input Reference Pulse Width
ns
ps
%
ps
ps
ps
PW,MIN
t
Output-to-Output Skew
100
sk(O)
(8)
DC
Output Duty Cycle
48
50
30
43
86
52
79
(9)
t
Cycle-to-Cycle Jitter
JIT(CC)
(9)
t
Period Jitter
106
212
JIT(PER)
(9)
(10)
t
I/O Phase Jitter
RMS (1 σ)
JIT(∅)
(11)
BW
PLL Closed Loop Bandwidth
÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
÷160 feedback
0.60-1.5
0.40-1.2
0.30-1.0
0.30-0.8
0.20-0.7
0.15-0.4
MHz
MHz
MHz
MHz
MHz
MHz
t
Maximum PLL Lock Time
Output Rise/Fall Time
10
ms
LOCK
t , t
0.05
1.0
ns
20% to 80%
r
f
1. AC characteristics apply for parallel output termination of 50 Ω to V
.
TT
2. In bypass mode, the MPC9992 divides the input reference clock.
3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
= f ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f ≤ 20 MHz.
f
XTAL(min, max)
VCO(min, max)
XTAL
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f = f
÷ (M ⋅ VCO_SEL)
ref
VCO
5. V is the minimum differential input voltage swing required to maintain AC characteristics.
PP
6. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC)
CMR
CMR
range and the input swing lies within the V (AC) specification.
PP
7. Calculation of reference duty cycle limits: DC
= t
⋅ f
⋅ 100% and DC
= 100% – DC
E.g. at f
= 50 MHz
REF
REF,MIN
PW,MIN REF
REF,MAX
REF, MIN.
the input duty cycle range is 10% < DC < 90%.
8. Output duty cycle for QAx and QBx outputs. The pulse width for the QSYNC output is equal to one QAx output period t ± 5%.
QA
9. Jitter data is valid f = 25 MHz.
ref
10. See application section for a jitter calculation for other confidence factors than 1 σ.
11. –3 dB point of PLL transfer characteristics.
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
6
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
APPLICATIONS INFORMATION
the B bank of outputs. The QSYNC output is asserted (logic
SYNC Output Description
high) one QA period in duration. The placement of the pulse
is dependent on the QA and QB output frequencies ratio.
Figure 3 shows the waveforms for the QSYNC output. The
QSYNC output is defined for all possible combinations of the
bank A and bank B outputs.
The MPC9992 has a system synchronization pulse output
QSYNC. In configurations with the output frequency
relationships are not integer multiples of each other QSYNC
provides a signal for system synchronization purposes. The
MPC9992 monitors the relationship between the A bank and
2:1 Mode
Qa
Qb
QSYNC
3:1 Mode
3:2 Mode
5:2 Mode
Qa
Qb
QSYNC
Qa
Qb
QSYNC
Qa
Qb
QSYNC
Figure 3. QSYNC Timing Diagram
MPC9992
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
7
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
Power Supply Filtering
R = 10 – 15Ω
C = 22 µF
F
F
The MPC9992 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL power supply impacts the device
R
F
V
V
CC
CC_PLL
C
10 nF
F
MPC9992
characteristics, for instance I/O jitter. The MPC9992 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9992. Figure 4 illustrates a typical
power supply filter scheme. The MPC9992 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the VCC_PLL
pin) is typically 9 mA (12 mA maximum), assuming that a
minimum of 2.955 V must be maintained on the VCC_PLL pin.
The resistor RF shown in Figure 4 must have a resistance of
10-15 Ω to meet the voltage drop criteria.
V
CC
33...100 nF
Figure 4. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 4, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9992 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Z = 50 Ω
Z = 50 Ω
Differential Pulse
Generator
Z = 50 Ω
MPC9992 DUT
R = 50 Ω
R = 50 Ω
T
T
V
V
TT
TT
Figure 5. MPC9992 AC Test Reference
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
8
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9992
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
9
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
MPC9992
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
10
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
NETCOM
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9992
IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
11
992
3.3VDifferentialECL/PECL PLLClockGenerator
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
+408 284 8200 (outside U.S.)
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
MPC9992FA 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MPC9992FAR2 | MOTOROLA | Clock Generator, 400MHz, CMOS, PQFP32, LQFP-32 | 获取价格 |
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| MPC9993 | MOTOROLA | INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER | 获取价格 |
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| MPC9993AC | IDT | PLL Based Clock Driver, 9993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 | 获取价格 |
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| MPC9993ACR2 | IDT | PLL Based Clock Driver, 9993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 | 获取价格 |
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| MPC9993D | MOTOROLA | INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER | 获取价格 |
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| MPC9993DFA | MOTOROLA | INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER | 获取价格 |
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| MPC9993FA | MOTOROLA | INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER | 获取价格 |
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| MPC9993FAR2 | MOTOROLA | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 | 获取价格 |
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| MPC9993FAR2 | NXP | IC,1:5 OUTPUT, DIFFERENTIAL,CMOS,QFP,32PIN,PLASTIC | 获取价格 |
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| MPC99J93 | MOTOROLA | Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver | 获取价格 |
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