QS5919T [IDT]
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER; 具有集成环路滤波器低偏移TTL PLL时钟驱动器
| 型号： | QS5919T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW TTL PLL
QS5919T
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
DESCRIPTION
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
5V operation
Low noise TTL level outputs
< 350ps output skew, Q0–Q4
2xQ output, Q outputs, Q output, Q/2 output
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Functional equivalent to Motorola MC88915
Positive or negative edge synchronization (PE)
Balanced drive outputs ±24mA
The QS5919T Clock Driver uses an internal phase locked loop (PLL)
tolocklowskewoutputs tooneoftworeferenceclockinputs.Eightoutputs
are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure <
350ps skewbetweenthe Q0-Q4,andQ/2outputs.The QS5919Tincludes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies.The PLLcanalsobe disabledbythe PLL_ENsignaltoallow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lockhas beenachieved.The QS5919Tis designedforuse inhigh-
performanceworkstations,multi-boardcomputers,networkinghardware,
and mainframe systems. Several can be used in parallel or scattered
throughoutasystemforguaranteedlowskew,system-wideclockdistribu-
tionnetworks.
160MHz maximum frequency (2xQ output)
Available in QSOP and PLCC packages
FormoreinformationonPLLclockdriverproducts,seeApplicationNote
AN-227.
FUNCTIONALBLOCKDIAGRAM
REF_SEL
LOCK
FEEDBACK
PLL_EN
FREQ_SEL
PE
0
SYNC0
0
1
1
0
1
1
SYNC
PHASE
LOOP
FILTER
VCO
/2
DETECTOR
OE/RST
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
5
Q
4
3
2
1
0
Q
Q/2
Q
Q
Q
Q
2xQ
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1
c
2000 Integrated Device Technology, Inc.
DSC-5815/-
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PINCONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
1
2
Q4
GND
Q5
VDD
4
3
2
1
28
27
26
VDD
2xQ
Q/2
3
4
25
24
23
22
21
20
19
Q/2
FEEDBACK
REF_SEL
SYNC0
AVDD
5
OE/RST
FEEDBACK
REF_SEL
SYNC0
GND
Q3
6
GND
Q3
5
6
7
8
9
7
VDD
Q2
VDD
Q2
8
J28-1
SO28-9
AVDD
PE
PE
9
GND
10
11
GND
LOCK
AGND
LOCK
PLL_EN
GND
10
11
AGND
SYNC1
SYNC1
12 13 14 15 16
17 18
17
16
15
FREQ_SEL
GND
12
13
14
Q1
VDD
Q0
PLCC
QSOP
TOP VIEW
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Rating
Max.
Unit
VDD, AVDD Supply Voltage to Ground
–0.5 to +7
V
VIN
DC Input Voltage VIN
–0.5 to +7
V
Maximum Power
QSOP
PLCC
655
770
mW
mW
Dissipation (TA = 85°C)
Storage Temperature Range
TSTG
–65°C to +150°C °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25° C, f = 1MHz, V = 0V)
IN
QSOP
PLCC
Parameter
Typ.
Max.
Typ.
Max.
Unit
CIN
3
4
4
6
pF
2
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC0
I
I
I
I
I
Reference clock input
Reference clock input
SYNC1
REF_SEL
FREQ_SEL
FEEDBACK
Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Q0 -Q4
Q5
O
O
O
O
O
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
2xQ
Q/2
LOCK
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to
the inputs.
OE/RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL_EN
I
I
PLL enable. Enables and disables the PLL. Useful for testing purposes.
PE
When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the
negative edge of SYNC.
VDD
—
—
—
—
Power supply for output buffers.
AVDD
GND
AGND
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
VDD
Industrial: TA = –40°C to +85°C, AVDD /
= 5.0V ± 10%
Symbol
FMAX_2XQ
FMAX_Q
Description
– 55
55
– 70
70
– 100
100
50
– 133
133
66.5
33.25
20
– 160
160
80
Units
MHz
MHz
MHz
MHz
MHz
MHz
Max Frequency, 2xQ
Max Frequency, Q0 - Q4, Q5
Max Frequency, Q/2
Min Frequency, 2xQ
Min Frequency, Q0 - Q4, Q5
Min Frequency, Q/2
27.5
13.75
20
35
FMAX_Q/2
FMIN_2XQ
FMIN_Q
17.5
20
25
40
20
20
10
10
10
10
10
FMIN_Q/2
5
5
5
5
5
3
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
FREQUENCY SELECTION TABLE
SYNC (MHz)
(allowable range) (1)
Output Used for
Feedback
Output Frequency Relationships (2)
FREQ_SEL
HIGH
HIGH
HIGH
HIGH
LOW
Min.
Max
Q/2
Q5
Q0 - Q4
SYNC X 2
SYNC
2XQ
Q/2
Q0 -Q4
Q5
FMIN_Q/2
FMIN_Q
FMAX _Q/2
FMAX _Q
SYNC
– SYNC X 2
– SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
FMIN_Q
FMAX _Q
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
2xQ
Q/2
FMIN_2XQ
FMIN_Q/2 /2
FMIN_Q /2
FMIN_Q /2
FMIN_2XQ /2
FMAX _2XQ
FMAX _Q/2 /2
FMAX _Q /2
FMAX _Q /2
FMAX _2XQ /2
– SYNC / 2
– SYNC X 2
– SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
LOW
Q0 -Q4
Q5
SYNC / 2
– SYNC / 2
SYNC / 4
LOW
SYNC
– SYNC
SYNC / 2
LOW
2xQ
– SYNC / 2
NOTES:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect
output frequencies.
2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, AVDD / VDD = 5.0V ± 10%
Symbol
Parameter
Input HIGH Voltage
Conditions
Min.
Typ.
Max.
Unit
VIH
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
VDD = Min., IOH = −24mA
VDD = Min., IOH = −100µA
VDD = Min., IOL = 24mA
VDD = Min., IOL = 100µA
—
—
2.4
3
—
—
—
—
—
100
—
—
—
0.8
—
—
0.45
0.2
—
5
V
V
VOH
Output HIGH Voltage
V
VOL
Output LOW Voltage
—
—
—
—
—
—
V
V
VH
IOZ
IIN
Input Hysteresis
mV
µA
µA
µA
Output Leakage Current
Input Leakage Current
Input Pull-Down Current (PE)
VOUT = VDD or GND, VDD = Max.
VIN = AVDD or GND, AVDD = Max.
AVDD = Max., VIN = AVDD
5
IPD
100
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
VDD = Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
1.5
mA
∆IDD
Power Supply Current per Input HIGH
Dynamic Power Supply Current (1)
V
DD = Max., V = 3.4V
0.5
0.2
1.5
0.4
mA
IN
IDDD
VDD = Max., CL = 0pF
mA/MHz
NOTE:
1. Relative to the frequency of Q outputs.
4
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
3
ns
(1)
FI
tPWC
DH
Input Clock Frequency, SYNC0, SYNC1
Input clock pulse, HIGH or LOW (2)
Input duty cycle (2)
2.5
2
FMAX _2XQ
MHz
ns
—
75
25
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter (1)
Min.
Max.
Unit
(2)
(2)
tSKR
Output Skew Between Rising Edges, Q0-Q4 and Q/2
—
350
ps
tSKF
tSKALL
tPW
tPW
tJ
Output Skew Between Falling Edges, Q0-Q4 and Q/2
Output Skew, All Outputs (2,5)
—
—
350
ps
ps
ns
ns
ns
ps
ms
ns
500
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter (4)
TCY/2 − 0.4
TCY/2 − 0.4
− 0.15
− 500
—
TCY/2 + 0.4
TCY/2 + 0.4
0.15
0
tPD
SYNC Input to Feedback Delay (6)
tLOCK
SYNC to Phase Lock
10
7
tPZH
tPZL
tPHZ
tPLZ
tR, tF
Output Enable Time, OE/RST LOW to HIGH (3)
0
Output Enable Time, OE/RST HIGH to LOW (3)
0
6
ns
ns
Output Rise/Fall Times, 0.8V 2V
0.3
1.5
NOTES:
1. See Test Loads and Waveforms for test load and termination. Test circuit 1 is used for output enable/disable parameters. Test circuit 2 is used for all
other timing parameters.
2. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input
frequencies.
5. Skew measured at selected synchronization edge.
6. tPD measured at device inputs at 1.5V, Q output at 80MHz.
5
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TEST LOADS AND WAVEFORMS
VDD
300Ω
160Ω
7.0V
OUTPUT
OUTPUT
300Ω
30pF
20pF
68
Ω
TEST CIRCUIT 1
TEST CIRCUIT 2
1.0ns
1.0ns
tR
tF
3.0V
2.0V
2.0V
1.5V
0.8V
Vth = 1.5V
tPW
0.8V
0V
0V
TTL INPUT TEST WAVEFORM
TTLOUTPUTWAVEFORM
ENABLE
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPLZ
tPZL
OUTPUT
NORMALLY
LOW
3.5V
SWITCH
CLOSED
1.5V
1.5V
VOL
VOH
0.3V
0.3V
tPHZ
tPZH
SWITCH
OPEN
OUTPUT
NORMALLY
HIGH
0V
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
6
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TIMING DIAGRAM
SYNC
tPD
FEEDBACK
tJ
Q
tSKF
Q0-Q4
tSKR
Q/2
2xQ
tSKALL
Q
5
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the
negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.
2. All parameters are measured at 1.5V.
7
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PLLOPERATION
The Phase Locked Loop (PLL) circuit included in the QS5919T
providesforreplicationofincomingSYNCclocksignals.Anymanipulation
ofthatsignal,suchas frequencymultiplyingorinversionis performedby
digitallogicfollowingthePLL(seetheblockdiagram).Thekeyadvantage
ofthePLLcircuitistoprovideaneffectivezeropropagationdelaybetween
the outputandinputsignals.Infact,addingdelaycircuits inthe feedback
path, ‘propagationdelay’canevenbe negative!Asimplifiedschematic
of the QS5919T PLL circuit is shown below.
SIMPLIFIEDDIAGRAMOFQS5919TFEEDBACK
2xQ
Q
Q/2
Q
INPUT
VCO
/2
/2
PHASE
DETECTOR
The phase difference between the output and the input frequencies
feeds the VCOwhichdrives the outputs.Whicheveroutputis fedback,it
will stabilize at the same frequency as the input. Hence, this is a true
negativefeedbackclosedloopsystem.Inmostapplications,theoutputwill
optimallyhavezerophaseshiftwithrespecttotheinput.Infact,theinternal
loopfilteronthe QS5919Ttypicallyprovides within150ps ofphase shift
betweeninputandoutput.
Iftheuserwishes tovarythephasedifference(typicallytocompensate
forbackplane delays), this is mosteasilyaccomplishedbyaddingdelay
circuits tothefeedbackpath.Therespectiveoutputusedforfeedbackwill
beadvancedbytheamountofdelayinthefeedbackpath.Allotheroutputs
willretaintheirproperrelationships tothatoutput.
8
QS5919T
INDUSTRIALTEMPERATURERANGE
LOWSKEWTTLPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
ORDERINGINFORMATION
QS
XXXX
X
XX
Package
Device Type
Speed
Q
J
Quarter Size Outline Package (SO28-9)
Plastic Leaded Chip Carrier (J28-1)
55
70
100
133
160
55MHz Max. Frequency
70MHz Max. Frequency
100MHz Max. Frequency
133MHz Max. Frequency
160MHz Max. Frequency
Low Skew TTL PLL Clock Driver with Integrated Loop Filter
5919T
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Turboclock is a registered trademark of Integrated Device Technology, Inc.
9
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