QS5LV931-50Q [IDT]
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER; 具有集成环路滤波器3.3V低偏移CMOS PLL时钟驱动器
| 型号： | QS5LV931-50Q |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 文件： | 总8页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
QS5LV931
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION:
• 3.3V operation
The QS5LV931 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q0–Q4, Q/2. Careful layout and design ensure <300ps
skew between the Q0–Q4, and Q/2 outputs. The QS5LV931 includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5LV931 is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe systems.
Several can be used in parallel or scattered throughout a system for
guaranteed low skew, system-wide clock distribution networks. In the
QSOP package, the QS5LV931 clock driver represents the best value
in small form factor, high-performance clock management products.
For more information on PLL clock driver products, see Application
Note AN-227.
• JEDEC LVTTL compatible level
• Clock input is 5V tolerant
• Q outputs, Q/2 output
• <300ps output skew, Q0–Q4
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Internal VCO/2 option
• Balanced drive outputs ±24mA
• ESD >2000V
• 80MHz maximum frequency
• Available in QSOP package
FUNCTIONALBLOCKDIAGRAM
FEEDBACK
PLL_EN
FREQ_SEL
SYNC
OE/RST
0
1
1
0
PHASE
LOOP
VCO
/2
DETECTOR
FILTER
R
D
R
D
R
D
R
D
R
D
R
Q
D
Q
Q
Q
Q
Q
Q
Q/2
Q4
Q3
Q2
Q1
Q0
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2002
1
c
2002 Integrated Device Technology, Inc.
DSC-5821/2
QS5LV931
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
AVDD/VDD Supply Voltage to Ground
DC Input Voltage VIN
–0.5 to +7
–0.5 to +5.5
0.5
V
GND
OE/RST
1
2
3
4
5
6
7
8
9
10
Q4
20
19
18
17
16
15
14
13
12
11
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
W
Q/2
GND
Q3
TSTG
–65 to +150
°C
FEEDBACK
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
AVDD
VDD
VDD
Q2
AGND
SYNC
GND
PLL_EN
GND
Q1
FREQ_SEL
GND
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)
Q1
Pins
CIN
Typ.
Max.
Unit
pF
3
4
4
5
COUT
pF
QSOP
TOP VIEW
PINDESCRIPTION
Pin Name
SYNC
I/O
Description
Referenceclockinput
I
I
FREQ_SEL
VCOfrequencyselect. ForchoosingoptimalVCOoperatingfrequencydependingoninputfrequency. HIGHisforhigherfrequencies,
LOWisforlowerfrequencies.
FEEDBACK
I
PLLfeedbackinputwhichisconnectedtoeitheraQoraQ/2output. Externalfeedbackprovidesflexibilityfordifferentoutputfrequency
relationships.SeetheFrequencySelectionTableformoreinformation.
Clockoutputs
Q0 -Q4
Q/2
O
O
I
Clockoutput. Matchedinphase, butfrequencyishalftheQfrequency.
Outputenable/asynchronousreset.Resetsalloutputregisters.When0,alloutputsareheldinatri-statedcondition.When1,outputsare
enabled.
OE/RST
PLL_EN
VDD
I
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
Powersupplyforoutputbuffers
—
—
—
—
AVDD
GND
Powersupplyforphaselockloopandotherinternalcircuitries
Groundsupplyforoutputbuffers
AGND
Groundsupplyforphaselockloopandotherinternalcircuitries
OUTPUTFREQUENCYSPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V
Symbol
FMAX_Q
FMAX_Q/2
FMIN_Q
Description
– 50
50
25
10
5
– 66
66
33
10
5
– 80
80
40
10
5
Units
MHz
MHz
M H z
MHz
Max Frequency, Q0 - Q4,
Max Frequency, Q/2
Min Frequency, Q0 - Q4
Min Frequency, Q/2
FMIN_Q/2
2
QS5LV931
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
FREQUENCYSELECTIONTABLE
SYNC (MHz)
Output Used for
Feedback
Q/2
(allowablerange)(1)
OutputFrequencyRelationships
FREQ_SEL
HIGH
Min.
Max
Q/2
Q0 - Q4
SYNC X 2
SYNC
FMIN_Q/2
FMIN_Q
FMAX_Q/2
FMAX_Q
SYNC
HIGH
Q0 -Q4
SYNC / 2
SYNC
LOW
Q/2
FMIN_Q/2/2
FMIN_Q /2
FMAX_Q/2/2
FMAX _Q /2
SYNC X 2
SYNC
LOW
Q0 -Q4
SYNC / 2
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_Q x2. Operation with Sync inputs outside specified
frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V
Symbol
VIH
Parameter
Conditions
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
IOH = −24mA
Min.
Typ.
—
Max.
—
Unit
V
Input HIGH Voltage
InputLOWVoltage
Output HIGH Voltage
2
VIL
—
—
0.8
—
V
VOH
VDD — 0.6
—
V
IOH = −100µA
VDD — 0.2
—
—
VOL
OutputLOWVoltage
VDD = Min., IOL = 24mA
VDD = Min., IOL = 100µA
—
—
—
—
—
—
0.45
0.2
—
V
—
VH
InputHysteresis
100
—
mV
IOZ
OutputLeakageCurrent
VOUT = VDD or GND,
VDD = Max., Outputs Disabled
AVDD = Max., VIN = AVDD or GND
5
µA
IIN
InputLeakageCurrent
—
—
5
µA
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions
VDD = Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
VDD = Max., VIN = 3V
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
—
1
mA
∆IDD
Power Supply Current per Input HIGH
1
30
µA
IDDD
Dynamic Power Supply Current per Output
VDD = Max., CL = 0pF
0.2
0.3
µA/MHz
INPUTTIMINGREQUIREMENTS
Symbol
tR, tF
FI
Description(1)
Maximum input rise and fall times, 0.8V to 2V
Min.
—
Max.
Unit
ns
3
FMAX_Q
—
(1)
Input Clock Frequency, SYNC
2.5
2
MHz
ns
tPWC
DH
Input clock pulse, HIGH or LOW (2)
(2)
Duty Cycle, SYNC
25
75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL
combinations.
2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
3
QS5LV931
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
tSKR
tSKF
tPW
Parameter (1)
Output Skew Between Rising Edges, Q0-Q4 and Q/2 (2)
Output Skew Between Falling Edges, Q0-Q4 and Q/2(2)
Pulse Width, Q0-Q4, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter (4)
Min.
Max.
300
Unit
ps
—
—
300
ps
TCY/2 −0.4
— 0.15
−500
—
TCY/2 + 0.4
0.15
ns
tJ
ns
tPD
SYNC Input to Feedback Delay (5)
500
ps
tLOCK
tPZH
tPZL
tPHZ
tPLZ
tR,tF
SYNC to Phase Lock
10
ms
ns
Output Enable Time, OE/RST LOW to HIGH (3)
0
14
Output Disable Time, OE/RST HIGH to LOW (3)
Output Rise/Fall Times, 0.8V ~2V
0
14
2
ns
ns
0.3
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
4
QS5LV931
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
AC TEST LOADS AND WAVEFORMS
VDD
300Ω
100Ω
6.0V
OUTPUT
OUTPUT
300Ω
30pF
100Ω
Test Circuit 1
Test Circuit 2
1.0ns
1.0ns
tR
tF
3.0V
2.0V
3.0V
2.0V
tPW
Vth = 0.5VDD
0.8V
0.5VDD
0.8V
0V
0V
CMOS Input Test Waveform
CMOS Output Waveform
ENABLE
DISABLE
3V
0.5VDD
0V
CONTROL
INPUT
tPLZ
tPZL
OUTPUT
NORMALLY
LOW
3.0V
SWITCH
CLOSED
0.5VDD
VOL
VOH
0.3V
0.3V
tPHZ
tPZH
SWITCH
OPEN
0.5VDD
OUTPUT
NORMALLY
HIGH
0V
Enable and Disable Times
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
5
QS5LV931
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
AC TIMING DIAGRAM
SYNC
tPD
FEEDBACK
tJ
Q
tSKF
Q0-Q4
tSKALL
tSKR
Q/2
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK .
2. All parameters are measured at 0.5VDD.
6
QS5LV931
INDUSTRIALTEMPERATURERANGE
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
PLLOPERATION
The Phase Locked Loop (PLL) circuit included in the QS5LV931 circuitistoprovideaneffectivezeropropagationdelaybetweentheoutput
providesforreplicationofincomingSYNCclocksignals. Anymanipulation and input signals. In fact, adding delay circuits in the feedback path,
of that signal, such as frequency multiplying, is performed by digital logic ‘propagation delay’ can even be negative! A simplified schematic of the
following the PLL (see the block diagram). The key advantage of the PLL QS5LV931 PLL circuit is shown below.
SIMPLIFIEDDIAGRAMOFQS5LV931FEEDBACK
Q
Q/2
INPUT
/2
VCO/2
PHASE
DETECTOR
Thephasedifferencebetweentheoutputandtheinputfrequenciesfeeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedbackclosedloopsystem.Inmostapplications,theoutputwilloptimally
havezerophaseshiftwithrespecttotheinput.Infact,theinternalloopfilter
on the QS5LV931 typically provides within 150ps of phase shift between
inputandoutput.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
beadvancedbytheamountofdelayinthefeedbackpath. Allotheroutputs
will retain their proper relationships to that output.
7
QS5LV931
3.3VLOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
QS
X
XXXX
XX
Package
Device Type
Speed
Process
Industrial (-40°C to +85°C)
Blank
Q
Quarter Size Outline Package
50
66
80
50MHz Max. Frequency
66MHz Max. Frequency
80MHz Max. Frequency
3.3V Low Skew CMOS PLL Clock
Driver with Integrated Loop Filter
5LV931
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
8
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