QS5V9910-2SOC [IDT]
PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 0.300 INCH, SOIC-24;
| 型号： | QS5V9910-2SOC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 0.300 INCH, SOIC-24 光电二极管 |
| 文件： | 总6页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V LOW SKEW
QS5V9910
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
FEATURES:
DESCRIPTION
•
•
•
•
•
•
EightzerodelayLVTTLoutputs
<250ps ofoutputtooutputskew
Selectable positive ornegative edge synchronization
Synchronous outputenable
Outputfrequency:25MHzto70MHz
3 skew grades:
TheQS5V9910isahighfanoutphaselocked-loopclockdriverintended
forhighperformancecomputinganddata-communicationsapplications.It
has eight zero delay LVTTL outputs.
Whenthe GND/sOEpinis heldlow,allthe outputs are synchronously
enabled.However,ifGND/sOEis heldhigh,alltheoutputs exceptQ2 and
Q3 are synchronouslydisabled.
QS5V9910-2:tSKEW0<250ps
QS5V9910-5:tSKEW0<500ps
QS5V9910-7:tSKEW0<750ps
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of
REF.
•
•
•
•
•
•
3-level input for PLL range control
PLL bypass for DC testing
Externalfeedback,internalloopfilter
12mAbalanceddrive outputs
LowJitter:<200ps peak-to-peak
Available inSOICPackage
TheFBsignaliscomparedwiththeinputREFsignalatthephasedetector
inordertodrive the VCO.Phase differences cause the VCOofthe PLLto
adjust upwards or downwards accordingly.
Aninternalloopfiltermoderates the response ofthe VCOtothe phase
detector. The loop filter transfer function has been chosen to provide
minimal jitter (or frequency variation) while still providing accurate re-
sponses toinputfrequencychanges.
FUNCTIONALBLOCKDIAGRAM
VCCQ/PE
GND/sOE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FB
PLL
REF
FS
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
MARCH 2000
1
c
2000 Integrated Device Technology, Inc.
DSC-5808/-
QS5V9910
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Rating
Max.
Unit
Supply Voltage to Ground
–0.5 to +7
V
VI
DC Input Voltage
–0.5 to VCC+0.5
–0.5 to +5.5
530
V
V
1
2
3
GND
TEST
NC
REF
VCCQ
FS
24
23
22
21
20
19
18
17
16
15
14
13
REF Input Voltage
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
mW
TSTG
–65°C to +150°C °C
GND/sOE
VCCN
Q7
4
5
NC
NOTE:
VCCQ/PE
VCCN
Q0
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
6
SO24-2
7
Q6
8
GND
Q5
Q1
9
GND
Q2
10
11
12
Q4
CAPACITANCE (T = 25 C, f = 1MHz, V = 0V)
Parameter
°
A
IN
VCCN
FB
Q3
Description
Input Capacitance
Typ. Max. Unit
VCCN
CIN
5
7
pF
NOTE:
SOIC
TOP VIEW
1. Capacitance applies to all inputs except TEST and FS. It is
characterized but not production tested.
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
Feedback Input
FB
IN
TEST (1)
GND/ sOE (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as
the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
VCCQ/PE
FS (2)
IN
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
Frequency range select.
FS = GND: 25 to 35MHz.
FS = MID (or open): 35 to 60MHz
FS = VCC: 60 to 70MHz
8 clock output
Q0 - Q7
VCCN
OUT
PWR
PWR
PWR
Power supply for output buffers
VCCQ
Power supply for phase locked loop and other internal circuitry
Ground
GND
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL
may require an additional lock time before all data sheet limits are achieved.
2
QS5V9910
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
RECOMMENDED OPERATING RANGE
QS5V9910-5, -7
(Industrial)
QS5V9910-2
(Commercial)
Symbol
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
Max.
Min.
Max.
Unit
Vcc
3
3.6
3
3.6
V
TA
-40
+85
0
+70
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Input HIGH Voltage
Conditions
Min.
Max.
Unit
VIH
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
—
V
V
VIL
Input LOW Voltage
Input HIGH Voltage (1)
Input MID Voltage (1)
Input LOW Voltage (1)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
—
VCC−0.6
VCC/2−0.3
—
0.8
—
VIHH
VIMM
VILL
IIN
V
3-Level Inputs Only
VCC/2+0.3
0.6
V
3-Level Inputs Only
V
Input Leakage Current
(REF, FB Inputs Only)
VIN = VCC or GND
VCC = Max.
—
±5
µA
VIN = VCC
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.2
—
±200
±50
I3
3-Level Input DC Current (TEST, FS)
VIN = VCC/2
µA
VIN = GND
±200
±100
±100
—
IPU
Input Pull-Up Current (VCCQ/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
VCC = Max., VIN = GND
VCC = Max., VIN = VCC
VCC = Min., IOH = −12mA
VCC = Min., IOL = 12mA
µA
µA
V
IPD
VOH
VOL
Output LOW Voltage
0.55
V
NOTE:
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are
switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are
achieved.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
ICCQ
Quiescent Power Supply Current
VCC = Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
8
25
mA
∆ICC
ICCD
ITOT
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
V
CC = Max., V = 3V
1
30
90
—
—
—
µA
µA/MHz
mA
IN
VCC = Max., CL = 0pF
55
34
42
76
VCC = 3.3V, FREF = 25MHz, CL = 160pF (1)
VCC = 3.3V, FREF = 33MHz, CL = 160pF (1)
VCC = 3.3V, FREF = 66MHz, CL = 160pF (1)
mA
mA
NOTE:
1. For eight outputs, each loaded with 30pF.
3
QS5V9910
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
—
10
ns/V
tPWC
DH
3
—
90
70
ns
%
10
25
REF
Reference Clock Input
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
QS5V9910-2
Typ. Max.
QS5V9910-5
QS5V9910-7
Symbol
Parameter
REF Frequency Range
Min.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FREF
FS = LOW
FS = MID
FS = HIGH
25
—
—
—
—
—
0.1
—
0
35
60
25
—
35
25
—
35
MHz
35
60
35
60
—
—
—
—
0.25
—
0
60
70
35
60
—
—
—
—
0.3
—
0
60
70
70
tRPWH
tRPWL
tSKEW
tDEV
REF Pulse Width HIGH (7)
REF Pulse Width LOW (7)
3
—
—
—
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
3
—
—
—
3
—
Zero Output Skew (All Outputs) (1,3)
Device-to-Device Skew (1,2,4)
REF Input to FB Propagation Delay (1,6)
Output Duty Cycle Variation from 50% (1)
Output Rise Time (1)
—
0.25
0.75
0.25
1.2
1.8
1.8
0.5
25
—
0.5
1.25
0.5
1.2
1.8
1.8
0.5
40
—
0.75
1.65
0.7
1.2
2.5
2.5
0.5
40
—
—
—
tPD
−0.25
−1.2
0.15
0.15
—
−0.5
−1.2
0.15
0.15
—
−0.7
−1.2
0.15
0.15
—
tODCV
tORISE
tOFALL
tLOCK
tJR
0
0
0
1
1
1.5
1.5
—
—
—
Output Fall Time (1)
1
1
PLL Lock Time (1,5)
—
—
—
—
—
—
Cycle-to-Cycle Output Jitter (1) RMS
—
—
—
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing tolerances apply for FNOM ≥25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outputs. See AC test loads.
4. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
5. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
6. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
7. Refer to Input Timing Requirements for more detail.
4
QS5V9910
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
AC TEST LOADS AND WAVEFORMS
≤ 1ns
≤ 1ns
VCC
3.0V
2.0V
Vth =1.5V
0.8V
150Ω
0V
Output
LVTTL INPUT TEST WAVEFORM
150Ω
20pF
tOFALL
tORISE
TESTLOAD
2.0V
0.8V
LVTTLOUTPUTWAVEFORM
AC TIMING DIAGRAM
tREF
tRPWH
tRPWL
REF
tPD
tODCV
tODCV
FB
tJR
Q
tSKEW
tSKEW
OTHER Q
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with
75Ω to VCC/2.
tSKEW: The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow,
etc.)
tODCV: The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
5
QS5V9910
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
ORDERINGINFORMATION
XXXXX
XX
X
QS
Package Process
Device Type
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
C
I
Small Outline IC (300-mil) (SO24-2)
SO
3.3V Low Skew PLL Clock Driver TurboClock Jr.
5V9910-2
5V9910-5
5V9910-7
CORPORATE HEADQUARTERS
for SALES:
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Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Turboclock is a registered trademark of Integrated Device Technology, Inc.
6
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