VF2510BGILF [IDT]

TSSOP-24, Tube;


型号：	VF2510BGILF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	TSSOP-24, Tube 驱动光电二极管逻辑集成电路
文件：	总9页 (文件大小：123K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICSVF2510

Integrated

Circuit

Systems,Inc.

3.3V Phase-Lock Loop Clock Driver

General Description

Features

TheICSVF2510isahighperformance, lowskew, lowjitter

clock driver.It uses a phase lock loop (PLL) technology to

align, in both phase and frequency, the CLKIN signal with

the CLKOUT signal.It is specifically designed for use with

synchronousSDRAMs.TheICSVF2510 operatesat3.3V

VCC and drives up to ten clock loads.

•

Meets or exceeds PC133 registered DIMM

specification1.1

•

Spread Spectrum Clock Compatible

Distributes one clock input to one bank of ten outputs

Operating frequency 20MHz to 200MHz

External feedback input (FBIN) terminal is used to

synchrionize the outputs to the clock input

No external RC network required

Operates at 3.3V Vcc

Plastic 24-pin 173mil TSSOP package

Industrial temperature version available

One bank of ten outputs provide low-skew, low-jitter

copies of CLKIN. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLKIN.

Outputs can be enabled or disabled via control (OE)

inputs. When the OE inputs are high, the outputs align in

phaseandfrequencywithCLKIN;whentheOEinputsare

low, the outputs are disabled to the logic low state.

•

The ICSVF2510 does not require external RC filter

components.TheloopfilterforthePLLisincludedon-chip,

minimizing component count, board space, and cost.The

test mode shuts off the PLL and connects the input

directlytotheoutputbuffer.Thistestmode, theICSVF2510

can be use as low skew fanout clock buffer device. The

ICSVF2510 comes in 24 pin 173mil Thin Shrink Small-

Outline package (TSSOP) package.

Block Diagram

Pin Configuration

AGND 1

VCC 2

24 CLKIN

23 AVCC

22 VCC

21 CLK9

20 CLK8

19 GND

18 GND

17 CLK7

16 CLK6

15 CLK5

14 VCC

13 FBIN

FBOUT

CLK0 3

CLK1 4

CLK2 5

GND 6

GND 7

CLK3 8

CLK4 9

VCC 10

OE 11

CLK0

CLK1

CLK2

FBIN

PLL

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

CLK9

CLKIN

FBOUT 12

24 Pin TSSOP

4.40 mm. Body, 0.65 mm. Pitch

AVCC

0722B—05/06/04

ICSVF2510

Pin Descriptions

PIN #

2, 10, 14

PIN NAME

AGND

VCC

CLK0

CLK1

CLK2

TYPE

PWR

OUT

PWR

OUT

DESCRIPTION

Analog Ground

Power Supply (3.3V)

Buffered clock output.

Ground

6, 7, 18, 19 GND

CLK3

CLK4

Buffered clock output.

Output enable (has internal pull_up). When high, normal operation.

When low, clock outputs are disabled to a logic low state.

OE¹

FBOUT

FBIN

OUT

Feedback output

Feedback input

Buffered clock output.

Power Supply (3.3V) digital supply.

Analog power supply (3.3V). When input is ground PLL is off and

bypassed.

CLK5

CLK6

CLK7

CLK8

CLK9

VCC

OUT

PWR

AVCC

CLKIN

Clock input

Note:

1. Weak pull-ups on these inputs

Functionality

INPUTS

OUTPUTS

PLL

AVCC

CLK (9:0)

FBOUT

Source Shutdown

3.33

Driven

PLL

Driven

Buffer Mode

Driven

CLKIN

Driven

Test mode:

When AVCC is 0, shuts off the PLL

and connects the input directly to the output buffers

0722B—05/06/04

ICSVF2510

Absolute Maximum Ratings

Supply Voltage (AVCC). . . . . . . . . . . . . . . . . AVCC < (V_cc+ 0.7 V)

SupplyVoltage (VCC) . . . . . . . . . . . . . . . . . . 4.3 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_cc+ 0.5 V

Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C

StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These

ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - OUTPUT

T_A= 0 - 70°C; V_DD= V_DDL= 3.3 V +/-10%; C_L= 30 pF; R_L= 500 Ohms (unless otherwise stated)

PARAMETER

SYMBOL

V_OH

CONDITIONS

MIN

2.4

TYP

2.9

0.25

MAX UNITS

Output High Voltage

Output Low Voltage

I_OH= -8 mA

I_OL= 8 mA

V_OL

0.4

_OH= 2.4 V

_OH= 2.0 V

_OL= 0.8 V

_OL= 0.55 V

Output High Current

I_OH

I_OL

Output Low Current

Rise Time¹

Fall Time¹

Duty Cycle¹

T_r

T_f

V_OL= 0.8 V, V_OH= 2.0 V

V_OH= 2.0 V, V_OL= 0.8 V

V_T= 1.5 V;C_L=30 pF

0.5

1.1

2.1

2.7

D_t

Cycle to Cycle jitter¹

Absolute Jitter¹

Skew¹

Phase error¹

Delay Input-Output¹

at 66-100 MHz ; loaded outputs

10000 cycles; C_L= 30 pF

V_T= 1.5 V (Window) Output to Output

V_T= Vdd/2; CLKIN-FBIN

V_T= 1.5 V; PLL_EN = 0

T_CYC- T_CYC

T_JABS

T_sk

100

T_pe

-75

D_R1

3.3

3.7

¹Guaranteed by design, not 100% tested in production.

0722B—05/06/04

ICSVF2510

Electrical Characteristics - Input & Supply

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-10% (unless otherwise stated)

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

V_DD+ 0.3

0.8

UNITS

V_IH

V_IL

I_IH

V_SS- 0.3

V_IN= V_DD

V_IN= 0 V;

0.1

100

I_IL

Operating current

Input Capacitance

I_DD

C_L= 0 pF; F_IN@ 66MHz

Logic Inputs

170

C_IN

¹Guaranteed by design, not 100% tested in production.

Timing requirements over recommended ranges of supply

voltage and operating free-air temperature

Symbol Parameter

Test Conditions

Min.

Max.

Unit

F_OP

Operating frequency

200

MHz

Input clock

frequency

Input clock

frequency duty

cycle

F_CLK

200

MHz

Stabilization time

After power up

µs

Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal.

In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK.

Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable.

0722B—05/06/04

ICSVF2510

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

500 Ω

30pF

Figure 1. Load Circuit for Outputs

Notes:

Figure 2. VoltageWaveforms

Propagation DelayTimes

1. C_Lincludes probe and jig capacitance.

2. All input pulses are supplied by generators having the following

characteristics: PRR ≤133MHz, Z_O= 50 Ω, T ≤ 1.2ns, T ≤ 1.2ns.

3. The outputs are measured one at a time with one transition per measurement.

Figure 3. Phase Error and Skew Calculations

0722B—05/06/04

ICSVF2510

General Layout Precautions:

An ICS2509C is used as an example. It is similar to the

ICSVF2510. The same rules and methods apply.

1) Use copper flooded ground on the top signal layer

under the clock buffer The area under U1 in figure 1

on the right is an example. Every ground pin goes to a

ground via. The vias are not visible in figure 1.

2) Use power vias for power and ground. Vias 20 mil or

larger in diameter have lower high frequency

impedance. Vias for signals may be minimum drill

size.

3) Make all power and ground traces are as wide as the

via pad for lower inductance.

4) VAA for pin 23 has a low pass RC filter to decouple

the digital and analog supplies. C9-12 may be replaced

with a single low ESR (0.8 ohm or less) device with

the same total capacitance. R2 may be replaced with a

ferrite bead. The bead should have a DC resistance of

at least 0.5 ohms. 1 ohm is better. It should have an

impedance of at least 300 ohms at 100MHz. 600 ohms

at 100MHz is better.

Figure 1.

5) Notice that ground vias are never shared.

6) All VCC pins have a decoupling capacitor. Power is

always routed from the plane connection via to the

capacitor pad to the VCC pin on the clock buffer.

7) Component R1 is located at the clock source.

8) Component C1, if used, has the effect of adding delay.

9) Component C7 , if used, has the effect of subtracting

delay. Delaying the FBIn clock will cause the output

clocks to be earlier. A more effective method is to use

the propagation time of a trace between FBOut and

FBIn.

Component Values:

C1,C7= As necessary for delay

adjust

C[6:2]=.01uF

C8,C13=0.1uF

C[12:9]=4.7Uf

R1=10 ohm. Locate at driver

R2=10 ohm.

0722B—05/06/04

ICSVF2510

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

0.80

0.19

0.09

MAX

1.20

0.15

1.05

0.30

0.20

MIN

.002

.032

.007

.0035

MAX

.047

.006

.041

.012

.008

INDEX

AREA

SEE VARIATIONS

6.40 BASIC

SEE VARIATIONS

0.252 BASIC

4.30

0.65 BASIC

0.45

4.50

.169

0.0256 BASIC

.018

.177

0.75

.030

SEE VARIATIONS

aaa

0°

8°

0.10

0°

8°

.004

VARIATIONS

D mm.

D (inch)

MIN

7.70

MAX

7.90

MIN

.303

MAX

.311

- C -

SEATING

PLANE

Reference Doc.: JEDEC Publication 95, MO-153

10-0035

aaa

4.40 mm. Body, 0.65 mm. pitch TSSOP

(0.0256Inch)

(173 mil)

Ordering Information

ICSVF2510yGLF-T

Example:

ICS XXXX y G LF- T

Designation for tape and reel packaging

Lead Free (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

0722B—05/06/04

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VF2510BGILF [IDT]

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