XAH325125I [IDT]
XA Family of Low Phase Noise Quartz-based PLL Oscillators;
| 型号： | XAH325125I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | XA Family of Low Phase Noise Quartz-based PLL Oscillators |
| 文件： | 总20页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XA Family of Low Phase Noise
Quartz-based PLL Oscillators
XA
Datasheet
Description
Features
▪ Conforms to AEC-Q200
The IDT XA devices are ultra-precision crystal oscillators with 750
to 890fs typical phase jitter over 12kHz to 20MHz bandwidth.
Available in a wide frequency range from 0.750MHz to 1350MHz,
the XA series crystal oscillators utilize a family of proprietary
ASICs, with a key focus on noise reduction technologies.
▪ Frequency range: 0.750MHz to 1350MHz
▪ Output types: LVDS, LVPECL, LVCMOS
▪ Frequency stability: ±25, ±50, or ±100 ppm
▪ Supply voltage: 2.5V or 3.3V
The 3rd order Delta Sigma Modulator reduces noise to the levels
that are comparable to traditional Bulk Quartz and SAW
oscillators. With short lead-time, low cost, low noise, wide
frequency range, excellent ambient performance, the XA devices
are an excellent choice over the conventional technologies. The
XA devices have stabilities as tight as ±25ppm with extremely
quick delivery for both standard and custom frequencies.
▪ Phase jitter (12kHz to 20MHz): 750fs to 890fs typical
▪ Package options:
ꢀ 3.2 × 2.5 × 1.0 mm
ꢀ 5.0 × 3.2 × 1.2 mm
▪ Operating temperature: -40°C to +85°C (Grade 3)
ꢀ Frequency stability options: ±25, ±50, or ±100 ppm
▪ Operating temperature: -40°C to +105°C (Grade 2)
ꢀ Frequency stability options: ±50 or ±100 ppm
Pin Assignments
NOTE: To minimize power supply line noise, a 0.01μF bypass
capacitor should be placed between VDD (Pin 6) and GND (Pin 3)
on 6-pin devices, or VDD (Pin 4) and GND (Pin 2) on 4-pin
devices.
4
1
3
6
1
5
4
2
2
3
Table 2. 4-pin Package
Table 1. 6-pin Package
Pin # Pin Name
Description
Pin # Pin Name
Description
[a,b]
[a,b]
1
2
3
4
E/D
GND
OUT
Enable/Disable
1
2
3
4
5
6
E/D
NC
Enable/Disable
No connect
Connect to ground
Output
GND
OUT
OUT2
Connect to ground
Output
V
Supply voltage
DD
Complementary output
Supply voltage
[a] Pulled high internally.
[b] Low = output disabled.
V
DD
See Ordering Information for more details.
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Waveforms – LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Waveforms – LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Waveforms – LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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XA Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for IDT
commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Table 3. Absolute Maximum Ratings
Item
Rating
V
-0.5 to +5.0V
-0.5V to V + 0.5V
DD
E/D
DD
OUT
-0.5V to V + 0.5V
DD
Storage Temperature
Maximum Junction Temperature
Core Current
-55°C to 125°C
125°C
65mA maximum
Theta J
89.6 °C/W
54.3 °C/W
94.7 °C/W
66.8 °C/W
JS6
JX6
A
5.0 × 3.2 × 1.2 mm
3.2 × 2.5 × 1.0 mm
Theta J
B
ESD Compliance
Human Body Model (HBM)
Machine Model (MM)
1000V
150V
Mechanical Testing
Parameter
Test Method
Drop from 75cm to hardwood surface–3 times.
Mechanical Shock
Mechanical Vibration
High Temperature Burn-in
Hermetic Seal
10–55Hz, 1.5mm amplitude, 1 minute sweep; 2 hours each in 3 directions (X, Y, Z).
Under power at 125°C for 2000 hours.
2
He pressure: 4 ±1kgf/cm 2 hour soak.
Solder Reflow Profile
tP
10 seconds Max within
5°C of 260°C peak
260°C
Ramp up 3°C/s Max
Ramp down not
to exceed 6°C/s
225°C
180°C
50 ±10
seconds
above 225°C
reflow area
120 ±20 seconds
in pre-heating
area
160°C
25°C
400 seconds MAX from +25°C to 260°C peak
©2018 Integrated Device Technology, Inc.
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XA Datasheet
DC Electrical Characteristics
Table 4. 3.3V IDD DC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Output Type
Conditions
Minimum
Typical
Maximum
Units
LVDS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
120
32
LVPECL
—
0.75MHz to 20MHz.
20+MHz to 50MHz.
50+MHz to 130MHz.
130+MHz to 200MHz.
200+MHz to 250MHz.
I
Power Supply Current
35
mA
DD
LVCMOS
47
55
60
Table 5. 2.5V IDD DC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Output Type
Conditions
Minimum
Typical
Maximum
Units
0.75MHz to 20MHz.
20+MHz to 220MHz.
220+MHz to 630MHz.
630+MHz to 1000MHz.
0.75MHz to 20MHz.
20+MHz to 220MHz.
220+MHz to 630MHz.
630+MHz to 1000MHz.
0.75MHz to 20MHz.
20+MHz to 50MHz.
50+MHz to 100MHz.
100+MHz to 130MHz.
130+MHz to 160MHz.
160+MHz to 180MHz.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26
34
44
65
33
41
63
72
22
25
29
32
35
37
LVDS
LVPECL
I
Power Supply Current
mA
DD
LVCMOS
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XA Datasheet
Table 6. LVDS DC Electrical Characteristics
VDD = 3.3V, 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.
Symbol
Parameter
Differential Output Voltage
Conditions
Minimum
Typical
Maximum
Units
V
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 3.3V ±5%.
= 2.5V ±5%.
—
—
—
—
—
—
—
—
—
—
—
0.6
0.4
DD
DD
DD
DD
V
OD
1.3
V
Output Offset Voltage
V
OS
IH
1.25
—
V
Enable/Disable Input High Voltage (Output enabled)
Enable/Disable Input Low Voltage (Output disabled)
70% V
—
DD
V
—
30% V
IL
DD
Table 7. LVPECL DC Electrical Characteristics
VDD = 3.3V, 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.
Symbol
Parameter
Differential Output Voltage
Conditions
Minimum
Typical
Maximum
Units
V
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 3.3V ±5%.
= 2.5V ±5%.
—
2.055
—
2.405
—
DD
DD
DD
DD
V
OD
1.4
1.305
—
1.65
—
V
Output Offset Voltage
V
OS
IH
0.68
—
V
Enable/Disable Input High Voltage (Output enabled)
Enable/Disable Input Low Voltage (Output disabled)
70% V
—
—
DD
V
—
—
30% V
DD
IL
Table 8. LVCMOS DC Electrical Characteristics
VDD = 3.3V, 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.
Symbol
Parameter
Conditions
0.75MHz to 150MHz.
Minimum
Typical
Maximum Units
90% V
80% V
90% V
80% V
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
DD
DD
DD
V
V
V
V
= 3.3V ±5%.
= 2.5V ±5%.
= 3.3V ±5%.
= 2.5V ±5%.
DD
DD
DD
DD
150+MHz to 250MHz.
0.75MHz to 160MHz.
160+MHz to 180MHz.
0.75MHz to 150MHz.
150+MHz to 250MHz.
0.75MHz to 160MHz.
160+MHz to 180MHz.
V
Output High Voltage
OH
10% V
20% V
10% V
20% V
DD
DD
DD
DD
—
V
V
Output Low Voltage
OL
—
—
Enable/Disable Input High Voltage
(Output enabled)
V
—
—
—
—
70% V
—
—
—
—
IH
DD
Enable/Disable Input Low Voltage
(Output disabled)
V
30% V
IL
DD
©2018 Integrated Device Technology, Inc.
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XA Datasheet
AC Electrical Characteristics
Table 9. 3.3V AC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum Units
LVDS.
0.75
0.75
0.75
±25
±50
—
—
—
1350
F
Output Frequency Range
LVPECL.
LVCMOS.
1350
250
±100
±100
±3
MHz
—
Temperature = -40°C to +85°C.
Temperature = -40°C to +105°C.
—
ppm
ppm
ppm
ppm
Frequency Stability
—
Aging (1st year)
Aging (10 years)
T = 25°C.
—
A
T = 25°C.
—
—
±10
—
A
LVDS.
Differential.
- 2.0V.
—
100
50
15
Ω
Output Load
LVPECL.
LVCMOS.
V
—
—
DD
To GND.
—
—
pF
Output valid time after V meets minimum
specified level.
DD
T
Start-up Time
Output Rise Time
—
—
10
ms
ST
LVDS.
—
—
—
—
—
—
45
45
45
40
—
—
—
—
—
—
—
—
—
—
—
—
400
400
3
20% to 80% Vpp.
LVPECL.
ps
ns
ps
ns
t
R
LVCMOS.
LVDS.
10% to 90% V
—
DD.
—
400
400
3
80% to 20% Vpp.
90% to 10% V
t
Output Fall Time
LVPECL.
LVCMOS.
LVDS.
—
F
—
DD.
—
55
55
55
60
100
—
LVPECL.
—
O
Output Clock Duty Cycle
%
DC
F
F
< 62.5MHz.
> 62.5MHz.
—
OUT
OUT
LVCMOS.
—
T
Output Enable/ Disable Time
Period Jitter, RMS
—
—
ns
ps
OE
LVDS.
3
J
LVPECL.
LVCMOS.
LVDS.
5.8
5
—
PER
F
F
F
= 125MHz.
= 125MHz.
= 125MHz.
—
OUT
OUT
OUT
1.3
1.29
0.6
5.8
9.3
10
—
R
D
Random Jitter
LVPECL.
LVCMOS.
LVDS.
—
ps
ps
J
J
—
—
Deterministic Jitter
LVPECL.
LVCMOS.
—
—
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XA Datasheet
Table 9. 3.3V AC Electrical Characteristics (Cont.)
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum Units
LVDS.
—
—
—
—
—
—
23.6
27.7
19
—
T
Total Jitter
LVPECL.
LVCMOS.
LVDS.
—
—
—
—
—
ps
fs
J
F
F
= 125MHz.
= 125MHz.
OUT
OUT
890
860
750
f
Phase Jitter (12kHz–20MHz)
LVPECL.
LVCMOS.
JITTER
Table 10. 2.5V AC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum Units
LVDS.
0.75
0.75
0.75
±25
±50
—
—
—
1000
F
Output Frequency Range
LVPECL.
LVCMOS.
1000
180
±100
±100
±3
MHz
—
Temperature = -40°C to +85°C.
Temperature = -40°C to +105°C.
—
ppm
ppm
ppm
ppm
Frequency Stability
—
Aging (1st year)
Aging (10 years)
T = 25°C.
—
A
T = 25°C.
—
—
±10
—
A
LVDS.
Differential.
- 2.0V.
—
100
50
15
Ω
Output Load
LVPECL.
LVCMOS.
V
—
—
DD
To GND.
—
—
pF
Output valid time after V meets minimum
specified level.
DD
T
Start-up Time
Output Rise Time
—
—
10
ms
ST
LVDS.
—
—
—
—
—
—
45
45
45
—
—
—
—
—
—
—
—
—
—
—
400
400
3.5
400
400
3
20% to 80% Vpp.
LVPECL.
ps
ns
ps
ns
t
R
LVCMOS.
LVDS.
10% to 90% V
DD.
80% to 20% Vpp.
90% to 10% V
t
Output Fall Time
LVPECL.
LVCMOS.
LVDS.
F
DD.
55
O
Output Clock Duty Cycle
LVPECL.
LVCMOS.
55
%
DC
55
T
Output Enable/ Disable Time
—
100
ns
OE
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Table 10. 2.5V AC Electrical Characteristics (Cont.)
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum Units
LVDS.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
—
J
Period Jitter, RMS
LVPECL.
LVCMOS.
LVDS.
5.12
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ps
ps
ps
ps
fs
PER
F
F
F
F
F
= 125MHz.
= 125MHz.
= 125MHz.
= 125MHz.
= 125MHz.
OUT
OUT
OUT
OUT
OUT
1.4
R
D
Random Jitter
LVPECL.
LVCMOS.
LVDS.
1.36
1.3
J
J
J
9.2
Deterministic Jitter
Total Jitter
LVPECL.
LVCMOS.
LVDS.
10
6.7
29.2
29.3
25.6
1040
1200
850
T
LVPECL.
LVCMOS.
LVDS.
f
Phase Jitter (12kHz–20MHz)
LVPECL.
LVCMOS.
JITTER
Notes for all AC Electrical Characteristics tables:
1 All jitter values provided at 156.25MHz, unless noted otherwise.
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Output Waveforms – LVDS
Output Levels/Rise Time/Fall Time Measurements
TF
TR
OUTPUT 2
50% VPP
20% to 80% VPP
VOS
VOD
OUTPUT 1
Oscillator Symmetry
Ideally, Symmetry should be 50/50 for ½ period –Other expressions are 45/55 or 55/45
VOH
OUTPUT 2
50% VPP
OUTPUT 1
VOL
½ Period
Period
Output Waveforms – LVPECL
Rise Time/Fall Time Measurements
TF
TR
VOH
OUTPUT 2
20% to 80% VPP
OUTPUT 1
VOL
Oscillator Symmetry
VOH
OUTPUT 2
50% VPP
OUTPUT 1
VOL
½ Period
Period
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Output Waveforms – LVCMOS
Package Outline Draw ings
The package outline drawings are located at the end of this document. The package information is the most current data available.
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Ordering Information
XL
Family and ASIC
L
5
3
5
125.000000
Frequency
I
Output Type
Package
Voltage
Precision
Temperature Range
2: 2.5 VDC ±5%
3: 3.3 VDC ±5%
I: Industrial range: ‐ 40 to +85 °C (Grade 3)
K: Extended range :‐40 to +105 °C (Grade 2)
3: 3.2 x 2.5 mm
5: 5.0 x3.2 mm
125.000000 listed in MHz as example
3 digits before decimal and 6 digits after decimal
H: HCMOS Enable/Disable Pin1
L: LVDS Enable/Disable Pin 1
P: LVPECL Enable/Disable Pin1
000.750000 to 000.999999 75kHz to 999.999kHz
001.000000 to 009.999999 1MHz to 9.999999MHz
010.000000 to 099.999999 10MHz to 99.999999MHz
100.000000 to 999.999999 100MHz to 999.999999MHz
XA: 1,000 fs jitter
A00.000000 to A99.999999 1000MHz to1099.999MHz
B00.000000 to B99.999999 1100MHz to 1199.999MHz
C00.000000 to C99.999999 1200MHz to1299.999MHz
D00.000000 to D50.000000 1300MHz to 1350MHz
0: ±100ppm**
5: ±50ppm**
6: ±25ppm
** ±100ppm and ±50ppm for K (‐40°C to +105°C) only.
©2018 Integrated Device Technology, Inc.
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XA Datasheet
Revision History
Revision Date
Description of Change
May 24, 2018
April 27, 2018
Updated LVCMOS Output Clock Duty Cycle, FOUT test condition.
Initial release.
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1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
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without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
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of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
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