ZADCS1022VIS14T [IDT]
ADC, Successive Approximation, 10-Bit, 1 Func, 2 Channel, Serial Access, PDSO14;
| 型号： | ZADCS1022VIS14T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 2 Channel, Serial Access, PDSO14 光电二极管 转换器 |
| 文件： | 总26页 (文件大小：545K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev. 2.0 / October 2011
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Brief Description
Benefits
The ZMDI ZADCS1082/ZADCS1042/ZADCS1022
are 10-Bit low power analog-to-digital (A/D)
converters with up to 250ksps conversion rate.
The converter is based on successive-
approximation-register architecture.
Scalable system solutions possible due to
upward/downward compatibility within the family
( 8, 10, 12 bit resolution, 2, 4, 8 channels)
Accurate measurements
Long battery life cycles due to low power
All converters have an 8-channel input multiplexer
and a high-bandwidth a track/hold circuit. All
analog inputs are software configurable as eight /
four/two single ended or four/two/one differential
analog input channels as well as for unipolar or
bipolar output coding.
consumption
Synchronous sampling with several ZADCS
parts in parallel
Available Support
ZADCS1282 Kit
The ZADCS1082/ ZADCS1042/ ZADCS1022
operate from a single +2.7V to +5.25V supply.
The synchronous four wire serial interface
connects directly to a microcontroller using one of
the standards like SPI™, QSPI™, and Microwire™
without external components.
The ZADCS1082/ZADCS1042/ZADCS1022 use
either the external serial-interface clock or an
internally generated clock to perform successive-
approximation analog-to-digital conversions. The
internal clock mode can be used to run
synchronous conversions on several ZMDI ADCs
in parallel.
The “V” versions ZADCS1082V/ZADCS1042V/
ZADCS1022V are equipped with a high accurate
internal 2.5V reference with an additional external
±1.5% voltage adjustment range.
The device provides a hard-wired shut-down pin
(nSHDN) and software-selectable power-down
modes to automatically shut down the IC at the
end of a conversion. Accessing the serial interface
automatically powers up the ZADCS1082/
ZADCS1042/ZADCS1022. A quick turn-on time
allows the device to be shut down between
measurements.
- Evaluation Kit for ZMDI ZADCS10x2 Family
based on ZADCS1282 device
- Standalone and PC based operation modus
- USB 2.0 (1.1) compatible
- User Interface for PC operated modus
- Graphical oscilloscope appl. and FFT analyzer
Physical Characteristics
ADC resolution............................ 10 Bit
Conversion rate........................... 250 ksps
Power supply rate ....................... 2.7V to 5.25V
INL............................................... ±0.4 LSB max.
DNL............................................. ±0.4 LSB max.
SINAD......................................... >61 dB
Standby (idle) current.................. <0.5 µA
Current consumption @ 200 ksps, 3V supply
- with internal reference .............. < 1.2 mA
- without internal reference ......... < 0.9 mA
Temperature range ..................... -25°C to +85°C
14 / 16 / 20-Pin SSOP package
Features
10-Bit resolution SAR ADC
2/4/8 channel single or 1/2/4 channel diff. inputs
Software configurable uni- or bipolar output code
SPI™/QSPI™, Microwire™ compatible serial
interface
No missing codes
Low power consumption
Internal 2.5V reference (only “V” version -
ZADCS1082V/ ZADCS1042V/ZADCS1022V)
Software programmable power down mode
Single-Supply Operation +2.5V to +5.25V
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
The information furnished in this publication is PRELIMINARY and subject to changes without notice.
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Typical Applications
ZADCS1082 Block Diagram
Embedded control & real time appl.
Industrial control & process control
applications
CH0
CH1
SAR
CH2
8-Channel
Analog
Input
Multiplexer
Comparator
Motion control applications
Three phase motor control
CH3
CH4
IN
IN
+
-
CH5
CH6
CH7
nCS
+
-
Serial
Interface
and
Control
State
DAC
Power generation (Solar,
Windmills, etc.)
SCLK
DIN
with inherent
T&H
DOUT
SSTRB
nSHDN
Data Acquisition
COM
Machine
x 2.00
Portable Data Logging
Battery-Powered Systems
Automotive
+1.25V
Reference
Internal
3.2 MHz
Oscillator
VDD
REFADJ
VREF
DGND
AGND
Available in ZADCS1082V / ZADCS1042V / ZADCS1022V
Ordering Information
Order Code
ZADCS1082VIS20T
ZADCS1082IS20T
ZADCS1042VIS16T
ZADCS1042IS16T
ZADCS1022VIS14T
ZADCS1022IS14T
10
10
10
10
10
10
8
8
4
4
2
2
250
250
250
250
250
250
-25°C to +85°C
--
--
--
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
± 0,4 LSB
20
20
16
16
14
14
SSOP
Tube
Tube
Tube
Tube
Tube
Tube
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
SSOP
SSOP
SSOP
SSOP
SSOP
Sales and Further Information
www.zmdi.com
adc@zmdi.com
Zentrum Mikroelektronik
Dresden AG
Grenzstrasse 28
01109 Dresden
ZMD America, Inc.
8413 Excelsior Drive
Suite 200
Madison, WI 53717
USA
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Germany
Japan
Phone +49 (0)351.8822.7232
Phone +1 (608) 829-1987
Phone +81.3.6895.7410
Phone +886 2 2377 8189
Fax
+49 (0)351.8822.87232
Fax
+1 (631) 549-2882
Fax
+81.3.6895.7301
Fax
+886 2 2377 8199
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum
Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be
true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential
damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any
liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any
damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or
otherwise.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
The information furnished in this publication is PRELIMINARY and subject to changes without notice.
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Contents
1
General Device Specification ..............................................................................................................................7
1.1. Absolute Maximum Ratings (Non Operating)...............................................................................................7
1.2. Package Pin Assignment ZADCS1082 / ZADCS1082V ..............................................................................8
1.3. Package Pin Assignment ZADCS1042 / ZADCS1042V ..............................................................................9
1.4. Package Pin Assignment ZADCS1022 / ZADCS1022V ............................................................................10
1.5. Electrical Characteristics ............................................................................................................................11
1.5.1. General Parameters.............................................................................................................................11
1.5.2. Specific Parameters of ZADCS10x2V versions (with Internal Reference) ..........................................12
1.5.3. Specific Parameters of basic ZADCS10x2 versions (without Internal Reference) ..............................13
1.5.4. Digital Pin Parameters .........................................................................................................................13
1.6. Typical Operating Characteristics...............................................................................................................14
Detailed Description ..........................................................................................................................................15
2
2.1. General Operation......................................................................................................................................15
2.2. Analog Input................................................................................................................................................16
2.3. Internal & External Reference ....................................................................................................................18
2.4. Digital Interface...........................................................................................................................................18
2.5. Power Dissipation.......................................................................................................................................22
3
4
Layout................................................................................................................................................................24
Package Drawing ..............................................................................................................................................25
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
4 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
List of Figures
Figure 1 Package Pin Assignment for ZADCS1082 & ZADCS1082V........................................................................8
Figure 2 Package Pin Assignment for ZADCS1042 & ZADCS1042V........................................................................9
Figure 3 Package Pin Assignment for ZADCS1022 & ZADCS1022V......................................................................10
Figure 4: Basic application schematic for ZADCS1082V .........................................................................................15
Figure 5: Basic application schematic for ZADCS1082............................................................................................15
Figure 6: Input voltage range in unipolar mode........................................................................................................16
Figure 7: Input voltage range for bipolar mode ........................................................................................................16
Figure 8: Block diagram of input multiplexer ............................................................................................................17
Figure 9: Equivalent input circuit during sampling....................................................................................................17
Figure 10: Reference Adjust Circuit..........................................................................................................................18
Figure 11: 24-Clock External Clock Mode Timing (fSCLK ≤ 3.3MHz).........................................................................19
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission ................................................19
Figure 13: 16-Clock External Clock Mode Conversion.............................................................................................20
Figure 14: 13-Clock External Clock Mode Conversion.............................................................................................20
Figure 15 Detailed Timing Diagram..........................................................................................................................21
Figure 16: Unipolar Transfer Function......................................................................................................................22
Figure 17: Bipolar Transfer Function........................................................................................................................22
Figure 18: Supply Current versus Sampling Rate....................................................................................................24
Figure 19: Optimal Power-Supply Grounding System..............................................................................................24
Figure 20: Package Outline Dimensions ..................................................................................................................25
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
5 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
List of Tables
Table 1: Absolute Maximum Ratings..........................................................................................................................7
Table 2: Pin list ZADCS1082 / ZADCS1082V............................................................................................................8
Table 3: Pin list ZADCS1042 / ZADCS1042V............................................................................................................9
Table 4: Pin list ZADCS1022 / ZADCS1022V..........................................................................................................10
Table 5: Channel selection in Single Ended Mode...................................................................................................15
Table 6: Channel selection in Differential Mode.......................................................................................................15
Table 7 Control Byte Format ....................................................................................................................................19
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; OP = OPmin … OPmax) ...............................................21
Table 9: Package Dimensions for ZADC1082 devices (mm)...................................................................................25
Table 10: Package Dimensions for ZADC1042 devices (mm).................................................................................25
Table 11: Package Dimensions for ZADC1022 devices (mm).................................................................................25
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
6 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1
General Device Specification
1.1. Absolute Maximum Ratings (Non Operating)
Symbol
Parameter
Min
Max
Unit Note
VDD-GND
VDD to AGND, DGND
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
6
V
VAGND-DGND
AGND to DGND
0.3
V
CH0 – CH7, COM to AGND, DGND
VREF, VREFADJ to AGND
Digital Inputs to DGND
Digital Outputs to DGND
Digital Output Sink Current
VDD+0.3
VDD+0.3
6
V
V
V
VDD+0.3
25
V
mA
Iin
Input current into any pin except supply pins (Latch-Up)
Electrostatic discharge – Human Body Model (HBM)
Maximum Junction Temperature
Operating Temperature Range
Storage temperature
-100
100
mA
1
VHBM
JCT
OP
STG
lead
H
2000
V
+150°
+85
°C
-25
-65
+150
°C
Lead Temperature 100%Sn
JEDEC-J-STD-20C 260
°C
2
Humidity non-condensing
Ptot
Rthj
Total power dissipation
250
100
mW
K/W
Thermal resistance of Package
SSOP20 / 5.3mm
Table 1: Absolute Maximum Ratings
1
HBM: C = 100pF charged to VHBM with resistor R = 1.5k in series, valid for all pins
Level 4 according to JEDEC-020A is guaranteed
2
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
7 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.2. Package Pin Assignment ZADCS1082 / ZADCS1082V
Package
Name
Direction Type
Description
pin number
1
nCS
IN
IN
CMOS Digital
Active Low Chip Select
Serial Data Input
2
DIN
CMOS Digital
SUPPLY
SUPPLY
Analog
3
DGND
AGND
VREF
COM
CH0
Digital Ground
4
Analog Ground
5
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 4
Analog Input Channel 5
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 3
Analog Input Channel 2
Input to Reference Buffer Amplifier
Positive Supply
6
Analog
7
Analog
8
CH1
Analog
9
CH4
Analog
10
11
12
13
14
15
16
17
18
19
20
CH5
Analog
CH7
Analog
CH6
Analog
CH3
Analog
CH2
Analog
REFADJ
VDD
Analog
SUPPLY
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
nSHDN
DOUT
SSTRB
SCLK
IN
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
Table 2: Pin list ZADCS1082 / ZADCS1082V
nCS
DIN
SCLK
SSTRB
DOUT
nSHDN
VDD
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1082V,
No connect on ZADCS1082
CH2
CH3
CH6
CH7
CH1
CH4
CH5
Figure 1 Package Pin Assignment for ZADCS1082 & ZADCS1082V
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
8 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.3. Package Pin Assignment ZADCS1042 / ZADCS1042V
Package
Name
Direction Type
Description
pin number
1
nCS
IN
IN
CMOS Digital
Active Low Chip Select
Serial Data Input
2
DIN
CMOS Digital
SUPPLY
SUPPLY
Analog
3
DGND
AGND
VREF
COM
CH0
Digital Ground
4
Analog Ground
5
I/O
IN
IN
IN
IN
IN
I/O
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 3
Analog Input Channel 2
Input to Reference Buffer Amplifier
Positive Supply
6
Analog
7
Analog
8
CH1
Analog
9
CH3
Analog
10
11
12
13
14
15
16
CH2
Analog
REFADJ
VDD
Analog
SUPPLY
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
nSHDN
DOUT
SSTRB
SCLK
IN
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
Table 3: Pin list ZADCS1042 / ZADCS1042V
nCS
DIN
SCLK
SSTRB
DOUT
nSHDN
VDD
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1042V,
No connect on ZADCS1042
CH2
CH3
CH1
Figure 2 Package Pin Assignment for ZADCS1042 & ZADCS1042V
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
9 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.4. Package Pin Assignment ZADCS1022 / ZADCS1022V
Package
Name
Direction Type
Description
pin number
1
nCS
IN
IN
CMOS Digital
Active Low Chip Select
Serial Data Input
2
DIN
CMOS Digital
SUPPLY
3
DGND
AGND
VREF
COM
Digital Ground
4
SUPPLY
Analog Ground
5
I/O
IN
Analog
Reference Buffer Output / External Reference Input
Ground reference for analog inputs in single ended mode
Analog Input Channel 0
Analog Input Channel 1
Input to Reference Buffer Amplifier
Positive Supply
6
Analog
7
CH0
IN
Analog
8
CH1
IN
Analog
9
REFADJ
VDD
I/O
Analog
10
11
12
13
14
SUPPLY
nSHDN
DOUT
SSTRB
SCLK
IN
CMOS Digital
CMOS Digital
CMOS Digital
CMOS Digital
Active Low Shutdown
OUT
OUT
IN
Serial Data Output
Serial Strobe Output
Serial Clock Input
Table 4: Pin list ZADCS1022 / ZADCS1022V
nCS
DIN
SCLK
SSTRB
DOUT
nSHDN
VDD
DGND
AGND
VREF
COM
CH0
REFADJ on ZADCS1022V,
No connect on ZADCS1022
CH1
Figure 3 Package Pin Assignment for ZADCS1022 & ZADCS1022V
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
10 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.5. Electrical Characteristics
1.5.1. General Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); VREF = 2.500V applied to VREF pin; OP = OPmin
…
OPmax
)
Parameter
DC Accuracy
Resolution
Symbol Conditions
Min
Typ
10
Max
Unit
Bits
LSB
Bits
LSB
ZADCS1082 / ZADCS1082V
Relative Accuracy
INL
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
0.4
0.4
No Missing Codes
Differential Nonlinearity
NMC
DNL
10
ZADCS1082 / ZADCS1082V
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
Offset Error
LSB
LSB
0.5
0.5
0.25
2.0
2.0
Gain Error
Gain Temperature Coefficient
ppm/°C
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD
61
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Conversion Rate
THD
Up to the 5th harmonic
-3dB roll off
-72
dB
SFDR
74
dB
3.8
MHz
Sampling Time
(= Track/Hold Acquisition Time)
Ext. Clock = 3.3MHz, 2.5 clocks/
acquisition
tACQ
0.758
µs
µs
Ext. Clock = 3.3MHz, 10 clocks/
conversion
3.03
3.50
Conversion Time
tCONV
Int. Clock = 3.3MHz +/- 12% tolerance 2.75
µs
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
External Clock Frequency
Internal Clock Frequency
0.1
3.3
MHz
MHz
2.81
3.3
3.58
Analog Inputs
Unipolar, COM = 0V
0 to VREF
VREF / 2
16
Input Voltage Range, Single-
Ended and Differential
V
Bipolar, COM = VREF/2
Input Capacitance
pF
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
11 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.5.2. Specific Parameters of ZADCS10x2V versions (with Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
TA = + 25°C
Min
Typ
Max
Unit
Internal Reference at VREF
VREF Output Voltage
2.480 2.500 2.520
30
V
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation
mA
ppm/°C
mV
µF
± 30
0.35
± 50
0 to 0.2mA output load
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
4.7
0.047
µF
%
1.5
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VDD +
50mV
VREF Input Voltage Range
1.0
V
VREF Input Current
VREF = 2.5V
180
14
215
µA
k
µA
VREF Input Resistance
Shutdown VREF Input Current
11.5
0.1
VDD-
0.5
REFADJ Buffer Disable Threshold
V
External Reference at VREF_ADJ
Reference Buffer Gain
2.00
VREF_ADJ Input Current
±80
0.1
µA
µA
Full Power Down
VREFADJ Input Current
Full Power-Down mode
Power Requirements
Positive Supply Voltage
Positive Supply Current
VDD
2.7
5.25
1.0
1.4
300
4.0
1.3
1.6
300
4.0
V
Operating Mode ext. VREF
0.85
1.3
mA
mA
Operating Mode int. VREF
Fast Power-Down
IDD
IDD
VDD=3.6V
VDD=5.2V
ZADCS1082VI
ZADCS1042VI
ZADCS1022VI
250
0.5
µA
Full Power-Down
Positive Supply Current
Operating Mode ext. VREF
Operating Mode int. VREF
Fast Power-Down
1.00
1.40
250
0.5
mA
mA
ZADCS1082VI
ZADCS1042VI
ZADCS1022VI
µA
Full Power-Down
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
12 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.5.3. Specific Parameters of basic ZADCS10x2 versions (without Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
V
External Reference at VREF
VDD +
50mV
VREF Input Voltage Range
1.0
VREF Input Current
VREF = 2.5V
180
14
215
µA
k
µA
µF
VREF Input Resistance
11.5
4.7
Shutdown VREF Input Current
Capacitive Bypass at VREF
0.1
Power Requirements
Positive Supply Voltage
VDD
2.7
5.25
1.0
V
Positive Supply Current
ZADCS1082I
ZADCS1042I
Operating Mode
Full Power-Down
Operating Mode
Full Power-Down
0.85
0.5
IDD
IDD
VDD = 3.6V
µA
4.0
1.3
4.0
ZADCS1022I
Positive Supply Current
ZADCS1082I
ZADCS1042I
1.00
0.5
VDD = 5.25V
µA
ZADCS1022I
1.5.4. Digital Pin Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); OP = OPmin … OPmax
)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
1.9
3.3
V
V
V
V
V
Logic High Level
Logic Low Level
VIH
VIL
0.7
1.4
Hysteresis
VHyst
IIN
0.7
Input Leakage
Input Capacitance
VIN = 0V or VDD
± 0.1
5
± 1.0
µA
pF
CIN
Digital Outptus (DOUT, SSTRB)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
3.5
5.5
4
8.5
mA
mA
mA
mA
µA
Output High Current
IOH
VOH= VDD – 0.5V
VOL= 0.4V
10.8
11.5
15.3
± 1.0
Output Low Voltage
IOL
6.4
Three-State Leakage Current
ILeak
nCS = VDD
nCS = VDD
± 0.1
5
Three-State Output Capacitance
COUT
pF
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
13 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
1.6. Typical Operating Characteristics
Integral Nonlinearity vs. Code
Differential Nonlinearity vs. Code
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
640
768
896 1024
0
128
256
384
512
640
768
896 1024
Code
Code
IDDstatic vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
IDD vs. VDD
700
1500
1350
1200
1050
900
750
600
450
300
150
0
IDDactive (converting)
650
600
550
500
IDDstatic
External VREF
Internal VREF
4.8
-40
-20
0
20
40
60
80
100
2.7
3.4
4.1
5.5
VDD (V)
Temperatur (°C)
IDDactive (converting) vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
VREF vs. Temperature
1050
1000
950
2.501
2.500
2.499
2.498
900
-25
0
25
50
75
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperatur (°C)
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
14 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
2
Detailed Description
2.1. General Operation
The ZADCS10x2 family is a set of classic successive approximation register (SAR) type converters. The
architecture is based on a capacitive charge redistribution DAC merged with a resistor string DAC building a
hybrid converter with excellent monotonicity and DNL properties. The Sample & Hold function is inherent to
the capacitive DAC. This avoids additional active components in the signal path that could distort the input
signal or introduce errors.
All devices in the ZADCS10x2 family build on the same converter core and differ only in the number of input
channels and the availability of an internal reference voltage generator. The ZADCS10x2V versions are
equipped with a highly accurate internal 1.25V bandgap reference which is available at the VREFADJ pin. The
bandgap voltage is further amplified by an internal buffer amplifier to 2.50V that is available at pin VREF. All
other versions come without the internal reference and the internal buffer amplifier. They require an external
reference supplied at VREF, with the benefit of considerably lower power consumption.
A basic application schematic for ZADC1082V is shown in Figure 4, for ZADCS1082 in Figure 5.
ZADCS1082V can also be operated with an external reference, if VREFADJ is tied to VDD.
µC
µC
ZADCS1082V
ZADCS1082
+2.7V to 5.25V
+2.7V to 5.25V
nCS
SCLK
SSTRB
DOUT
nSHDN
VDD
nCS
SCLK
SSTRB
DOUT
nSHDN
VDD
1
2
20
19
18
17
16
15
14
13
12
11
1
2
20
19
18
17
16
15
14
13
12
11
DIN
DIN
DGND
AGND
VREF
COM
CH0
DGND
AGND
VREF
COM
CH0
3
3
4
4
≥ 4.7µF
≥ 4.7µF
5
5
47nF
0.1µF
10µF
0.1µF
10µF
VREFADJ
CH2
n.c.
6
6
CH2
7
7
CH1
CH3
CH1
CH3
8
8
CH4
CH6
CH4
CH6
9
9
CH5
CH7
CH5
CH7
10
10
Single-ended or differential
analog inputs, 0V … +2.5V
Single-ended or differential
analog inputs, 0V … +VREF
Figure 4: Basic application schematic for ZADCS1082V
Figure 5: Basic application schematic for ZADCS1082
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
IN+
IN-
IN-
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN+ IN-
IN+
IN+ IN-
IN- IN+
IN+
IN-
IN+ IN-
IN- IN+
IN+
IN-
IN+ IN-
IN- IN+
IN+
IN-
IN- IN+
IN+
IN-
IN+
IN-
IN+ IN-
Table 5: Channel selection in Single Ended Mode
Table 6: Channel selection in Differential Mode
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
Data Sheet
15 of 26
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
October 12, 2011
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
2.2. Analog Input
The analog input to the converter is fully differential. Both converter input signals IN+ and IN– (see Functional
Block diagram at front page) get sampled during the acquisition period enabling the converter to be used in
fully differential applications where both signals can vary over time.
The ZADCS10x2 family converters do not require that the negative input signal be kept constant within
± 0.5LSB during the entire conversion as is commonly required by converters featuring pseudo differential
operation only.
The input signals can be applied single ended, referenced to the COM pin, or differential, using pairs of the
input channels. The desired configuration is selectable for every conversion via the Control-Byte received on
DIN pin of the digital interface (see further description below)
A block diagram of the input multiplexer is shown in Figure 8. Table 5 and Table 6 show the relationship of the
Control-Byte bits A2, A1, A0 and SGL/DIF to the configuration of the analog multiplexer. The entire table
applies only to ZADCS1082 devices. For ZADCS1042 devices bit A1 is don’t care, for ZADCS1022 devices
A1 and A0 are don’t care.
Both input signals IN+ and IN– are generally allowed to swing between –0.2V and VDD+0.2V. However,
depending on the selected conversion mode – uniploar or bipolar – certain input voltage relations can limit the
output code range of the converter.
In unipolar mode the voltage at IN+ must exceed the voltage at IN– to obtain codes unequal to 0x00. The
entire 8 bit transfer characteristic is then covered by IN+ if IN+ ranges from IN– to (IN–+Vref). Any voltage on
IN+>(IN–+Vref) results in code 0xFF. Code 0xFF is not reached, if (IN–+Vref) > VDD + 0.2V because the input
voltage is clamped at VDD + 0.2V by ESD protection devices.
VIN+
VCM
1.5*VREF
VREF
0xFF
¾
VREF
Code Range
VCM Range
0.5*VREF
¼ VREF
0V
0x00
0V
VDD-VREF VIN-
-VREF/2
0V
+VREF/2
VDIFF
Figure 6: Input voltage range in unipolar mode
Figure 7: Input voltage range for bipolar mode
The voltage at IN– can range from -0.2V … ½ VREF without limiting the Code Range, assuming the fore
mentioned VDD condition is true. See also Figure 6 for input voltage ranges in unipolar conversion mode.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
16 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
In bipolar mode, IN+ can range from (IN– - Vref/2) to
(IN–+Vref/2) keeping the converter out of code
saturation. For instance, if IN– is set to a constant DC
voltage of Vref/2, then IN+ can vary from 0V to VREF to
cover the entire code range. Lower or higher voltages of
IN+ keep the output code at the minimum or maximum
code value.
Shown configuration
A2 … A0 = 0x000
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Figure 7 shows the input voltage ranges in bipolar mode
when IN– is set to a constant DC voltage.
IN+
As explained before, converters out of the ZADCS10x2
family can also be used to convert fully differential input
signals that change around a common mode input
voltage.
Converter
IN-
The bipolar mode is best used for such purposes since
it allows the input signals to be positive or negative in
relation to each other.
The common mode level of a differential input signal is
calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code
clipping or over steering of the converter, the common
mode level can change from ¼ VREF … ¾ VREF. Within
this range the peak to peak amplitude of the differential
input signal can be ± VREF/2.
COM
The average input current on the analog inputs depends
on the conversion rate. The signal source must be
capable of charging the internal sampling capacitors
(typically 16pF on each input of the converter: IN+ and
IN–) within the acquisition time tACQ to the required
accuracy. The equivalent input circuit in sampling mode
is shown in Figure 9.
SGL/DIF = HIGH
See Table 5 & Table 6
for Coding Schemes
Figure 8: Block diagram of input multiplexer
The following equation provides a rough hand calculation for a source impedance RS that is required to settle
out a DC input signal referenced to AGND with 8 bit accuracy in a given acquisition time
tACQ
RS
RSW
7CIN
For example, if fSCLK = 3.3MHz, the acquisition
time is tACQ = 758ns. Thus the output impedance
of the signal source RS must be less than
CHOLD+
16pF
RSW
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
IN+
CIN
4pF
3kΩ
758ns
RS
3kΩ 2.41kΩ
AGND
7 20pF
VDC
CHOLD-
RSW
If the output impedance of the source is higher
than the calculated maximum RS the acquisition
time must be extended by reducing fSCLK to
ensure 8 bit accuracy. Another option is to add a
capacitor of > 20nF to the individual input.
Although this limits the bandwidth of the input
signal because an RC low pass filter is build
together with the source impedance, it may be
COM
IN-
Channel
Multiplexer
CIN
4pF
16pF
3kΩ
AGND
Figure 9: Equivalent input circuit during sampling
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
Data Sheet
17 of 26
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
October 12, 2011
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
useful for certain applications.
The small-signal bandwidth of the input tracking circuitry is 3.8MHz. Hence it is possible to digitize high-speed
transient events and periodic signals with frequencies exceeding the ADC’s sampling rate. This allows the
application of certain under-sampling techniques like down conversion of modulated high frequency signals.
Be aware that under-sampling techniques still require a bandwidth limitation of the input signal to less than the
Nyquist frequency of the converter to avoid aliasing effects. Also, the output impedance of the input source
must be very low to achieve the mentioned small signal bandwidth in the overall system.
2.3. Internal & External Reference
ZADCS10x2V family members are equipped with a highly accurate internal 2.5V reference voltage source.
The voltage is generated from a trimmed 1.25V bandgap with an internal buffer that is set to a gain of 2.00.
The bandgap voltage is supplied at VREFADJ with an output impedance of 20kΩ. An external capacitor of
47nF at VREFADJ is useful to further decrease noise on the internal reference.
The VREFADJ pin also provides an opportunity to externally adjust the bandgap voltage in a limited range
(see Figure 10) as well as the possibility to overdrive the internal bandgap with an external 1.25V reference.
The internal bandgap reference and the VREF buffer can be shut down completely by setting VREFADJ to
VDD. This reduces power consumption of the ZADCS10x2V devices and allows the supply of an external
reference at VREF.
Basic ZADCS10x2 devices do not contain the internal bandgap
or the VREF buffer. An external reference must be supplied all
VDD = +2.7V … +5.25V
the time at VREF.
The value of the reference voltage at VREF sets the input range
of the converter and the analog voltage weight of each digital
ZADCS10x2V
code. The size of the LSB (least significant bit) is equal to the
value of VREF (reference to AGND) divided by 1024. For
example at a reference voltage of 2.500V, the voltage level of a
LSB is equal to 9.766mV.
510kΩ
VREFADJ
47nF
The average current consumption at VREF depends on the value
of VREF and the sampling frequency. Two effects contribute to
Figure 10: Reference Adjust Circuit
the current at VREF, a resistive connection from VREF to AGND
and charge currents that result from the switching and recharging of the capacitor array (CDAC) during
sampling and conversion. For an external reference of 2.5V the input current at VREF is approximately
100µA.
2.4. Digital Interface
All devices out of the ZADCS10x2 family are controlled by a 4-wire serial interface that is compatible to SPI™,
QSPI™ and MICROWIRE™ devices without external logic. Any conversion is started by sending a control
byte into DIN while nCS is low. A typical sequence is shown in Figure 11.
The control byte defines the input channel(s), unipolar or bipolar operation and output coding, single-ended or
differential input configuration, external or internal conversion clock and the kind of power down that is
activated after the completion of a conversion. A detailed description of the control bits can be obtained from
Figure 11. As it can also be seen in Figure 11 the acquisition of the input signal occurs at the end of the
control byte for 2.5 clock cycles. Outside this range, the Track & Hold is in hold mode.
The conversion process is started, with the falling clock edge (SCLK) of the eighth bit in the control byte. It
takes twelve clock cycles to complete the conversion and one additional cycle to shift out the last bit of the
conversion result. During the remaining seven clock cycles the output is filled with zeros in 24-Clock
Conversion Mode. Depending on what clock mode was selected, either the external SPI clock or an internal
clock is used to drive the successive approximation. Figure 12 shows the Timing for Internal Clock Mode.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
18 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
nCS
tACQ
1
8
1
8
1
8
SCLK
DIN
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
(Start)
Idle
Acquire
Conversion
Idle
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3
(MSB)
B2
B1 B0
(LSB)
Figure 11: 24-Clock External Clock Mode Timing (fSCLK ≤ 3.3MHz)
nCS
1
8
1
8
1
8
SCLK
DIN
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
(Start)
Idle
Acquire
Conversion
Result Output
Acquire
SSTRB
DOUT
tCONV
Zero filled
B9 B8 B7 B6 B5 B4 B3
B2
B1 B0
(LSB)
(MSB)
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
BIT
Name
Description
7
START
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
(MSB)
6
5
4
A2
A1
A0
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer.
For further details on the decoding see also Table 5 and Table 6.
3
UNI/BIP
Output Code Bit. The value of the bit determines conversion mode and output code format.
‘1’
‘0’
=
=
unipolar - straight binary coding
bipolar - two’s complement coding
2
SGL/DIF
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’
‘0’
=
=
single ended - all channels CH0 … CH7 measured referenced to COM
differential - the voltage between two channels is measured
1
PD1
Power Down and Clock Mode Select Bits
0 (LSB) PD0
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full Power-Down
Fast Power-Down
Internal clock mode
External clock mode
Table 7 Control Byte Format
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
19 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
nCS
1
8
1
8
1
8
1
SCLK
DIN
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
(Start)
Idle
Acquire
Conversion
Idle
Acquire
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3
(MSB)
B2
B1 B0
(LSB)
B9 B8
Figure 13: 16-Clock External Clock Mode Conversion
nCS
1
8
13
1
13
1
SCLK
DIN
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
S
A2 A1 A0 UNI/ SGL/ PD1 PD0
BIP DIF
S
A2 A1 A0
Conversion
(Start)
Idle
Acquire
Conversion
Acquire
SSTRB
DOUT
Zero filled
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B9 B8 B7 B6 B5 B4 B3 B2
(MSB)
(LSB)
Figure 14: 13-Clock External Clock Mode Conversion
Internal Clock Mode
In Internal Clock Mode, the conversion starts at the falling clock edge of the eighth control bit just as in
External Clock Mode. However, there are no further clock pulses required at SCLK to complete the
conversion. The conversion clock is generated by an internal oscillator that runs at approximately 3.3MHz.
While the conversion is running, the SSTRB signal is driven LOW. As soon as the conversion is complete,
SSTRB is switched to HIGH, signalling that the conversion result can be read out on the serial interface. To
shorten cycle times ZADCS10x2 family devices allow interleaving of the read out process with the
transmission of a new control byte. Thus it is possible to read the conversion result and to start a new
conversion with just two consecutive byte transfers, instead of thee bytes that would have to be send without
the interleaving function. While the IC is performing a conversion in Internal Clock Mode, the Chip Select
signal (nCS) may be tied HIGH allowing other devices to communicate on the bus. The output driver at DOUT
is switched into a high impedance state while nCS is HIGH. The conversion time tCONV may vary in the
specified limits depending on the actual VDD and temperature values.
16-Clocks per Conversion
Interleaving of the data read out process and transmission of a new Control Byte is also supported for
External Clock Mode operation. Figure 13 shows the transmission timing for conversion runs using 16 clock
cycles per run.
13-Clocks per Conversion
ZADCS10x2 family devices do also support a 13 clock cycle conversion mode (see Figure 14). This is the
fastest conversion mode possible. In fact, the specified converter sampling rate of 250ksps will be reached in
this mode, provided the clock frequency is set to 3.3MHz. Usually micro controllers do not support this kind of
13 bit serial communication transfers. However, specifically designed digital state machines implemented in
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
20 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this
operation mode.
Digital Timing
In general the clock frequency at SCLK may vary from 0.1MHz to 3.3MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the
falling clock edge of the eighth bit in the Control Byte. Otherwise the signal that was captured during
sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the
digital interface is provided in Table 8 and Figure 15.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SCLK Periode
tSCLK
303.0
ns
SCLK Pulse Width High
SCLK Pulse Width Low
tSCLKhigh
tSCLKlow
tDinSetup
tDinHold
151.5
151.5
ns
ns
DIN to SCLK Setup
DIN to SCLK Hold
30
10
30
ns
ns
ns
nCS Fall to SCLK Setup
tnCSSetup
SCLK Fall to
DOUT & SSTRB Hold
tOutHold
CLoad = 20pF
CLoad = 20pF
CLoad = 20pF
CLoad = 20pF
10
ns
ns
ns
SCLK Fall to
DOUT & SSTRB Valid
tOutValid
tOutDisable
tOutEnable
tnCSHigh
40
60
60
nCS Rise to
DOUT & SSTRB Disable
10
nCS Fall to
DOUT & SSTRB Enable
ns
ns
nCS Pulse Width High
100
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; OP = OPmin … OPmax
)
nCS
tSCLKhigh
tnCSSetup
tSCL
tSCLKlow
tOutValid
SCLK
tDINsetup
tDINhold
DIN
SSTRB
DOUT
tnCSHig
tOutEnable
tOutDisable
tOutHold
tOutEnable
Figure 15 Detailed Timing Diagram
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
21 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Output Code Format
ZADCS10x2 family devices do all support unipolar and bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V to 0xFF for an input
voltage difference of VREF (Full Scale = FS). The first code transition (0x00 0x01) occurs at a voltage
equivalent to ½ LSB, the last (0xFE 0xFF) at VREF-1.5 LSB. See also Figure 16 for details. In bipolar
mode a two’s complement coding is applied. Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in Figure 17.
Output Code
Output Code
ZS = V(IN-)
11 … 111
+ FS = ½VREF +V(IN-)
01 … 111
01 … 110
11 … 110
- FS = -½VREF +V(IN-)
VREF
11 … 101
1LSB =
1024
00 … 011
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
FS = VREF +V(IN-
VREF
1LSB =
1024
00 … 010
00 … 001
00 … 000
10 … 001
10 … 000
0
1
2
3
FS
-FS
ZS
+FS
(ZS)
FS-3/2 LSB
+FS-3/2 LSB
Input Voltage (LSB)
Input Voltage (LSB)
Figure 16: Unipolar Transfer Function
Figure 17: Bipolar Transfer Function
2.5. Power Dissipation
The ZADCS10x2 family offers three different ways to save operating current between conversions. Two
different software controlled power down modes can be activated to automatically shut-down the device after
completion of a conversion. They differ in the amount of circuitry that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to
less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with
ZADCS10x2V devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the
VREFADJ output buffer are kept alive while all other internal analog circuitry is shut down. The benefit of Fast
Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is
basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20kΩ
resistor and the external buffer capacitor of 47nF is not discharged in Fast Power-Down Mode. The settling
time of the low pass at VREFADJ is about 7ms to reach 10 bit accuracy. The Fast Power Down mode omits
this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power
down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly
transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device.
In all application cases where an external reference voltage is supplied (basic ZADCS10x2 and ZADCS10x2V
with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid.
Fast Power-Down and Full Power-Down Mode do not show any difference in this configuration.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
22 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Hardware Power Down
The third power down mode is called Hardware Power-Down. It is initiated by pulling the nSHDN pin LOW. If
this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode.
The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during
normal operation. This ensures the lowest possible power consumption in power down mode.
General Power Considerations
Even without activating any power down mode, the devices out of the ZADCS10x2 family reduce their power
consumption between conversions automatically. The comparator, which contributes a considerable amount
to the overall current consumption of the device, is shut off as soon as a conversion is ended. It gets turned on
at the start of the next acquisition period. This explains the difference between the IDDstatic and IDDactive
measurements shown in chapter 1.6 Typical Operating Characteristics.
The average current consumption of the device depends very much on the sampling frequency and the type
of protocol used to communicate with the device.
In order to achieve the lowest power consumption at low sampling frequencies, it is suggested to keep the
conversion clock frequency at the maximum level of 3.3MHz and to power down the device between
consecutive conversions. Figure 18 shows the characteristic current consumption of the ZADCS10x2 family
with external reference supply versus Sampling Rate
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
23 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
3
Layout
To achieve optimum conversion performance care must be taken in design and layout of the application
board. It is highly recommended to use printed circuit boards instead of wire wrap designs and to establish a
single point star connection ground system towards AGND (see Figure 19).
For optimal noise performance the star point should be located very close to the AGND pin of the converter.
The ground return to the power supply should be as short as possible and low impedance.
All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin
of the device should be connected to this ground point too. Any other digital ground system should be kept
apart as far as possible and connect on the power supply point only.
Analog and digital signal domains should also be separated as well as possible and analog input signals
should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that
allow smaller vertical distances between the ground plane and the shielded signals do generally show a better
performance than two-layer boards.
The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible,
the switching of any high power devices or nearby digital logic should be avoided during the sampling phase
of the converter.
Optional
R = 10Ω
Current consumption vs. Sample Rate
External Clock Mode, External VREF, fSCLK = 3.3MHz
VDD1
(+2.7 … +5.25V)
10000
ZADCS10x2
Family
1000
100
10
COM
DGND
Other
Digital
Circuitry
DGND
DVDD
GND
1
VDD2
1
10
100
1000
Sample Rate (ksps)
Figure 18: Supply Current versus Sampling Rate
Figure 19: Optimal Power-Supply Grounding System
The fully differential internal architecture of the ZADCS10x2 family ensures very good suppression of power
supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the
power supply that occur shortly before the latching of the comparator output. It is therefore recommended to
bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF
(electrolytic). In case of a noisy supply, an additional series resistor of 5 to 10 ohms can be used to low-pass
filter the supply voltage. The reference voltage should always be bypassed with capacitors of 0.1µF (ceramic)
and ≥ 4.7µF (electrolytic) as close as possible to the VREF pin. If VREF is provided by an external source, any
series resistance in the VREF supply path can cause a gain error of the converter. During conversion, a DC
current of about 100µA is drawn through the VREF pin that could cause a noticeable voltage drop across the
resistance.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
24 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
4
Package Drawing
ZADCS1082 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 20
and Table 9. ZADCS1042 and ZADCS1022 devices apply respective 16-pin and 14-pin SSOP-packages.
Their dimensions are specified in Table 9 and Table 10.
Figure 20: Package Outline Dimensions
Symbol
Nominal
A
A1
A2
bP
c
D
E
enom
0.65
HE
7.80
7.90
LP
Z
k
4°
8°
1.86 0.13 1.73 0.30 0.15 7.20 5.30
Maximum 1.99 0.21 1.78 0.38 0.20 7.33 5.38
Minimum 1.73 0.05 1.68 0.25 0.09 7.07 5.20
Table 9: Package Dimensions for ZADC1082 devices (mm)
0.74
7.65 0.63
0.25 0°
Symbol
A
A1
A2
bP
c
D
E
enom
HE
LP
Z
k
Nominal
1.86 0.13 1.73 0.30 0.15 6.20 5.30
7.80
4°
Maximum 1.99 0.21 1.78 0.38 0.20 6.07 5.38
Minimum 1.73 0.05 1.68 0.25 0.09 6.33 5.20
Table 10: Package Dimensions for ZADC1042 devices (mm)
0.65 7.90
7.65 0.63
0.89
10°
0.25 0°
Symbol
A
A1
A2
bP
c
D
E
enom
HE
LP
Z
k
Nominal
1.86 0.13 1.73 0.30 0.15 6.20 5.30
7.80
4°
Maximum 1.99 0.21 1.78 0.38 0.20 6.33 5.38
Minimum 1.73 0.05 1.68 0.25 0.09 6.07 5.20
0.65 7.90
7.65 0.63
1.22
10°
0.25 0°
Table 11: Package Dimensions for ZADC1022 devices (mm)
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
25 of 26
ZADCS1082/1042/1022
10-Bit, 250ksps, ADC Family
Sales and Further Information
www.zmdi.com
adc@zmdi.com
Zentrum Mikroelektronik
ZMD America, Inc.
8413 Excelsior Drive
Suite 200
Madison, WI 53717
USA
Zentrum Mikroelektronik
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Dresden AG
Grenzstrasse 28
01109 Dresden
Germany
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Taiwan
Japan
Phone +49 (0)351.8822.7232
Phone +1 (608) 829-1987
Phone +81.3.6895.7410
Phone +886 2 2377 8189
Fax
+49 (0)351.8822.87232
Fax
+1 (631) 549-2882
Fax
+81.3.6895.7301
Fax
+886 2 2377 8199
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are PRELIMINARY and subject to change without notice. Zentrum
Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true
and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages
of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD
AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with
or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
Data Sheet
October 12, 2011
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
26 of 26
相关型号：
©2020 ICPDF网 联系我们和版权申明